Integrated
Digital Digital Integrated
Circuits
Circuits
YuZhuo Fu
contact:[e-mail]
Office location417 room
WeiDianZi building,No 800 DongChuan
road,MinHang Campus
Introduction
Digital IC
3.CMOS Inverter
Introduction
Digital IC
outline
CMOS at a glance
CMOS static behavior
CMOS dynamic behavior
Power, Energy, and Energy Delay
Perspective tech.
Digital IC
3
Dynamic Power Consumption
(dis)charge process
CL is charged through pMOS on-resistance
CL is discharged through nMOS on-resistance
Power distribution
Charge processing:One part of Supply power is
dissipated in the pMOS transistor,another part is
dissipated in the charge CL
Discharge processing:all dissipated in the nMOS
transistor
Digital IC
4
Precise measure of dynamic power
cons
consumption
EVdd
dvout
= iVdd (t )Vdd dt = Vdd C L
dt
dt
0
0
Vdd
2
= C LVdd dvout = C LVdd
0
dvout
EC = iVdd (t )vout dt = C L
vout dt
dt
0
0
= CL
Vdd
v
out
0
Digital IC
dvout
2
C LVdd
=
2
5
Output voltages and supply current during
(dis)charge of CL
of
Energy dissipation is independent of the size
Power consumption is dependent of device switching
number.
charge
Digital IC
discharge
6
Power and Energy Figures of Merit
Power consumption in Watts
determines battery life in hours
Peak power
determines power ground wiring designs
power ground wiring designs
sets packaging limits
impacts signal noise margin and reliability analysis
Energy efficiency in Joules
rate at which power is consumed over time
Energy = power * delay
Joules = Watts * seconds
lower energy number means less power to perform a
energy number means less power to perform
computation at the same frequency
Digital IC
Power versus Energy
Power is height of curve
is height of curve
Watts
Lower power design could simply be slower
Approach 1
Approach 2
time
Energy is area under curve
Watts
Two approaches require the same energy
th
Approach 1
Approach 2
time
Digital IC
PDP and EDP
Power-delay product (PDP) = Pav * tp = (CLVDD2)/2
product (PDP)
(C
PDP is the average energy consumed per switching
event (Watts sec Joule)
event (Watts * sec = Joule)
lower power design could simply be a slower design
Energy-delay product (EDP) = PDP * tp = Pav * tp 2
product (EDP) PDP tp
EDP is the average energy consumed multiplied by
the computation time required
the computation time required
takes into account that one can trade increased
delay for lower energy/operation(
delay for lower energy/operation(e.g.,via supply
voltage scaling that increases delay,but decreases
energy consumption)
Digital IC
PDP and EDP
E n e rg y -D e la y (n o rm a liz e d )
15
energy-delay
10
energy
delay
5
0
0.5
1
1.5
2
Vdd (V)
allows one to understand tradeoffs better
one to understand tradeoffs better
Digital IC
2.5
Understanding Tradeoffs
Understanding Tradeoffs
Which design is the best (fastest, coolest, both) ?
(fastest coolest both)
b
c
d
1/Delay
better
Digital IC
a
Understanding Tradeoffs
Understanding Tradeoffs
Which design is the best (fastest, coolest, both) ?
(fastest coolest both)
Lower
EDP
b
c
d
1/Delay
better
Digital IC
a
Where Does Power Go in CMOS?
Dynamic Power Consumption
Charging and Discharging Capacitors
Short Circuit Currents
Short Circuit Path between Supply Rails during
Switching
Leakage
Leaking diodes and transistors
Digital IC
13
CMOS Energy Power Equations
CMOS Energy & Power Equations
E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDDIleakage
f01 = P01 * fclock
P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage
Dynamic power
Short-circuit
power
Digital IC
Leakage
Leakage power
Lowering Dynamic Power
Capac
Capacitance:
Function of fan-out, wire
length, transistor sizes
Supply Voltage:
Has been dropping with
successive generations
Pdyn = CL VDD2 P01 f
Activity factor:
How often, on average, do
wires switch?
Digital IC
Clock frequency:
Increasing
Transistor Sizing for Minimum Energy
In
Out
Cg1
1
f
Cext
Goal: Minimize Energy of whole circuit
Design parameters: f and VDD
parameters:
tp tpref of circuit with f=1 and VDD =Vref
F
f
t p = t p 0 1 + + 1 +
f
VDD
3VDD
t p0
t pLH = ln(2) ReqnC = 0.69 *
(1 - VDD )C L
VDD VTE
4 I DSATn
Digital IC
16
Transistor Sizing (2)
Performance Constraint (=1)
tp
t pref
=
t p0
t p 0 ref
F
2 + f +
f VDD Vref VTE
=
(3 + F )
Vref VDD VTE
F
2 + f +
f
=1
(3 + F )
Energy for single Transition
2
E = VDD C g1 [(1 + )(1 + f ) + F ]
2
VDD 2 + 2 f + F
E
=
V 4+ F
Eref ref
Digital IC
17
Transistor Sizing (3)
E/Eref=f(f)
VDD=f(f)
4
1.5
3.5
F=1
3
normalized energy
2
vdd (V)
2.5
5
2
1.5
1
10
0.5
1
0.5
20
0
1
2
3
4
5
6
f
7
0
1
2
3
4
5
6
7
f
Digital IC
18
Sh Ci
Short Circuit Power Consumption
Vin
Isc
Vout
CL
Finite slope of the input signal causes a direct
slope of the input signal causes direct
current path between VDD and GND for a short
period of time during switching when both the
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Digital IC
Short path power consumption
Direct-Path Current power consumption
Digital IC
20
Short Circuit power consumption
Energy of ever switch activity
Edp = Vdd
I peak
2
Average power
t rise + Vdd
Pdp =
I peak
2
t fall =
t rise + t fall
2
t rise + t fall
2
Vdd I peak
Vdd I peak f
Short circuit occupy no more than 20% of dynamic
power
Digital IC
21
An example
An example
Assume rise/fall time
both are 300ps
Short circuit power:
300ps5V
0.14mA=0.21pJ
Dynamic power
30pF 5V 5V=0.75pJ
Digital IC
22
Short Circuit Currents Determinates
Short Circuit Currents Determinates
Esc = tsc VDD Ipeak P01
Psc = tsc VDD Ipeak f01
Duration and slope of the input signal, tsc
Ipeak determined by
the saturation current of the P and N transistors
which depend on their sizes process technology
which depend on their sizes, process technology,
temperature, etc.
strong function of the ratio between input and
function of the ratio between input and
output slopes
function of
a function of CL
Digital IC
Impact of
Impact of CL on Psc
Isc 0
Vin
Isc Imax
Vout
Vin
CL
Vout
CL
Large capacitive load
Small capacitive load
Output fall time significantly Output fall time substantially
tl
ll
larger than input rise time. smaller than the input rise
time.
Digital as IC
Ipeak a Function of CL
Function of
2.5
x 10-4
When load capacitance
is small, Ipeak is large.
CL = 20 fF
2
1.5
CL = 100 fF
1
0.5
CL = 500 fF
0
0
2
4
-0.5
time (sec)
500 psec input slope
Digital IC
6
x 10-10
Short circuit dissipation
is minimized by
matching the rise/fall
times of the input and
output signals - slope
engineering.
Psc as a Function of Rise/Fall
Function of Rise/Fall
Times
8
When load capacitance is small
(tsin/tsout > 2 for VDD > 2V) the
power is dominated by Psc
7
VDD= 3.3 V
6
5
4
VDD = 2.5 V
3
2
If VDD < VTn + |VTp| then Psc is
eliminated since both devices are
never on at the same time.
VDD = 1.5V
1
0
0
2
W/Lp = 1.125 m/0.25 m
W/Ln = 0.375 m/0.25 m
CL = 30 fF
tsin/tsout
4
Digital IC
normalized wrt zero input risetime dissipation
Leakage (Static) Power Consumption
VDD Ileakage
Vout
Drain junction
leakage
Sub-threshold current
Gate leakage
Sub-threshold current is the dominant factor.
current is the dominant factor
All increase exponentially with temperature!
Digital IC
Leakage as Function of
Leakage as a Function of VT
Continued scaling of supply voltage and the subsequent
sca
supp
subseque
scaling of threshold voltage will make subthreshold
conduction a dominate component of power dissipation.
10-7
ID ( A )
10-2
VT=0.4V
VT=0.1V
10-12
0
0.2
0.4
0.6
VGS (V)
(V)
Digital IC
0.8
1
An 90mV/decade VT
roll-off - so each
255mV increase in
VT gives 3 orders of
magnitude reduction
magnitude reduction
in leakage (but
adversely affects
performance)
performance)
TSMC Processes Leakage and VT
CL018
G
CL018
LP
CL018
ULP
CL018
HS
CL015
HS
CL013
HS
Vdd
1.8 V
1.8 V
1.8 V
2V
1.5 V
1.2 V
Tox (effective)
42
42
42
42
29
24
Lgate
0.16 m
0.16 m
0.18 m
0.13 m
0.11 m
0.08 m
IDSat (n/p)
(A/m)
600/260
500/180
320/130
780/360
860/370
920/400
20
1.60
0.15
300
1,800
13,000
0.42 V
0.63 V
0.73 V
0.40 V
0.29 V
0.25 V
30
22
14
43
52
80
Ioff (leakage)
(leakage)
(A/m)
VTn
FET Perf.
(GHz)
From MPR, 2000
Digital IC
Exponential Increase in Leakage
Currents
Currents
10000
Ileakage(nA/m)
1000
0.25
0.18
0.13
0.1
100
10
1
30
40
50
60
Digital IC
Temp(C)
70
80
90
100
110
From De,1999
Principles for Power Reduction
Principles for Power Reduction
Prime choice: Reduce voltage!
choice: Reduce voltage!
Recent years have seen an acceleration in
supply voltage reduction
supply voltage reduction
Design at very low voltages still open question
(0.6 0.9 V by 2010!)
Reduce switching activity
Reduce physical capacitance
Device Sizing: for F=20
fopt(energy)=3.53, fopt(performance)=4.47
Digital IC
31
Review: Energy & Power Equations
E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD
Ileakage
f01 = P01 * fclock
P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage
Dynamic power
(~90% today and
decreasing relativelly)
)
Short-circuit power
(~8% today and
decreasing
absolutely)
Digital IC
Leakage power
(~2% today and
increasing)
)
Impact of
Technology
Scaling
Introduction
Digital IC
Goals of Technology Scaling
Make things cheaper:
Want to sell more functions (transistors) per chip for
the same money
Build same products cheaper, sell the same part for
less money
Price of a transistor has to be reduced
But also want to be faster, smaller, lower power
Digital IC
Technology Scaling
Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating
frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per
generation
generation spans
years
Technology generation spans 2-3 years
Digital IC
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of Introduction
1999
Technology node [nm]
180
Supply [V]
1.5-1.8
Wiring levels
2000
2001
2004
2008
2011
2014
130
90
60
40
30
1.5-1.8
1.2-1.5
0.9-1.2
0.6-0.9
0.5-0.6
0.3-0.6
6 -7
6 -7
7
8
9
9-10
10
Max frequency
[GHz],Local-Global
1.2
1.6-1.4
2.1-1.6
3.5-2
7.1-2.5
11-3
14.9
-3.6
Max P power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
Digital IC
Technology Evolution (1999)
Technology Evolution (1999)
Digital IC
Technology Scaling (1)
M ini m um Featu re Size (m i c ron)
10
10
10
10
2
1
0
-1
-2
10
1960
1970
1980
1990
Year
Minimum Feature Size
Digital IC
2000
2010
Technology Scaling (2)
ec
Sca
Number of components per chip
Digital IC
Technology Scaling (3)
Sca
(3)
tp decreases by 13%/year
50% every 5 years!
every years!
Propagation Delay
Digital IC
Technology Scaling Models
gy
Full scaling(constant electrical)
Ideal model dimensions and voltage scale together
by the same factor S
Fixed voltage scaling
Most common model until recently- only dimensions
scale, voltages remain constant
General scaling
Most realistic for todays situation-voltages and
dimensions scale with different factors
Digital IC
Scaling Relationships for Long Channel Devices
Digital IC
Difference between long and short
channels
channels
ID
VDS =VDSAT
W
= nCox
L
= vsat CoxW (VGT
2
VDSAT
(VGS VT )VDSAT
2
VDSAT
)
2
Digital IC
43
Transistor Scaling
(velocity-saturated devices)
Digital IC
Processor Scaling
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
Digital IC
Processor Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
Digital IC
Processor Performance
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
ISSCC
Digital IC
2010 Outlook
Performance 2X/16 months
1 TIP (terra instructions/s)
30 GHz clock
Size
No of transistors: 2 Billion
Die: 40*40 mm
Power
10kW!!
Leakage: 1/3 active Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
Digital IC
Some interesting questions
What will cause this model to break?
When will it break?
Will the model gradually slow down?
Power and power density
Leakage
Process Variation
Digital IC
summary
CMOS at a glance
CMOS static behavior
VTC, noise margin, threshold voltage
CMOS dynamic behavior
Capacitance mosaic, delay
Ratio pMOS/nMOS:3.5,2.4,1.6
Optimizing inverter sizing
Power
Power mosaic
Optimizing dynamic power
power consideration
Short power consideration
Digital IC
50