Inverter-homework
3.CMOS 1. for a CMOS inverter, when the pMOS and
nMOS are long-channel devices ,or when the
supply voltage is low, velocity does not occur,
under these circumstances,Vm(Vin=Vout)=?
2. for a long channel model, please analysis a
first-order expression of the current as function
of Vgs and Vds in the reistive operation of a
pMOS transistor.
Digital IC
1
exercises
3.figure shows a generic nMOS inverter used a
resistive load, assume VDD=1.8V,
Rload=5K/10K/15K,please give a curve of I-V
characteristics both resistive and nMOS
Digital IC
Slide 2
exercises
4.figure shows a generic nMOS inverter
used a resistive load, assume VDD=1.8V,
pMOS width=24/14/4,please give a curve
of I-V characteristics both resistive and
nMOS
Digital IC
Slide 3
exercises
5.A novel inverter has the transfer
characteristics shown in figure. What are
the values of VIL,VIH,VOL, and VOH that
give best noise margins? What are these
high and low noise margin?
Digital IC
Slide 4
exercises
6.Graphically derive the transfer
characteristics for this buffer.why is it a
bad circuit idea
Digital IC
Slide 5
exercises
7.Consider an nMOS transistor in a
0.6um process with
W/L=4/2r(i.e.,1.2/0.6um), in this process,
the gate oxide thickness is 100A(1A=108cm), =3.9 =3.9*8.85*10-14F/cm, the
ox
0
mobility of electrons is 350cm2/V.s, the
threshold voltage is 0.7V. Plot IDS vs. VDS
for VGS=0,1,2,3,4,5V
Digital IC
Slide 6
exercises
8.Show that the current through two transistors in series
is equal to the current through a single transistor of twice
the length if the transistors are well described by the
long-channel model. Specifically show that IDS1=IDS2 in
figure when the transistors are in their linear
region:VDS<VDD-Vt(this is also true in
saturation).Hint:express the currents of the series
transistors in terms of V1 and solve for V1
Digital IC
Slide 7
exercises
9.Calculate the diffusion parasitic CDB of
the drain of a unit-sized contacted nMOS
transistor in a 0.6um process when the
drain is at 0 and at VDD=5V. Assume the
substrate grounded. is The transistor
characteristics are
CJ=0.42fF/um2,MJ=0.44,CJSW=0.33fF/um
,MJSW=0.12,and 0=0.98V at room
temperature
Digital IC
Slide 8
exercises
10.Assume an inverter in the generic
0.25um CMOS technology designed
with a PMOS-to-NMOS ratio of 6 and
with the NMOS transistor minimum
size(W=0.375um,L=0.25um,W/L=1.5)
Please give the gain of VM, and
VIL,VIH,NML,NMH, VTC curve
Digital IC
Slide 9
exercises
11.Calculating nMOS 1,2,3,4s AS(area of Source),
AD(area of Drain),PS(perimeter of Source),PD (perimeter
of Drain), assuming =0.25um, we use
Keq=0.57,Keqsw=0.61,CJ=2fF,CJSW=0.28 for nMOS
Calculating the internal capacitors between AB,BC,CD
A
Digital IC
B
C
D
Slide 10
exercises
12.Determine the sizes of the inverters in
the figure, such that the delay between
nodes out and in is minimized, CL=64Cg1
is assumed
in
2
1
Digital IC
out
CL
3
Slide 11
exercises
13.Calculate the internal capacitor
between the two inverters using simple
capacitor computing model, numbers
show in the figure mean the nMOS width
1
Digital IC
8
Slide 12
exercises
14.Sizing a chain of inverters.
a. In order to drive a large capacitance (CL = 20 pF)
from a minimum size gate (with input capacitance Ci =
10fF), you decide to introduce a two-staged buffer as
shown in Figure Assume that the propagation delay of a
minimum size inverter is 70 ps. Also assume that the
input capacitance of a gate is proportional to its size.
Determine the sizing of the two additional buffer stages
that will minimize the propagation delay.
b. If you could add any number of stages to achieve the
minimum delay, how many stages would you
insert?What is the propagation delay in this case?
Digital IC
Slide 13
exercises
c. Describe the advantages and disadvantages
of the methods shown in (a) and (b).
d. Determine a closed form expression for the
power consumption in the circuit. Consider only
gate capacitances in your analysis. What is the
power consumption for a supply voltage of 2.5V
and an activity factor of 1?
Digital IC
Slide 14