Logic
Introduction
Digital Ratioed IC
1
EE141
Ratioed Logic design
Ratioed Logic design
Basic concept
Resistive load
Depletion NMOS
Pseudo NMOS
DCVSL logic
Pseudo NMOS logic effort
Digital IC
2
Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
F
In1
In2
In3
VSS
(a) resistive load
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
PDN
VSS
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
Digital IC
3
How to obtain good load
How to obtain a good load
What is a good load
Low power
VOL tend to zero
Charge time short (large charge current)
Memory address decoder match the structure
Low power when address hold the line
Change quickly when address content is changed
Digital IC
4
Ratioed Logic design
Ratioed Logic design
Basic concept
Resistive load
Depletion NMOS
Pseudo NMOS
DCVSL logic
Pseudo NMOS logic effort
Digital IC
5
Ratioed Logic-resistive load
VDD
N transistors + Load
Resistive
Load
VOH = V DD
RL
VOL =
F
In1
In2
In3
RPN
PN
RPN + RL
Assymetrical response
PDN
Static power consumption
tpL= 0.69 RLCL
VSS
Digital IC
6
Resistive load
Resistive load
Could not be to low
VOL
RPDN
=
VDD
RPDN + RL
In order to obtain wide range low noise marginRL>>RPDN
Then resistive size should be adjust
Could not be to high
Then enough large current could give quick switch time,
ti
because
t pLH = 0.69 RL C L
t pHL = 0.69( RL RPDN )C L
Decrease power consumption as soon as possible
Digital IC
7
Ratioed Logic design
Ratioed Logic design
Basic concept
Resistive load
Depletion NMOS
Pseudo NMOS
DCVSL logic
Pseudo NMOS logic effort
Digital IC
8
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
F
In1
In2
In3
PDN
VSS
PDN
VSS
depletion load NMOS
pseudo-NMOS
Digital IC
9
Depletion NMOS load
Depletion NMOS load
Depletion load has negative threshold voltage
It is reasonable when we assume the load transistor works at
saturate state, just like a current source
I L=
k n ,load
2
VTn
2
Practically, the load curve slant down
Load transistors source is connect with output, which VSB will
effect threshold voltage of the transistor
Compared with resistive load, depletion load has smaller area
40k resistive load need 3200m2(0.5um) which could
occupy 1000 unit transistor
Digital IC
10
Depletion NMOS ratios computing
At leas, VOL should close next stage MOS transistor
Vout Vt 0.3Vdd
Vdd RPDN
0.3Vdd
RPDN + RNMOSs load
RPDN
RNMOS load
3
7
WNMOSs load 3
WPDN
7
Inverter: nMOS
Digital IC
11
Ratioed Logic design
Ratioed Logic design
Basic concept
Resistive load
Depletion NMOS
Pseudo NMOS
DCVSL logic
Pseudo NMOS logic effort
Digital IC
12
Pseudo
Pseudo-NMOS ratios computing
ratios computing
PMOSs source and substrate voltage is always zero
that means no body effect
Load transistors saturate current is
kp
I L = (VDD VTp ) 2
2
So pMOS load current is larger than that of nMOS
Digital IC
13
Pseudo-NMOS ratios computing
2
OL
2
VDSATp
V
k n ((VDD VTn )VOL
) + k p ((VDD VTp )VDSATp
2
2
k p (VDD + VTp )VDSATp pW p
VOL =
VDSATp
k n (VDD VTn )
nWn
)=0
n = 3800 cm 2 /v . s, p = 1800 cm 2 /v . s
VOL n
1800 0.4
=
=
= 0.19
3800 1
Wn pVDSATp
Wp
pMOS load for 1/5, always 1/3-1/6
Digital IC
14
Pseudo NMOS logic design rule
Pseudo NMOS logic design rule
Static power
Paverage = Vdd I low =
Constrains should be regarded
kp
2
Vdd (Vdd VT ) 2
ILshould be low in order to decrease power
VOL=ILRPDN should be lower in order to obtain effective low
voltage
voltage
ILshould high in order to decrease tpLH=(CLVdd)/(2IL)
RPDNshould be small in order to decrease tpHL=0.69RPDNCL,
Pull
Pull-down transistors should be wider ,but we
can not benefit from both power and delay
Digital IC
15
Pseudo-NMOS VTC
3.0
2.5
W/Lp = 4
Vou t [V]
2.0
1.5
W/L
W/Lp = 2
1.0
0.5
W/Lp = 0.5
W/Lp = 1
W/Lp = 0.25
0.0
0.0
0.5
1.0
1.5
2.0
2.5
Vin [V]
Digital IC
16
Pseudo-NMOS NMOS ratioed
logic
Pseudo-NMOS ratioed logic merits
N-fan-in needs N+1 transistorswith smaller area and parasitic
capacity
Every input only connects with one transistor, which load capacity is
smaller as front stage logic.
shortcoming
Static power1mW per logic50W consumption if chip has 100,000
such logic structure
application
Can not fit for large scale circuit
not fit for large scale circuit
Only apply on high speed circuit
Only apply on 1-state on most output(such as address decoder)
Large fan-in
Digital IC
17
Load curve analysis
Load curve analysis
Resistive load
VDD Vout
IL =
RL
More output voltage, lower
charge current, which
increase charge time
increase charge time
Ideally, constant current
source
Charge current does not be
decreased by output voltage
Digital IC
18
Improved Loads
VD D
M1
Enable
M2
M1 >> M2
F
A
B
C
D
CL
Adaptive Load
Digital IC
19
Improved Loads (2)
VDD
M1
VDD
M2
Out
A
A
B
B
Out
PDN1
PDN2
VSS
VSS
Differential Cascode Voltage Switch Logic (DCVSL)
Digital IC
20
Ratioed Logic design
Ratioed Logic design
Basic concept
Resistive load
Depletion NMOS
Pseudo NMOS
DCVSL logic
Pseudo NMOS logic effort
Digital IC
21
DCVSL Example
Out
2.5
B
B
B
V ol ta ge [V]
Out
B
AB
1.5
0 .5
A
AB
A,B
A, B
A
- 0 .5
0
XOR-NXOR gate
Digital IC
0.2
0.4
0.6
Time [ns]
0.8
1.0
22
Pseudo
Pseudo-nMOS Power
Power
Pseudo-nMOS draws power whenever Y = 0
Called static power P = IVDD
A few mA / gate * 1M gates would be a problem
few mA gate 1M gates would be problem
This is why nMOS went extinct!
Use pseudo-nMOS sparingly for wide NORs
Turn off pMOS when not in use
en
Y
A
B
Digital IC
C
23
Pass-Transistor Logic
Introduction
Digital IC
24
EE141
Pass
Pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary PassTransistor Logic
Transmission gate principle
Some issues of transmission gate
issues of transmission gate
Resistive issue
Delay issue
Digital IC
25
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
B
Network
B
N transistors
transistors
No static consumption
Pass
Pass-transistor logic is a path, not a
not
road connected with rail directly
Digital IC
26
Example: AND Gate
B
A
B
F = AB
0
Digital IC
27
Pass Transistors
Pass Transistors
Transistors can be used as switches
g
s
d
g
s
d
1: Circuits & Layout
Digital IC
Slide 28
Pass Transistors
Pass Transistors
Transistors can be used as switches
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
g=1
s
d
g=0
g
s
s
1
Input
d
d
g=1
s
d
Digital IC
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
Slide 29
NMOS-Only Logic
In
x
0.5 m/0 .25 m
3.0
Out
In
0.5 m/0.25 m
NMOS keep onthen
VGS>Vt
Voltage [V]
VD D
1.5 m/0.25 m
Out
2.0
x
1.0
VDG=0,which means
means
NMOS always works in
0.0
0
0.5
1
1.5
2
Time [ns]
the saturation state
Digital IC
30
NMOS-only Switch
C = 2.5V
C = 2.5 V
M2
A = 2 .5 V
A = 2.5 V
B
B
Mn
CL
VB does not pull up to 2.5V, but 2.5V -
M1
VTN
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
Digital IC
31
The proper way of cascading pass gates
The proper way of cascading pass gates
Weak for passing high voltage
Vs = min{ G VT , VD }
V
Proper way of cascading pass transistors,which will not
accumulate threshold drop
Digital IC
32
Output of passing-transistor should not be
connected with the gate of next stage
Digital IC
33
Transmission Gates
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Digital IC
Slide 34
Transmission Gates
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input
g = 0, gb = 1
gb
a
b
b
gb
b
gb
g = 1, gb = 0
gb
strong 1
1
g
g
a
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g
a
Output
a
g
b
gb
a
b
gb
Digital IC
Slide 35
Tristates
Tristates
Tristate buffer produces Z when not enabled
EN
A
0
0
0
1
1
0
1
EN
Y
1
Y
A
EN
Y
A
EN
Digital IC
Slide 36
Tristates
Tristates
Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
EN
1
Y
A
EN
Y
A
EN
Digital IC
Slide 37
Nonrestoring Tristate
Transmission Tristate
Nonrestoring gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
EN
A
Y
EN
Digital IC
Slide 38
Tristate Inverter
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A
EN
Y
EN
Digital IC
Slide 39
Tristate Inverter
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
Digital IC
Slide 40
Multiplexers
Multiplexers
2:1 multiplexer chooses between two inputs
S
S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
Y
X
D0
0
Y
D1
Digital IC
1
Slide 41
Multiplexers
Multiplexers
2:1 multiplexer chooses between two inputs
S
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
Digital IC
D0
0
Y
D1
1
Slide 42
Gate
Gate-Level Mux Design
Mux Design
Y = SD1 + SD0 (too many transistors)
How many transistors are needed?
Digital IC
Slide 43
Gate
Gate-Level Mux Design
Mux Design
Y = SD1 + SD0 (too many transistors)
How many transistors are needed? 20
D1
S
D0
D1
S
D0
Y
4
2
4
2
4
2
Y
2
Digital IC
Slide 44
Transmission Gate Mux
Transmission Gate Mux
Nonrestoring mux uses two transmission gates
Digital IC
Slide 45
Transmission Gate Mux
Transmission Gate Mux
Nonrestoring mux uses two transmission gates
Only 4 transistors
S
D0
Y
S
D1
S
Digital IC
Slide 46
Inverting Mux
Inverting Mux
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
th
thi
Noninverting multiplexer adds an inverter
D0
S
S
D0
S
D1
D1
S
Y
S
S
S
Y
S
D0
Y
S
D1
Digital IC
0
1
Slide 47
4:1 Multiplexer
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
1: Circuits & Layout
Digital IC
Slide 48
4:1 Multiplexer
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
S1S0 S1S0 S1S0 S1S0
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
Digital IC
Slide 49
Pass
Pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary PassTransistor Logic
Transmission gate principle
Some issues of transmission gate
issues of transmission gate
Resistive issue
Delay issue
Digital IC
50
Pass
Pass-transistors VTC
VTC
Digital IC
51
Complementary Pass Transistor Logic
A
A
B
B
Pass-Transistor
Network
F
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
A
F=A
(b)
A
A
B
B
F =A+B
B
OR/NOR
Digital IC
A
F=A
EXOR/NEXOR
52
Pass
Pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive
issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary PassTransistor Logic
Transmission gate principle
gate principle
Some issues of transmission gate
Resistive issue
Delay issue
Digital IC
53
Solution 1:Level Restoring Transistor
V DD
Level Restorer
V DD
Mr
B
A
Mn
M2
X
Out
M1
Advantage: Full Swing
Restorer adds capacitance, takes away pull down current at X
Ratio problem
Digital IC
54
Restorer Sizing
V oltage [V]
3.0
2.0
Upper limit on restorer size
Pass-transistor pull-down
can have several transistors in
stack
stack
W /Lr =1.75/0.25
W /L r =1.50/0.25
1.0
W/ Lr =1.0/0.25
0.0
0
100
200
W /L r =1.25/0.25
300
Time [ps]
400
Digital IC
500
55
pass
pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3l: Transmission Gate Complementary
Pass-Transistor Logic
Transmission gate principle
Some issues of transmission gate
issues of transmission gate
Resistive issue
Delay issue
Digital IC
56
Solution 2: Single Transistor Pass Gate with
VT=0
VDD
0V
2.5V
VDD
0V
VDD
Out
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
Digital IC
57
pass
pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary
Pass-Transistor Logic
Transmission gate principle
Some issues of transmission gate
issues of transmission gate
Resistive issue
Delay issue
Digital IC
58
Solution 3: Transmission Gate
C
A
C
A
B
B
C
C
C = 2.5 V
A = 2.5 V
B
CL
C=0V
Digital IC
59
pass
pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary PassTransistor Logic
Transmission gate principle
Some issues of transmission gate
issues of transmission gate
Resistive issue
Delay issue
Digital IC
60
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
V DD
M2
F
S
M1
B
S
GND
In
1
Digital IC
In
2
61
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
Digital IC
62
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
VDD
S Sum Generation
Ci
P
A
B
P
Ci
VDD
A
P
Co Carry Generation
Ci
A
P
Setup
Similar delays for sum and carry
Digital IC
63
pass
pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary PassTransistor Logic
Transmission gate principle
Some issues of transmission gate
issues of transmission gate
Resistive issue
Delay issue
Digital IC
64
More detail about a processing of
low-to-high
Two transistors stories
NMOS
For VGS=VDS , VGD=0<Vt ,then
NMOS always works in the
saturation or off state
PMOS
For VGS=-2.5V, transistor turn
from saturation to linear state
More detail
Vout <| Vtp |: NMOS and PMOS are in saturation
| Vtp |< Vout < Vdd Vtn : NMOS in satur.PMOS in linear
Vdd Vtn < Vout : NMOS cut offPMOS in linear
off
Digital IC
65
Transmission gate effective
resistance of low-to-high
Relatively constant
Req=Rp||Rn
Rn =
VDD Vout
2
VDSATn
W
k ( ) N ((VDD Vout VTn )VDSATn
)
L
2
'
n
VDD Vout
k n (VDD Vout VTn )VDSATn
Rp =
VDD Vout
=
I Dn
Vout VDD
=
I Dp
VDD Vout
(Vout VDD ) 2
W
k ( ) P ((VDD VTp )(Vout VDD )
)
L
2
'
p
1
k p (VDD VTp )
Digital IC
66
pass
pass- transistor logic outline
outline
Pass-transistor principle
Pass-transistor VTC
VTC
How to solve pass-transistor threshold drop issue
Solution 1:Level Restoring Transistor Resistive issue
Solution 2: Single Transistor Pass Gate with VT=0
Solution 3: Transmission Gate Complementary Pass-Transistor Logic
Transmission gate principle
Some issues of transmission gate
Resistive issue
Delay issue
Complementary Pass-Transistor Logic
Digital IC
67
Delay in Transmission Gate Networks
Many applications use transmission like that
Replaced by their equivalent resistances
Digital IC
68
Computing delay time
Computing delay time
How to do
Solving the differential equation
Vi
1
=
(Vi +1 Vi (Vi Vi 1 ))
t
Req C
dQ CdV
,
I C = I i +1 I i , I C =
=
dt
dt
Vi 1
= ( I i +1 I i )
t C
It is too complex to find precise solution,we have to
find some approximate solution
Digital IC
69
A close solution
close solution
Delay time is
n(n + 1)
(Vn ) = CReq k = CReq
2
k =0
n
Break chain and Insert buffer
Digital IC
70
Transmission gate delay optimization
Total delay time
Assume all has n transmission gatebreak chain
every m switchs,buffer delay time is tbuf
n
m ( m + 1)
n
t p = 0 .69[ CR eq
] + ( 1)t buf
m
m
2
n ( m + 1)
n
= 0 .69 CR eq
+ ( 1)t buf
m
2
Digital IC
71
Optimal number of switch
moptimal
t p
t p
m
m
=0
= 0.69CReq
moptimal = 1.7
tbuf
CReq
Digital IC
ntbuf
n
2 =0
2m
It is independent with n
= 1 .7
72