2010 Spring EEL 6323 Midterm Exam
(Closed book, closed notes, 60 Minutes)
Name: _____________________________
UFID: _____________________________
Problem 1
Problem 2
Problem 3
Total :
40 pts.
30 pts.
30 pts.
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Note: Please show work. Answers without analysis will not receive
credit.
PROBLEM 1 (40pts)
Short answer questions
1.1. For the transistor networks shown below, determine the logic functions (if any) and the
voltage levels at the output of each logic gate.
A
B
0
0
0
Vdd
Vdd
0
Vdd
Vdd
A
B
0
0
0
Vdd
Vdd
0
Vdd
OUT
Vdd
OUT
B
A
(a)
OUT
B
A
OUT
(c)
1.2 Estimate the frequency of the following 13 stage ring oscillator if implemented in 180nm
CMOS technology.
1.3 The delay versus fanout for gates A and B are plotted below. Extract the logical effort (g) and
parasitic delay (p) for each gate. In addition, give at least one example of gates A and B.
A
B
8
Normalized Delay: d
7
6
5
4
3
2
1
0
1
2
3
4
5
Electrical
Electrical Effort:
h = Cout / Cin
1.4 The DC characteristics of an inverter (X) are defined as VIHX=3.1 volts, VILX=1.8 volts,
VOHX=4.5 volts, VOLX=0.9 volts. The DC characteristics of another inverter (Y) are defined
as VIHY=2.9 volts, VILY=1.2 volts, VOHY=4.2 volts, VOLY=0.3 volts. Which of the
following configurations has the largest NMH? Assume Vdd=5 volts.
a.
b.
c.
d.
X drives Y
Y drives X
X drives X
Y drives Y
1.5 Consider both the Verilog-HDL and VHDL RTL descriptions of a component name
MUX_INV provided below. The codes are functionally identical to each other. Draw the
output waveform of this design given the input signals shown below:
Verilog (out, Code
module
module
output
input
reg
MUX_INV a, b, sel)
out;
a, b, sel;
out;
always @(sel)
begin
case (sel)
1b0: out = !a;
1b1: out = !b;
endcase
end
endmodule
a
b
sel
out
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_INV is
port (
a
: in std_logic;
b
: in std_logic;
sel
: in std_logic;
out : out std_logic );
end MUX_INV;
architecture Behavioral of MUX_INV is
begin
muxProc: process (sel)
case sel is
when 0" => out <= not a;
when 1" => out <= not b;
endcase;
end process muxProc;
end Behavioral;
PROBLEM 2: (30 Points)
.
Consider the following simplified transistor model in Fig. P2.1. In the figure below, k is the
transistor multiplier factor, where a large k implies a large transistor width. The transistor
resistance Rd equals R/k, where R is some unit resistance. Similarly, the parasitic Source/Drain
capacitances Cs and Cd equal kC, where C is some unit capacitance.
Cd=kC
In
k
Rd=R/k
Cs=kC
Fig. P2.1: simplified transistor model
With this in mind, estimate the pull down delay of the following two circuits (Fig. P2.2). Assume
the output capacitance CL is initially charged to Vdd and the transistor layout is such that the
diffusion regions are NOT overlapped. Moreover, assume that the inputs In1=In2=In3=In4
transition simultaneously from 0 to 1 (i.e. from 0 to Vdd). Which circuit is faster? Justify your
work.
In4
In3
In2
In1
k1=16
M1
CL=32C
In4
k2=8
M1
k2=4
M2
k3=4
k1=2
In3
M3
In2
M4
In1
k4=2
M2
k3=8
M3
k4=16
Fig. P2.2: Pull down circuits.
M4
CL=32C
PROBLEM 3 (30pts)
Select gate sizes x, y and z for least delay from A to B. You will need to consider the critical
path (i.e. path with worst case delay). Check your answer. Estimate the absolute delay in 180nm
process.
x
A
8
x
z
y
B
100
Extra work page