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17 Pages

EEL6323-S10-HLec01-intro-2spp

Course: ESI 6323, Spring 2009
School: University of Florida
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6323 Advanced EEL VLSI Design Spring 2010 Section: 6963 Lecture 0: Introduction Course Outline CMOS Trends and Scaling 1 Practical Information Instructor Rizwan Bashirullah Office: 527 NEB, E-mail: rizwan@ufl.edu Tel: (352) 392-0622, Fax: (352) 392-8381 Admin Janet Holman, 526 NEB holman@ece.ufl.edu Practical Information Class Meeting time: MWF 10:40-11:30 Location: NEB 100 Website: http://www.icr.ece.ufl.edu/teaching/EEL6323S10/6323home.htm (password protected) Instructor Office Hours: MW 11:30 - 12:30pm TA Qiuzhong Wu (qiuzhongwu@ufl.edu) Chung-Ching Peng (cpeng@cise.ufl.edu) Office hours: TBA 2 Class Material Required Textbooks Neil H.E. Weste, David Harris, CMOS VLSI Design, A Circuits and Systems Perspective, 3rd Edition, Pearson, Addison-Wesley, 2005. ISBN 0-321-14901-7 Jan. M. Rabaey, A. Chandrakasan, and B. Nikolic, "Digital Integrated Circuits, A Design Perspective," 2nd Edition, Prentice Hall, 2003. ISBN 0-13-090996-3 In addition, handouts developed by instructor may be downloaded from class www site Class Material Journal/Conference References Journal of Solid State Circuits (JSSC), TVLSI, CAS-I and II ISSCC, VLSI Symposium, CICC, ISCAS Web Links IEEE Explorer 3 Course Goals To develop a basic understanding of CMOS integrated circuit design To develop proficiency in analysis, design and implementation of CMOS circuits To develop a basic understanding of design considerations to maximize chip success Course Topics CMOS Overview Scaling Trends and Process Technology Gates Transistor Models DC/Transient and Delay Logical Effort Circuit Simulation Static, Dynamic Variability and Circuit Pitfalls Low power design Power dissipation Low power techniques and trends Datapaths Adders Multipliers Timing Digital Flow Design methodology Synthesis, Place and Route, verification Circuit Families Clock Distribution and Generation Skew Tolerant Design Latches and Flip-flops PLL/DLL Signaling and power Interconnects, Packaging and I/O Power Delivery and Decoupling Memory 4 Digital IC Flow RTL to layout Behavioral Language Synthesis Place and route Verification -- right-shift arithmetic for 8-bit signed integer rsa: process (a, shamt) variable fill : std_logic_vector(1 downto 0); variable temp : std_logic_vector(4 downto 0); begin for i in 0 to 3 loop fill(i):=1 and a(3); end loop; if shamt(0)=1 then temp := fill(0) & a(7 downto 1); end if; if shamt(1)=1 then temp := fill(1 downto 0) & temp(7 downto 2); end if; if shamt(2)=1 then out <= fill(3 downto 0) & temp(7 downto 4); end if; end process; Grading Policy Problem Sets (5): 30% Midterms (2): 20% Each Final Project (1): 30% Grading policy is subject to change 5 Projects USB controller and IO interface EPC Gen 2 RFID protocol or Smart Card Ultra low power embedded processor and communication interface Academic Honesty All students admitted to the University of Florida have signed a statement of academic honesty committing themselves to be honest in all academic work and understanding that failure to comply with this commitment will result in disciplinary action. This statement is a reminder to uphold your obligation as a student at the University of Florida and to be honest in all work submitted and exams taken in this class and all others. Students requesting classroom accommodation must first register with the Dean of Students Office. The Dean of Students Office will provide documentation to the student who must then provide documentation to the instructor when requesting accommodation. 6 Lecture 1: Introduction Moores Law CMOS Trends 1975 1974 1973 1972 1971 1970 1969 1968 1967 1966 1965 1964 1963 1962 1961 Electronics, April 19, 1965. 1960 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Moores Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months Digital Integrated Circuits, 2nd Ed. 2003 Prentice Hall/Pearson 7 Moores law in Microprocessors Transistors (MT) 1000 2X growth in 1.96 years! 100 10 486 1 P6 Pentium proc 386 286 0.1 8086 8085 Transistors on Lead Microprocessors double every 2 years Transistors on Lead Microprocessors double every 2 years 0.01 8080 0.001 8008 4004 1970 1980 1990 Year 2000 2010 Courtesy, Intel Digital Integrated Circuits, 2nd Ed. 2003 Prentice Hall/Pearson Memory Trends 32 word lines x 1024 blocks 16896 bit lines 10.7mm Charge pump 2kB buffer & cache 1Gbit flash memory 11.7mm From [Nakamura02] 8 Feature Size Human hair, 100m Amoeba, 15m Red blood cell, 7m AIDS 0.1m [Source: virus, Gordon Moore, Intel, ISSCC] Die Size Trends 9 Die Size Growth Die size (mm) 100 10 8080 8008 4004 8086 8085 1 1970 286 386 P6 486 Pentium proc ~7% growth per year ~2X growth in 10 years 1980 1990 Year 2000 2010 Die size grows by 14% to satisfy Moores Law Die size grows by 14% to satisfy Moores Law Courtesy, Intel Digital Integrated Circuits, 2nd Ed. 2003 Prentice Hall/Pearson Frequency Frequency (Mhz) 10000 Doubles every 2 years 1000 100 486 10 8085 1 0.1 1970 8086 286 P6 Pentium proc 386 8080 8008 4004 1980 1990 Year 2000 2010 Lead Microprocessors frequency doubles every 2 years Lead Microprocessors frequency doubles every 2 years Courtesy, Intel Digital Integrated Circuits, 2nd Ed. 2003 Prentice Hall/Pearson 10 Processor Supply Voltage [Source: Gordon Moore, Intel, ISSCC] Static Power VDD decreases Save dynamic power Protect thin gate oxides and short channels No point in high value because of velocity sat. Vt must decrease to maintain device performance But this causes exponential increase in OFF leakage Major challenge [Source: Gordon Moore, Intel, ISSCC] Processor Power (Watts) Active and Leakage 11 Power Dissipation Power (Watts) 100 P6 Pentium proc 10 8086 286 1 8008 4004 486 386 8085 8080 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Lead Microprocessors power continues to increase Courtesy, Intel Digital Integrated Circuits, 2nd Ed. 2003 Prentice Hall/Pearson Power density Power Density (W/cm2) 10000 1000 100 Rocket Nozzle Nuclear Reactor 8086 10 4004 Hot Plate P6 Pentium proc 8008 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Power density too high to keep junctions at low temp Courtesy, Intel Digital Integrated Circuits, 2nd Ed. 2003 Prentice Hall/Pearson 12 Multi-core: 80 Tile Processor Intel Device Enhancements TiSi2 n+ S Al Gate D Gate NiSi Gate Si1-xGex Si Substrate (a) 1970s LDD (b)1980s High-k Highgate dielectric Gate Silicide added Channel Strained silicon Strained channel (c) 2003 Transistor New transistor structure Source: Intel 13 Gate Stack Traditional Oxide Scaling XG=LG/45 70nm node, XG~2nm (6-7 atomic layers) Increased gate leakage Introduce High-k Gate dielectrics Thicker oxide to reduce leakage Use high dielectric constants to maintain same capacitance per unit area hafnium oxides HfO2 kx~30-40 zirconium oxides ZrO2 kx~25 Equivalent Oxide Thickness (EOT) EOT=(kSiO2/kx)tx kSiO2 ~3.9 tx = physical oxide thickness Strained Silicon and Silicides Higher mobility Increases drive current and transistor speed Implant SiGe to stretch the Si lattice Yields up to 70% increase in mobility or 30% improvement in performance Silicide Polysilicon gate and Source/Drain regions have high resistance Deposit metal on polygate and/or S/D regions to decrease resistance (Tantalum, molybdenum, titanium, cobalt) Polycide: only the gate is silicided Salicide (self-aligned silicidization): both polygate and S/D regions are silicided 14 LDD and Isolation LDD Lightly doped drain Reduces the electric field at the drain junction Improves device immunity to hot electron damage LDD is shallow and increases series resistance (decreases performance) Silicon Nitride spacer along the edge of gate serves to mask n+/p+ S/D regions LOCal Oxidation of Silicon (LOCOS) to isolate devices LOCOS produces Birds beak caused by lateral diffusion of SiO2 Limits packing density due to extended transition between thin and thick oxides Shallow Trench Isolation (STI) 180nm and below Improved packing density 90nm Process Interconnects M7 Metal lines Al M6 Cu M5 M4 Insulating dielectric M3 M2 M1 (low-k) (low- Interconnects Source: Intel 15 Low-K Dielectrics and Copper Interconnects Low-K is used for Inter Layer Dielectrics (ILD) to decrease interconnect capacitance SiO2 dielectric constant k=3.9-4.2 Addition of Fluorine to SiO2 forms fluorosilicate glass (FSG) and decreases k to ~3.6 Replace Al interconnects with Cu up to 40% decrease in resistance Process enhancements Isolation, Reliability, Gate stack, Strained Si Low-k and copper interconnects Other enhancements Multiple Vt transistors Low-Vt and high-Vt Multiple Oxide thickness Core logic vs IO logic Thick metal options Triple Well process 16 Summary Number of transistors doubles ~18-24mo Die size increase by 14% every 2 years Frequency doubles every 2 years But power limit Leakage power is increasing as TOX decreases (20% or more)new devices Supply voltages have been steadily decreasing But will remain at 1V or so Minimizing Power is essential Different architectures, slower speeds, power gating 17

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