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EEL6323-S11-HLec017-Adders-2spp

Course: ESI 6323, Spring 2009
School: University of Florida
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17: Lecture Adders Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Select Adder Carry-Lookahead Adder Tree Adder Reading: Chapter 10, W&H Carry Generation and Propagation Define 3 new variables that depend only on A and B Generate: Cout = 1 independent of C G=AB S = P Cin Propagate: Cout = C Cout = G + P Cin P=AB Kill: Cout = 0 independent of C K = ~A ~B 1 Carry Chain Carry of Mirror Adder Manchester Carry Chain Group PG Logic (Ci=Gi:0) Gi:0=Gi+PiGi-1:0 or Ci=Gi+PiCi-1 Sum Logic Si=Pi+ Gi-1:0 Pi:0=PiPi-1:0 Bitwise PG Logic Gi=AiBi Pi= (Ai + Bi) C0=G0:0=G0 C1=G1:0=G1 + P1C0 C2=G2:0=G2 + P2(G1 + P1C0) C3=G3:0=G3 + P3(G2 + P2(G1 + P1C0)) 2 PG network for Manchester Carry Chain Manchester Carry Chain Discharge Transistor R1 1 MC 2 C1 R2 M0 C2 R3 3 M1 C3 4 R4 M2 R5 5 M3 C4 6 C5 R6 Out M4 C6 Propagate/Generate Row VDD Pi Ci - 1 Gi Pi + 1 Gi + 1 Ci Ci + 1 GND Inverter/Sum Row 3 Carry-Bypass Adder G0 Cin P1 G1 C0 Cin P1 FA P2 FA G2 C1 FA G3 C3 FA G1 C0 P3 C2 FA G0 G2 C1 FA P0 P2 P3 G3 FA BP=P oP1 P2 P3 C3 C2 FA Multiplexer P0 C3 CSA Manchester Stage 4 Carry-Bypass Adder (cont.) Carry generated at first bit position Bit 03 Setup N=16, M=4 Bit 47 tsetup Bit 811 Bit 1215 Setup Setup Setup Carry propagation tbypass Carry propagation Carry propagation Carry propagation Sum Sum Sum tsum Sum M bits tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum Variable length carry bypass Bypass the bypass Carry Ripple vs Carry Skip Adder tp Ripple Adder Bypass Adder 4-8 N 5 Carry-Select Adder Trick for critical paths dependent on late input Cin Precompute two possible outputs for X = 0, 1 Select proper output when X arrives Setup P,G "0" Carry Propagation "0" "1" "1" Carry Propagation C in Multiplexer Cout Carry Vector Sum Generation Carry Select Adder: Critical Path Bit 03 Bit 47 Bit 811 Bit 1215 Setup Setup Setup Setup 0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry 1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry Ci,0 Multiplexer Co,3 Multiplexer Co,7 Multiplexer Co,11 Multiplexer Sum Generation Sum Generation Sum Generation Sum Generation S03 S47 S811 Co,15 S1215 6 Square Carry Root Select Bit 0-1 Bit 2-4 Setup Bit 5-8 Setup Setup Bit 9-13 Setup Bit 14-19 (1) "0" Carry "0" "0" "0" Carry "0" "0" Carry "0" "0" Carry (1) "1" Carry "1" Carry "1" (3) "1" (3) "1" Carry "1" (4) (4) "1" Carry "1" (5) (7) (6) (5) (6) Multiplexer Multiplexer Multiplexer Sum Generation Sum Generation Sum Generation S2-4 (7) S5-8 Multiplexer Mux Ci,0 (8) S0-1 Sum Generation S9-13 Sum S14-19 (9) Adder Delays - Comparison 50 Ripple adder tp (in unit delays) 40 30 Linear select 20 10 0 Square root select 0 20 40 60 N 7 VDD Look-Ahead: Topology G3 G2 Rippling effect of carry bits: Ci=Gi+PiCi-1 Ci+1=Gi+1+Pi+1Ci G1 G0 Cin C3 What if you expand the equations all the way (basic lookahead concept): P0 P1 C0=G0+P0Cin C1=G1 + P1G0 + P1P0Cin C2=G2 + P2G1 + P2P1G0 + P2P1P0Cin C3=G3 + P3G2 + P3P2G1 + P3P2P1C0 + P3P2P1P0Cin P2 P3 4-bit lookahead topology -slow for large adders -Area grows with progressively with N Logarithmic Lookahead Trees Carry-lookahead group of N bits has N+1 parallel branches and up to N+1 transistor in a stack (previous example) Poor performance. Limit CLA to 2-4 bits (radix 2 or 4) Organize carry propagation and generation into recursive trees Hierarchically decompose the carry propagation into subgroups of N-bits A0 A1 A2 A3 F A4 A5 tp log2(N) A6 A7 Can continue building the tree hierarchically. 8 S13 S14 S15 (A13, B13) (A14, B14) (A15, B15) S8 (A8, B8) S12 S7 (A7, B7) (A12, B12) S6 (A6, B6) S11 S5 (A5, B5) S10 S4 (A4, B4) (A11, B11) S3 (A3, B3) S9 S2 (A2, B2) (A10, B10) S1 (A1, B1) (A9, B9) S0 16-bit radix-2 Kogge-Stone tree (A0, B0) Tree Adders Wiring problem for Large adder Increases logical effort VDD VDD Clkk Pi:i-2k+1 Pi:i-k+1 Clkk Gi:i-2k+1 Pi:i-k+1 Gi:i-k+1 Pi-k:i-2k+1 Propagate Gi-k:i-2k+1 Generate Summary Many adder topologies Speed optimization revolves around finding ways to decrease carry chain delay Carry bypass, carry-select, carry lookahead, logarithmic adders and tree adders (variations of Log adders) 9

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