Motivation
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Overview
Logic Modeling
ECE 553: TESTING AND
TESTABLE DESIGN OF
DIGITAL SYSTES
Model types
Models at different levels of abstractions
Models and definitions
Summary
Logic Modeling
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Logic Modeling Model types
Motivation
Models are often easier to work with
Models are portable
Models can be used for simulation, thus
avoiding expensive hardware/actual circuit
implementation
Nearly all engineering systems are studied
using models
All the above apply for logic as well as for fault
modeling
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External
representation
Internal
representation
Behavior
System at I/O level
Timing inf provided
Internal details missing
Functional
DC behavior no timing
Structural
Gate level description
Models are often described using an hierarchy
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Modeling Levels
Hierarchical Model: A Full-Adder
Timing
Application
Clock
boundary
Architectural
and functional
verification
e
d
b
A
B
C
HA
HA1
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D
E
HA2
F
f
0, 1, X
and Z
Zero-delay
unit-delay,
multipledelay
Logic
verification
and test
0, 1
and X
Zero-delay
Logic
verification
Carry
Sum
Transistor technology
data, connectivity,
node capacitances
Analog
voltage
Fine-grain
timing
Timing
verification
Tech. Data, active/
passive component
connectivity
Analog
voltage,
current
Continuous
time
Digital timing
and analog
circuit
verification
Function,
behavior, RTL
FA;
inputs: A, B, C;
outputs: Carry, Sum;
HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);
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Programming
language-like HDL
Logic
HA;
inputs: a, b;
outputs: c, f;
AND: A1, (a, b), (c);
AND: A2, (d, e), (f);
OR: O1, (a, b), (d);
NOT: N1, (c), (e);
Circuit
description
Connectivity of
Boolean gates,
flip-flops and
transistors
Switch
c
a
Modeling
level
Transistor size
and connectivity,
node capacitances
Timing
Circuit
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Signal
values
0, 1
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1
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Logic Models and definitions*
Logic Models and definitions (2)
Combinational circuit models
Program model of a circuit
Function expressed as truth-table or cubes
Cubes cube and intersection can be used during simulation
Express circuit (gate level) as a program consisting of
interconnected logic operations
Execute the program to determine circuit output for varying
inputs
Sequential Circuits
Structure represented as a collection of flip -flops feeding
combinational logic
Time frame expansion is possible
RTL model
Higher level model of the circuit
HDL model
Binary Decision Diagrams (BDD)
Examples at this level are verilog HDL and VHDL
*Ref: Abramovici et. al, Digital system testing and testable design
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Logic Models and definitions (3)
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Netlist Format: Two Examples
Structural model
UW format
External representation in the form of netlist
Examples of this are uw format, iscas format, EDIF,
Some keywords used in such representation
# gate connected to
1
2
3
4
5
6
7
8
Primary inputs and Primary outputs
Gates: AND, OR, NOT,
Storage: latch, flip-flop
Connections: lines, nets
Fanin: number of inputs to a gate
Fanout: number of lines a signal feeds
Fanoutfree circuit: every line or gate has a fanout of one
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PI 4, 5 ;
PI 3, 6 ;
not 5 ;
not
6;
and 7 ;
and
7;
or 8 ;
PO ;
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ISCAS format
output = gate(inputs)
INPUT(G1)
INPUT(G2)
OUTPUT(G7)
G3 = NOT(G2)
G4 = NOT(G1)
G5 = AND(G1, G3)
G6 = AND(G2, G4)
G7 = OR(G5, G6)
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Logic Models and definitions (4)
Logic Models and definitions (5)
Structural model
Additional useful terms
Internal representation in the form of tables
Tables of gates and storage elements (names)
Tables of connections
Tables of fanin and fanouts
Objective is to make the storage and search processes
(integral part of simulation) more efficient
Knowledge of data structures and algorithms is very
useful
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Graph representation
Reconvergent fanouts
Stems and branches
Logic levels in a circuit
levelization of a circuit
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Summary
Modeling of logic circuit offers many advantages
Many modeling levels exist and are used
Gate level models are most prevalent in logic testing
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