061 CS Computer Organization
Quiz 5 Monday 2/13
Winter - 2012
solution
1. You are given a box of 2k by 4-bit memory chips, and asked to construct from them a 128k
by 1-byte memory module, utilising the Chip Select (CS) input on each of the chips. This
will require "two levels" of addressing i.e. a portion of the address will be input to the
address pins of the individual chips, and a portion will be input to a module-level decoder
driving the chips' CS pins. How many bits will be input to this module-level decoder?
a. 2
b. 3
e. 6
f. 8
c. 4
d. 5
The next two questions refer to the following scenario:
st
nd
rd
th
Consider an elevator that connects the 1 , 2 , 3 & 4 floors of a building, able to make "express" rides, e.g. it
st
rd
th
can.go from the 1 floor to the 3 or 4 floor without stopping at imtermediate floors (and vice versa).
The controller for this system is an example of a finite state machine (fsm), whose state space consists of the
elevator stopped at each of the four floors, with the doors either closed or open (i.e. doors open & doors closed
are separate states). The task of the fsm is to control the transitions between all possible states, according to
external inputs from button pushes, sensors, etc (which we don't need to worry about here).
To answer the following questions, you will need to sketch the fsm diagram, identifying all possible states and all
possible transitions between states. Think carefully about the open- & closed-door states.
2. How many bits would be needed to label all possible states?
c. 3
a. 1
b. 2
d. 4
e. 5
f. 6
3. How many distinct transitions are there between states (not including null transitions, i.e.
transitions back to the current state)?
a. 4
b. 6
c. 8
d. 12
e. 20
f. 24
The following four questions refer to the von Neumann model of computing:
4. The key components of the Processing unit are:
a. the arithmetic & logic unit (ALU) and the register bank
b. the ALU and the instruction register
c. the instruction decoder and the ALU
d. the memory data register and the program counter
e. register the bank and the program counter
5. The main purpose of the control unit is:
a. to store the list of instructions
b. to fetch the next instruction from memory & decode it
c. to control the ALU
d. to control access to memory
e. to fetch any operands required by the instructions
6. The Program Counter is:
a. a binary counter that keeps track of the number of instructions executed
b. a register that stores the instruction currently being executed
c. a control circuit that steps through a sequence of instructions
d. a register that stores the address of the next memory location to be written to
e. a register that stores the memory address of the next instruction
1
7. The Instruction Register is:
a. a binary counter that keeps track of the number of instructions executed
b. a register that stores the instruction currently being executed
c. a control circuit that steps through a sequence of instructions
d. a register that stores the address of the next memory location to be written to
e. a register that stores the memory address of the next instruction
8. An ISA specifies a word size of 4 bytes; byte addressability; and an address space of
16M; it uses single-word instructions.
What are the sizes of the PC and the IR?
a. both 16 bits
b. both 24 bits
c. both 32 bits
d. PC: 16 bits; IR: 32 bits
e. PC: 24 bits; IR: 32 bits
f. PC: 32 bits; IR: 24 bits
9. For the system in the previous question: What are the sizes of the MDR and the MAR?
a. both 16 bits
c. both 32 bits
e. MDR: 24 bits; MAR: 32 bits
f. MDR: 32 bits; MAR: 24 bits
b. both 24 bits
d. MDR: 16 bits; MAR: 32 bits
10. W hat are the register transfers (sometimes called "micro-instructions") that comprise the
Fetch phase of the Instruction cycle?
a.
b.
c.
d.
e.
f.
2
IR <- (PC); MAR <- (IR); PC <- Mem[MDR]; PC <- (PC) + 1;
PC <- (MDR) + 1; MAR <- Mem[PC]; IR <- (MDR)
MAR <- (PC) + 1; MDR <- Mem[IR]; IR <- (MAR);
MAR <- (PC); PC <- (PC) + 1; MDR <- Mem[(MAR)]; IR <- (MDR)
MDR <- (PC); PC <- (PC) + 1; MAR <- Mem[(MDR)]; IR <- (PC)
huh??