RC Generic Architecture
Host CPU s
Local Interconnect(s)
Mem
Node Architecture
NIC Node Interconnect
RC Devices
Coupling in Reconfigurable Systems
Ex: xtremeData
Ex: Nallatech, GiDEL
Different levels of coupling in a reconfigurable system. (Reconfigurable logic shaded)
* Compton and Hauck, "Reconfigurable Computing: A Survey of Systems and Software", ACM 2002.
2
Attached Processing Unit
Ex: Nallatech, GiDEL
3
General Design Pattern for RC Circuit
Input Address Generator
RAM
Buffer
Buffers handle differences in speed between RAM and datapath
Controller
Datapath
Buffer Output Address Generator
RAM
4
2
H100 Series
FPGA Application Accelerators
Products in the H100 Series PCI-X Mainstream
IBM EBlade
HPC solution for optimal price/performance PCI-X form factor Single Xilinx Virtex 4 FPGA processor SRAM and SDRAM external memory Four high-speed serial I/O system links Supported by Nallatech's application development flow and ANSI C-toFPGA compiler Ideal for adding FPGA compute capability to new or existing clusters
H101-PCIXM
H102-EBLADE
IBM BladeCenter expansion blade Two Xilinx Virtex 4 FPGA processors SRAM and SDRAM external memory Eight high-speed serial I/O system links Supported by Nallatech's application development flow and ANSI C-toFPGA compiler Ideal for adding FPGA compute capability to IBM BladeCenter clusters
6.4
DOUBLE PRECISION GFLOPS SUSTAINED
20
SINGLE PRECISION GFLOPS SUSTAINED
64
INT16 GigaOPS SUSTAINED
12.8
DOUBLE PRECISION GFLOPS SUSTAINED
40
SINGLE PRECISION GFLOPS SUSTAINED
128
INT16 GigaOPS SUSTAINED
IBM BladeCenter
IBM BladeCenter
IBM HS21 BladeCenter Single FPGA expansion blade with two Xilinx Virtex 4 FPGA processors Eight high-speed serial I/O system links Supported by Nallatech's application development flow and ANSI C-toFPGA compiler The ideal platform for adding FPGA compute capability to IBM BladeCenter clusters
H102-BLADECENTER
H114-BLADECENTER
Fully loaded IBM HS21BladeCenter Seven FPGA expansion blades each with two Xilinx Virtex 4 FPGA processors Fifty-six high-speed serial I/O system links Supported by Nallatech's application development flow and ANSI C-toFPGA compiler The ideal platform for adding FPGA compute capability to IBM BladeCenter clusters
12.8
DOUBLE PRECISION GFLOPS SUSTAINED
40
SINGLE PRECISION GFLOPS SUSTAINED
128
INT16 GigaOPS SUSTAINED
89.6
DOUBLE PRECISION GFLOPS SUSTAINED
280
SINGLE PRECISION GFLOPS SUSTAINED
896
INT16 GigaOPS SUSTAINED
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H100 Series
FPGA Application Accelerators
Technical Specification Technical Specification FPGA Compute Engine
Total number of FPGA Processors Xilinx FPGA Type Internal Memory per FPGA processor External SRAM per FPGA processor External SDRAM per FPGA processor Max # double precision FPUs Max # single precision FPUs Max # INT16 Units FPGA clock frequency Inter compute engine serial comms Serial comms latency H101-PCIXM 1 Virtex-4 LX100 0.5 MBytes RAM distributed across FPGA, 0.5 TBytes/sec bandwidth 16 MBytes DDR-II SRAM across 4 banks, 6.4GBytes/sec total bandwidth 512 MBytes DDR2 SDRAM in 1 bank, 3.2GBytes/sec bandwidth 32 100 320 200MHz 4x 2.5 Gbit/sec serial links 340ns 6.4 GigaFLOPS 20 GigaFLOPS 64 GigaOPS H102-EBLADE 2 Virtex-4 LX100 0.5 MBytes RAM distributed across FPGA, 0.5 TBytes/sec bandwidth 16 MBytes DDR-II SRAM across 4 banks, 6.4GBytes/sec total bandwidth 512 MBytes DDR2 SDRAM in 1 bank, 3.2GBytes/sec bandwidth 64 200 640 200MHz 8x 2.5 Gbit/sec serial links 340ns 12.8 GigaFLOPS 40 GigaFLOPS 128 GigaOPS H102-BLADECENTER 2 Virtex-4 LX100 0.5 MBytes RAM distributed across FPGA, 0.5 TBytes/sec bandwidth 16 MBytes DDR-II SRAM across 4 banks, 6.4GBytes/sec total bandwidth 512 MBytes DDR2 SDRAM in 1 bank, 3.2GBytes/sec bandwidth 64 200 640 200MHz 16x 2.5 Gbit/sec serial links 340ns 12.8 GigaFLOPS 40 GigaFLOPS 128 GigaOPS H114-BLADECENTER 14 Virtex-4 LX100 0.5 MBytes RAM distributed across FPGA, 0.5 TBytes/sec bandwidth 16 MBytes DDR-II SRAM across 4 banks, 6.4GBytes/sec total bandwidth 512 MBytes DDR2 SDRAM in 1 bank, 3.2GBytes/sec bandwidth 448 1,400 4,480 200MHz 56x 2.5 Gbit/sec serial links 340ns 89.6 GigaFLOPS 280 GigaFLOPS 896 GigaOPS
System Performance
Double Precision Floating Point Single Precision Floating Point Integer 16
Actual performance is dependant on the end application and the extent to which the algorithms can be pipelined or parallelized.
Power Consumption
Total Power Consumption (typical) 25W 50W 150W 500W
Development Tools Support
Supported Compilers DIME-C Impulse-C Mitrionics Mitrion-C Not Applicable DIME-C Impulse-C Mitrionics Mitrion-C Not Applicable DIME-C Impulse-C Mitrionics Mitrion-C Intel Xeon Processor 5110 (1.60GHz, 1066MHz) 2x2MB L2 Cache, Dual Core* DIME-C Impulse-C Mitrionics Mitrion-C Intel Xeon Processor 5110 (1.60GHz, 1066MHz) 2x2MB L2 Cache, Dual Core*
Host Configuration
HS21 Blades
Ordering Information
H101 PCI-X Mainstream H102 BladeCenter expansion blade H102 BladeCenter Solution: IBM BladeCenter Chassis, H102 blade H114 BladeCenter Solution: IBM BladeCenter Chassis, 7 H102 blades H1XX BladeCenter Solution: IBM BladeCenter Chassis with choice of 4, 6, 8, 10 or 12 FPGAs Nallatech HPC Software Toolkit H101-PCIXM H102-EBLADE H102-BLADECENTER H114-BLADECENTER H1XX-BLADECENTER (replace XX with the number of FPGAs: 04, 06, 08, 10 or 12) H100-DEVKIT-S
Contact us today for more information: North America Toll Free: 1-877-44-NALLA Email: [e-mail] EMEA, APAC & ROW Phone: [phone] Email: [e-mail]
Visit www.nallatech.com/hpc for further information
Document: NT190-0313/Version 1.5/April 2007. Intellectual Property: The contents of this document are the copyright of Nallatech Limited Nallatech Limited 2007. All rights reserved. Nallatech, the Nallatech logo, "The High Performance FPGA Solutions Company", DIMEtalk, DIMEscript, DIME-II and FUSE are all trade marks of Nallatech Limited. All names, images and logos identifying Nallatech Limited or third parties and their products and services are subject to copyright, design rights and trade marks of Nallatech Limited and/or third parties. Nothing contained in these terms shall be construed as conferring by implication, estoppel or otherwise any license or right to use any trademark, patent, design right or copyright of Nallatech Limited, or any other third party. Microsoft and Windows are either registered trade marks or trade marks of Microsoft Corporation in the United States and/or other countries. Disclaimer: This document is for general information purposes only and is not tailored for any specific situations or circumstances. Although Nallatech Limited believes the contents to be true and accurate as at the date of writing, Nallatech Limited makes no assurances or warranty regarding the accuracy, currency or applicability of any contents in relation to specific situations and particular circumstances. As such, the content should not be relied upon and readers should not act on this information without further consultation with Nallatech Limited. Nallatech Limited accepts no responsibility for loss which may arise as a result of relying on the information in this document alone.
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Virtex-4 Family Overview
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DS112 (v2.0) January 23, 2007
Preliminary Product Specification
General Description
Combining Advanced Silicon Modular Block (ASMBLTM) architecture with a wide variety of flexible features, the VirtexTM-4 Family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform families--LX, FX, and SX--offering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 hard-IP core blocks includes the PowerPCTM processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex- 4 building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90-nm copper process using 300-mm (12-inch) wafer technology..
Summary of Virtex-4 Family Features
Three Families -- LX/SX/FX
Virtex-4 LX: High-performance logic applications solution Virtex-4 SX: High-performance solution for digital signal processing (DSP) applications Virtex-4 FX: High-performance, full-featured solution for embedded platform applications Digital clock manager (DCM) blocks Additional phase-matched clock dividers (PMCD) Differential global clocks 18 x 18, two's complement, signed Multiplier Optional pipeline stages Built-in Accumulator (48-bit) and Adder/Subtracter Distributed RAM Dual-port 18-Kbit RAM blocks Optional pipeline stages Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.
SelectIOTM Technology
1.5V to 3.3V I/O operation Built-in ChipSyncTM source-synchronous technology Digitally controlled impedance (DCI) active termination Fine grained I/O banking (configuration in one bank)
XesiumTM Clock Technology
-
XtremeDSPTM Slice
-
Smart RAM Memory Hierarchy
-
Flexible Logic Resources Secure Chip AES Bitstream Encryption Copper 90-nm CMOS Process 1.2V Core Voltage Flip-Chip Packaging including Pb-Free Package Choices RocketIOTM 622 Mb/s to 6.5 Gb/s Multi-Gigabit Transceiver (MGT) [FX only] IBM PowerPC RISC Processor Core [FX only]
PowerPC 405 (PPC405) Core Auxiliary Processor Unit Interface (User Coprocessor)
Multiple Tri-Mode Ethernet MACs [FX only]
-
Table 1: Virtex-4 FPGA Family Members
Configurable Logic Blocks (CLBs) (1) Array (3) Row x Col Logic Cells
Block RAM
Ethernet MACs RocketIO Transceiver Blocks Total Max I/O User Banks I/O
Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160
Slices
PowerPC Max Max Processor Distributed XtremeDSP 18 Kb Block Slices (2) Blocks RAM (Kb) DCMs PMCDs Blocks RAM (Kb)
64 x 24 96 x 28 128 x 36 128 x 52 160 x 56 192 x 64 192 x 88
13,824 24,192 41,472 59,904 80,640
6,144 10,752 18,432 26,624 35,840
96 168 288 416 560 768 1056 1392
32 48 64 64 80 96 96 96
48 72 96 160 200 240 288 336
864 1,296 1,728 2,880 3,600 4,320 5,184 6,048
4 8 8 8 12 12 12 12
0 4 4 4 8 8 8 8
N/A N/A N/A N/A N/A N/A N/A N/A
N/A N/A N/A N/A N/A N/A N/A N/A
N/A N/A N/A N/A N/A N/A N/A N/A
9 11 13 13 15 17 17 17
320 448 640 640 768 960 960 960
110,592 49,152 152,064 67,584
XC4VLX200 192 x 116 200,448 89,088
20042007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS112 (v2.0) January 23, 2007 Preliminary Product Specification
www.xilinx.com 1
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Virtex-4 Family Overview
Table 1: Virtex-4 FPGA Family Members (Continued)
Configurable Logic Blocks (CLBs) (1) Array (3) Row x Col Logic Cells
Block RAM
Ethernet MACs RocketIO Transceiver Blocks Total Max I/O User Banks I/O
Device XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
Slices
PowerPC Max Max Processor Distributed XtremeDSP 18 Kb Block (2) Blocks RAM (Kb) DCMs PMCDs Slices Blocks RAM (Kb)
64 x 40 96 x 40 128 x 48 64 x 24 64 x 36 96 x 52 128 x 52 160 x 68 192 x 84
23,040 34,560 55,296 12,312 19,224 41,904 56,880 94,896
10,240 15,360 24,576 5,472 8,544 18,624 25,280 42,176
160 240 384 86 134 291 395 659 987
128 192 512 32 32 48 128 160 192
128 192 320 36 68 144 232 376 552
2,304 3,456 5,760 648 1,224 2,592 4,176 6,768 9,936
4 8 8 4 4 8 12 12 20
0 4 4 0 0 4 8 8 8
N/A N/A N/A 1 1 2 2 2 2
N/A N/A N/A 2 2 4 4 4 4
N/A N/A N/A N/A 8 12 16 20 24
9 11 13 9 9 11 13 15 17
320 448 640 320 320 448 576 768 896
142,128 63,168
Notes: 1. One CLB = Four Slices = Maximum of 64 bits. 2. Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator 3. Some of the row/column array is used by the processors in the FX devices.
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
Up to twenty Digital Clock Manager (DCM) modules
Precision clock deskew and phase shift Flexible frequency synthesis Dual operating modes to ease performance trade-off decisions Improved maximum input/output frequency Improved phase shifting resolution Reduced output jitter Low-power operation Enhanced phase detectors Wide phase shift range
500 MHz XtremeDSP Slices
Dedicated 18-bit x 18-bit multiplier, multiply-accumulator, or multiply-adder blocks Optional pipeline stages for enhanced performance Optional 48-bit accumulator for multiply accumulate (MACC) operation Integrated adder for complex-multiply or multiply-add operation Cascadeable Multiply or MACC Up to 100% speed improvement over previous generation devices. Up to 10 Mb of integrated block memory Optional pipeline stages for higher performance Multi-rate FIFO support logic
Full and Empty Flag support Fully programmable AF and AE Flags Synchronous/ Asynchronous Operation
Companion Phase-Matched Clock Divider (PMCD) blocks Differential clocking structure for optimized low-jitter clocking and precise duty cycle 32 Global Clock networks Regional I/O and Local clocks Up to 40% speed improvement over previous generation devices Up to 200,000 logic cells including:
Up to 178,176 internal registers with clock enable (XC4VLX200) Up to 178,176 look-up tables (LUTs) Logic expanding multiplexers and I/O registers
500 MHz Integrated Block Memory
Flexible Logic Resources
Cascadable variable shift registers or distributed memory capability
Dual-port architecture Independent read and write port width selection (RAM only) 18 Kbit blocks (memory and parity/sideband memory support) Configurations from 16K x 1 to 512 x 36 (4K x 4 to 512 x 36 for FIFO operation) Byte-write capability (connection to PPC405, etc.) Dedicated cascade routing to form 32K x 1 memory without using FPGA routing Up to 100% speed improvement over previous generation devices.
DS112 (v2.0) January 23, 2007 Preliminary Product Specification
www.xilinx.com 2
DIMEtalk Overview
1.1.2
How DIMEtalk Works Within a Nallatech FPGA Computing System
Figure 1 shows how DIMEtalk abstracts the features of the hardware platform to provide an easy to use development environment for implementing applications on multi-FPGA systems. Standard VHDL design flows are complemented with support for third-party compiler tools alongside an integrated C to VHDL Function Generator, DIME-C, enabling developers to select the design flow most appropriate to their application. Communications networks between algorithm blocks, memory and I/O interfaces can be rapidly created across multiple FPGAs through the GUI-based application development environment. This functionality enables users to develop complex high performance FPGA Computing applications more easily, reducing risk, cost and shortening time to market.
FPGA 0
FPGA 1
FPGA 2
Point-to-Point links across DIME-II Interconnect Fabric Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm
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DIMEtalk network fabric
FUSE firmware DIME-II FPGA Computing Hardware FUSE FPGA Computing Runtime Software Host System
Figure 1: DIMEtalk in FPGA System
1.1.3
DIMEtalk Components
Once a user is familiar with how DIMEtalk works within an FPGA system it is important to consider the components which make up a DIMEtalk network. Data networks are a well established way of communicating data around systems yet many existing networking standards are overly cumbersome and overhead-heavy for use in FPGA systems. The simple network design and low overhead of DIMEtalk has been developed specifically for communications within FPGAs and between FPGAs in close proximity. Interfaces to longer distance and backplane interfaces mean that DIMEtalk can be used in conjunction with these standards. DIMEtalk networks are composed of four categories of underlying network components which the user can build together as required, to form the network on an application-specific basis. The components are FPGA IP blocks, available through the software tool, DIMEtalk System Design, and are shown in Table 2.
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www.nallatech.com
DIMEtalk 3.1 User Guide
Generic Symbol
Description
Routers direct data around the network and interconnect all other component types within a physical device. Bridges move data between physical devices across a defined physical media (i.e. between FPGAs). Nodes are the user interface to the network and can be connected to User FPGA designs via node interfaces (Block RAM,SRAM, DDR SDRAM, ZBT, FIFO, Memory Map).
DIMEtalk System Design Symbol
Edges interface the network to/from another data transfer standard (such as PCI, PCI-X,VME, Ethernet or USB on Nallatech cards).
Table 2: DIMEtalk Components
Figure 2 shows how these components can be used in an example multiple FPGA network on Nallatech hardware (BenNUEY motherboard, BenDATA and BenADDA modules). The role of each network component is explained below. 1. 2. 3. The Edge component allows the network to interface with the PCI FPGA. The Router receives data from its edge component. Routers pass data around the network and connect all the component types within the device. The Router passes data to Nodes which are the user interface to the network.
NT107-0305 Issue 3 November 24, 2006
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Getting Started
CD_Drive:\ autorun.exe. In the DIMEtalk menu which appears, click on `Install DIMEtalk Design Tools'. 2. The DIMEtalk setup wizard appears. Work through the series of dialog boxes until the `Finish' box is reached. Click `Finish' to install the software.
3.
2.2
Building a DIMEtalk Network
This section describes how to create an initial DIMEtalk network and provides an introduction to the tool and its various components. This initial example can be used to explore the various options in the DIMEtalk System Design toolbar and menus, and to become familiar with the network creation process. Figure 4 shows a simple network in the DIMEtalk System Design tool containing a node, a router and an edge. Note that the exact order of the component tabs are configurable so they may not look the same between different systems.
Figure 4: Initial DIMEtalk Network
Figure 5 shows how these components (node, router edge) relate to the physical hardware used - in this case a BenNUEY-PCI motherboard
FPGA #0
R E
N
PCI I/F
Figure 5: Initial DIMEtalk Network Projected onto Hardware
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NT107-0305 Issue 3 November 24, 2006