4930/5934 EEL Reconfigurable Computing Midterm Exam Spring Semester 2010
18 pts.
Name ___________________________________
1. Systolic Architecture (a) Given the following algorithm in pseudo-code, draw a datapath that is fully-pipelined and with the maximum loop-unrolling. for (i=1; i < 10000; i++) { z[i] = avg(a[i-1] + a[i] + a[i+1]); } Assume the memory bandwidth is 64 bits and data items are 16 bits.
(b) Calculate the speedup of the above circuit (assuming the FPGA clock rate of 200 MHz) as compared to the corresponding software executing on a microprocessor (assume 15 instructions for each iteration, a CPI of 2, and clock frequency of 3 GHz).
(c) Using the same assumptions as above except the memory bandwidth is increased to 128 bits, calculate the speedup of the resulting circuit (using the maximum amount of loop unrolling) as compared to the corresponding software executing on a microprocessor.
1
EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
16 pts.
Name ___________________________________
2. Smart Buffer This problem makes use of the algorithm (pseudo code) and the systolic architecture of Problem 1, but with the following design and assumptions.
addr 6 5 p15 4 p11 3 2 p7 1 p3 0 xx Smart Buffer Input BRAM etc. etc. p16 p17 p12 p13 p8 p9 p4 p5 xx p1 32
Assumptions: p18 p14 p10 p6 p2
Memory bandwidth is 32 bits. Data item are 8 bits. However, we want the bandwidth into the datapath to be 48 bits. For that reason, a smart buffer is used. This smart buffer is similar to the one explained in class. The difference is that this smart buffer only uses 6 bytes (instead of the 8-byte one in class).
48 Datapath
(a) Specify the contents of the smart buffer after each of the following clock cycle. after clock cycle 1 after clock cycle 2 after clock cycle 3 after clock cycle 4 (b) Briefly describe what happens at each clock cycle. Keep the algorithm as uniform as possible. Cycle 1:
Cycle 2:
Cycle 3:
Cycle 4:
2
EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
16 pts.
Name ___________________________________
3. Memory Map and Glue Logic Code Given below is a block diagram of a DIMEtalk memory map node and how it is interfaced to the Glue Logic similar to that of Lab 3. (To/From addr[31..0] (To/From go TopLevel reset en PCIX bus) VHDL dt_clk Memory Glue done wen module) Map node Logic data_in data_in[31..0] result[31..0] data_out data_out[31..0] dt clk Given below is the part of the C program relevant to the writing of the "go" signal and the reading of the "done" and "result" signals. Note for both FPGA_read and FPGA_write, the parameter list is (data, wordcount, address, node, timeout). go = 1; done = 0; FPGA_write(&go,1,2,MemMap,1000); while(done != 1) { FPGA_read(&done,1,3, MemMap,1000); } FPGA_read(&result,1,5,MemMap,1000) (a) Complete the following VHDL code (a part of the Glue Logic module) that handles the "go" , "done", and "result" signals. Assume that the PORT statement has been defined and use the signal names shown in the block diagram above.
ARCHITECTURE Behavioral OF GlueLogic IS SIGNAL BEGIN PROCESS( BEGIN IF
)
END IF; END PROCESS; END Behavioral;
3
EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
16 pts.
Name ___________________________________
4. Glue Logic Circuit Diagram Based on the glue logic code you gave in Problem 3, draw the circuit diagram that corresponds to the VHDL code. You can use components such as flipflops, registers, mux's, comparators, and any gates.
Flip-flop D EN Q 32-bit register D[31..0] EN Z[31..0] 2-to-1 MUX D Z EN sel
32-bit comparator Addr[31..0] Z Value [31..0] True or False
Glue Logic component
addr[31..0]
en
wen
done result[31..0]
data_in[31..0]
go data_out[31..0]
dtclk
(assume connected to all necessary components)
4
EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
18 pts.
Name ___________________________________
5. Analysis of VHDL code Sometimes to debug the VHDL code of a controller, it is necessary to reverse-engineer the code to determine its timing behavior and the corresponding ASM chart. Given below is the VHDL code below of a controller. On the next page, (a) determine its timing behavior and (b) construct the corresponding ASM chart. ENTITY Contr IS PORT ( Clock, Resetn, Go : IN STD_LOGIC ; EnY, EnZ : OUT STD_LOGIC ) ; END Contr; ARCHITECTURE ASMArch OFContr IS SIGNAL state : STD_LOGIC_VECTOR (1 DOWNTO 0) ; BEGIN PROCESS (Resetn, Clock) BEGIN IF Resetn = '0' THEN state <= "10"; ELSIF (Clock'EVENT AND Clock = `1') THEN CASE state IS WHEN "00" => IF Go = `0' THEN state <= "00"; ELSE state <= "10"; END IF; WHEN "01" => state <= WHEN "10"; "10" => IF Go = `0' THEN state <= "00"; ELSE state <= "01"; END IF;
WHEN OTHERS =>
state <= "10"; END CASE ; END IF ; END PROCESS ; PROCESS (state, Go) BEGIN EnY <= `0'; EnZ <= `0'; CASE state IS WHEN "00" => WHEN "01" => EnY <= `1'; WHEN "10" => EnZ <= `1'; IF Go = `0' THEN EnY <= `1'; END IF;
WHEN OTHERS =>
END CASE ; END PROCESS ; END ASMArch ;
5
EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
Name ___________________________________
(a) Based on the VHDL code from the previous page complete the following timing diagram for state, Eny, and EnZ..
20 pts.
Clock state Resetn Go EnY EnZ
(a) (b) Based on the VHDL code from the previous page, complete the corresponding ASM chart using state boxes, conditional outputs, etc. State 00
00
10
6
EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
16 pts.
Name ___________________________________
6. FPGA configuration block details. Specify the portion of the bit stream (A through I) required to program a Virtex slice to implement the logic circuits specified in following VHDL statements: Y <= (G4 AND G3) OR ((NOT G2) AND G1); IF (CLK'EVENT AND CLK ='1') THEN XQ <= (F3 AND F2) + (NOT F1);
IMPORTANT NOTE: For "don't care" values, be sure to use `X' instead of `0' or `1'.
.....
rest of bit stream
A
B
C
D
E
F
G
H
I
.....
...
2 3 4 5 6 7 8 9 10 11 12 13 14 15 ]
LUT1 [ 0
1
...
LUT2 [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ]
... ...
rest of bit stream
...
B D E
G4 G3 G2 G1
LUT1
A C
Y
H I
F4 F3 F2 F1
XQ
G
LUT2
F
0 Definition of MUXs 1
S
00 01 10
M N
G4 G3 G2 G1 Y 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
F4 F3 F2 F1 XQ 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
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EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
ENTITY _entity_name IS PORT(__input_name, __input_name __input_vector_name __bidir_name, __bidir_name __output_name, __output_name END __entity_name; ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : STD_LOGIC; SIGNAL __signal_name : STD_LOGIC; BEGIN -- Process Statement -- Concurrent Signal Assignment -- Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement END a;
Name ___________________________________
: IN STD_LOGIC; : IN STD_LOGIC_VECTOR(__high downto __low); : INOUT STD_LOGIC; : OUT STD_LOGIC);
__instance_name: __component_name PORT MAP (__component_port => __connect_port, __component_port => __connect_port); WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value; __signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE __expression; IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF; CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; WAIT UNTIL __expression;
<generate_label>: FOR <loop_id> IN <range> GENERATE -- Concurrent Statement(s) END GENERATE;
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EEL 4930/5934 Reconfigurable Computing Midterm Exam Spring Semester 2010
Name ___________________________________
IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer gets the most points.
SUMMARY SHEET: Problem: 1 (18 pts) 2 (16 pts) 3 (16 pts) 4 (16 pts) 5 (18 pts) 6. (16 pts) Points:
Total
Re-Grade Information: _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________
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