Test COMP541, #1 SAMPLE QUESTIONS
Wednesday, March 28, 2012
Notes:
This exam will be take-home. Your work is due at the beginning of class on Monday,
April 2, 2012.
This exam is open-book, open-notes, though you may not consult other people or
resources on the Internet.
You should set aside a 2-hour period to complete the exam.
There will be approximately 15 questions.
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1. (2 points) What is the sum (in hex) of (1E)16 + (8C)16 ?
2. (2 points) What is the parity (even or odd) of each of the following numbers?
a. 10001101
b. 00110100
3. (4 points) Draw the logic diagram (i.e., circuit schematic) by hand for the following function.
The diagram should correspond exactly to the function. Only W, X, Y and Z are available
as inputs; their complements are not available.
O =W X Y + W Z + X Y
4. (4 points) The gates in the following circuit each have a propagation delay of 1ns (worst case
of low-to-high and high-to-low delays). What is the maximum propagation delay? Please
indicate the longest path in the circuit. NOTE: Assume that the bubbles (i.e., the little circles
representing inversion) are part of the gate they are attached to, and that they do not cost any
extra delays. In this question, assume that complemented versions of inputs are available as
shown.
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5. (6 points) Write a truth table for the following circuit
6. (8 points) Write Verilog code to drive output E high whenever the input BCD digit is illegal.
Recall that a BCD digit is a 4-bit value that represents an integer from 0 through 9. Values
10 15 through would be illegal in BCD encoding.
module BCD_error(bcd, E);
input [3:0] bcd;
output E;
...
endmodule
7. (8 points) Design a circuit with two 2-bit numbers (A[1:0] and B[1:0]) as input that generates
their product as a 4-bit output (P[3:0]). For your answer, (i) create a truth table, and (ii) write
the logic equations for P[3], P[2], P[1] and P[0] (no need to draw circuit).
8. (5 points) Write a dataflow Verilog program for the previous problem.
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9. (14 points) A sequential circuit (below) has one D flip-flop (call it A), two inputs X and Y,
and one output S.
a. (7) Derive the state table (please write legibly and label the columns carefully).
b. (7) Draw the state diagram (with circles and arrows).
10. (20 points) A state machine (below) has four states, one input, X, and one output Y. It is a
Moore machine, i.e., its output depends only on its state.
(a) Code this state machine in Verilog (use the next page). Feel free to make a state table if
that will help you, but it is not necessary.
(b) Describe in a sentence what this state machine does.
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1
0
00/1
0
1
11/0
01/0
1
0
10/0
0
1
module prob(clk, X, Y)
input clk;
input X;
output Y;
...
endmodule
11. (10 points) Memory systems.
a. (2) How many 4K x 16 memory chips are needed to build an 8K x 32 memory
system?
b. (2) How many address wires are necessary for the memory system?
c. (6) Either draw a block diagram (with the address and data wires carefully labeled) or
write a Verilog module that implements the 8K x 32 memory system.
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