3342
EEL
Introduction EEL to Digital Circuits and
Introduction
Systems
Systems
Registers and Counters
Registers
Registers
Several FFs can be grouped together with a common clock to
from a register. This register uses a gated clock.
Registers
Registers
Since clock enables may affect the setup time of the FFs and
cause timing problems, FFs with clock enables can be used in the
register.
Register Transfers
Register
Transferring data between registers is a common operation in
digital systems.
Register Outputs
Register
Tri-state buffers can be connected to the outputs of a register.
Register Transfers on Tri-State Bus
Register
Tri-state buses can be used to transfer data between registers.
Parallel Adder with Accumulator
Parallel
In computer circuits, it is frequently desirable to store one number
in a register, called accumulator, and add a second number to it,
leaving the sum stored in the accumulator.
Shift Registers
Shift
A shift register is a register in which data can be stored, and this
data can be shifted to the left or right when a shift signal is
applied.
Shift
Registers
Registers
Serial Shift Registers
Serial
Shift registers with 4, 8, or more FFs are available in integrated
circuits form.
Serial Shift Registers
Serial
Parallel-In, Parallel-Out Shift Registers
Parallel-In,
Parallel-in implies that all bits can be loaded at the same time
while parallel-out implies that all bits can be read at the same
time.
Parallel-In, Parallel-Out Shift Registers
Parallel-In,
Parallel-In,
Parallel-Out
Shift Registers
Shift
Shift Register with Feedback
Shift
Binary Counter
Binary
A synchronous counter is a counter in which the states of the FFs
change simultaneously.
First, we will use three T FFs in the binary counter. The FFs
change states at the falling or rising edge of the clock.
The state of the counter is determined the by states of the FFs.
Initially all FFs are set to 0. When a pulse is received, the counter
will change to state 001. When a second pulse is received, the
counter changes state to 010, etc
The sequence of the FF states is CBA = 000, 001, 010, 011, 100,
101, 110, 111, 000,
Binary
Counter
Counter
Up-Down Binary Counter
Up-Down
An up-down binary counter has two inputs U and D.
When U = 1, the counter counts up in the sequence 000, 001, 010,
011, 100, 101, 110, 111, 000
When D = 1, the counter counts down in the sequence 000, 111,
110, 101, 100, 011, 010, 001, 000,
When U = D = 0, the counter state does not change.
The case in which U = D = 1 is not allowed.
Up-Down Binary Counter
Up-Down
Up-Down Binary Counter
Up-Down
This counter can be implemented using D FFs as follows:
Counter for Other Sequences
Counter
In some applications, the sequence of states of a counter is not in
straight binary order.
Counter
for
Other
Sequences
Sequences
The counter can be implemented using T FFs.
Their input equations can be derived from
next-state maps.
Counter
for
Other
Sequences
Sequences
Counter
for
Other
Sequences
Sequences
Counters for Other Sequences
Counters
What happens if the counter is set initially to the state CBA = 001 and
a pulse is applied?
By tracing the signals through the network, it is clear that TC = TB = 0
and TA = 1. As a result, states A and B change and the state of the
counter changes from 001 to 111.
Counter Using D Flip-Flops
Counter
Assume the same counter is implemented using D FFs.
Counter
Using
D Flip-Flops
Flip-Flops
Note that for a D FF, Q+ = D, so the D input map is identical with
the next-state map:
DC = C+ = B
DB = B+ = C + BA
DA = A+ = A(C + B)
Counter Using
D Flip-Flops
DC = C+ = B
DB = B+ = C + BA
DA = A+ = A(C + B)
Counter Design Using S-R FFs
Counter
Counter
Design
Using
S-R FFs