Midterm EE555 Solutions
1. True/False: T, F, T, F, T, T, T, F, F, F, F, F, T, F, T, F, T, F, F, T, F, F, 75, F, T
2. Multiplexing Strategies
The average arrival rate of flow one is 1 = 5000 packets per second. Similarly, the
average arrival rates for flows two through four are 2 = 3 = 4 = 1000 packets per
second. On the other hand, the link can serve packets at an average rate of =
10000 packets per second. Denote i = the average service rate allocated to flow I,
in packets/sec. Denote T: The total time spent in system, both waiting and being
served.
Scenario A:
i.
ii.
iii.
=
2
=
3
=
4
= 10000/4 = 2500 packets/second
Since 1 > 1, the queue length for flow 1 grows without bound, or until
packets are dropped. We say its mean delay is infinity.
The mean delay for the other three flows is E(T) = 1/( i- i)= 1/(2500-1000)
= 0.67 msec
The mean delay averaged over all packets is infinite.
Scenario B:
i.
ii.
iii.
1
1
= 10000*(5/8) = 6250 and
2
=
3
=
4
= 10000/8 = 1250 packets/sec
The mean delay for flow 1 is 1/(6250-5000)=0.8 msec
The mean delay for the other three flows is 1/(1250-1000)=4 msec.
The overall average delay is (0.625*0.8+0.125*4+0.125*4+0.125*4)= 2 msec.
This result is a substantial improvement over the allocation used in Scenario
A.
Scenario C: (i)-(iii) the total arrival rate, summed over all flows is 8000. Thus the
average delay for each flow and the overall average delay are all 1/(10000-8000)=
0.5 ms, a significant improvement over the allocation used in Scenario A and B,
showing that statistical multiplexing can lead to smaller delays
3. Scheduling Strategies:
The round number for the arriving packets given their arriving times is as shown
below:
The GPS server will become Idle at Round Number 7.
Bit-by-bit GPS would transmit two packets (P1,1 and P3,1) in the first round, so the
round takes two time units and the slope is 1/2. In the second round, only one
packet is being transmitted (P1,1), the round duration is one time unit and the slope
is 1/1. The GPS server completes two rounds by time 3, hence R(3) = 2, at which
point two new packets arrive (P2,1 and P4,1) and the slope of the R(t) becomes 1/3.
And so onThe left side of the above diagram shows how the packet arrival times
are mapped into the round number units.
The order actual of transmissions under packet-by-packet FQ is based on the
Finishing Numbers. At time 0 the finish numbers are: F(1,1) = 4 and F(3,1) = 1, so
packet P3,1 is transmitted first and packet P1,1 goes second. At time 3 the finish
numbers for the newly arrived packets are: F(2,1) = max{0, R(3)} + L(2,1) = 2 + 4 = 6
and F(4,1) = max{0, R(3)} + L(4,1) = 2 + 2 = 4, so F(4,1) < F(2,1). Note that the
ongoing transmission of packet P1,1 is not preempted and will be completed at time
5, at which point packet P4,1will enter the service. At time 6 the finish number for
packet P3,2is F(3,2) = max{0, R(6)} + L(3,2) = 3 + 1 = 4. The current finish numbers
are F(3,2) < F(2,1) so P3,2 enters the service at time 7, followed by P2,1 which enters
the service at time 8. Finally, at time 12 the finish number for the new packet P3,3
is F(3,3) = max{0, R(12)} + L(3,3) = 6 + 1 = 7 and it is transmitted at 12. The FQ
server will be idle at t = 13.
In summary, The order of transmissions under packet-by-packet FQ is:
P3,1, P1,1, P4,1, P3,2, P2,1, P3,3.
4. Traffic Regulation and Shaping
The Token Counter = 200 Queue Length
The smallest bucket depth for the stream to conform to the filter is 50 .
This is because the total # of bits transmitted in 30 msec is 500 bits = b+rT
or b = 500 (15K)(30msec) = 50 bits
5. Switching Architecture:
a. STS switch (for a diagram refer to Homework #3) with N = 16, n = 128, k =
unknown, P(Blocking) = 0.002 and p = channel occupancy = 0.1. Number of bits
per channel is 8 bits.
P(Blocking) = (1-q'2)k = (1-(1-p')2)k = (1-(1-(p(N/k))2))k from which we get k = 7
# of cross points = (2)(7)(16) = 224
# of bits in Control memory for space switches = (2)(7)(128)(4) = 7168 bits
# of bits in Data memory for the time switches = (7)(128)(8) = 7168 bits
# of bits in Control memory for the time switches = (7)(128)(7) = 6272 bits
b.
Minimum required size of the RAM = 512 * 16 = 8192 Bytes = 216 bits
Number of rows in memory = 216/25 = 211 rows. Hence we need 11 bits to
address each row.
Processing time per channel = {(512x8)/32}* {2+2+1} = 640 nsec/channel.
Transmission time per channel = 0.4sec/16 = 25 nsec. Hence total time is 665
nsec. The Throughput is hence (512)(8)/665 = 6.15Gbps
Switching speed = 6.15G/(512)(8) = 1.5M packet/sec