2300
Problem ECE Set 8
ECE 2300
Problem Set 8
Due: November 9, 2011, 1:25 PM
1.
Counter Design
Using two 74163 counters and logic gates, design a free-running counter that counts from 0 to
12, 23 to 30. That is, the counters output should repeat the sequence {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 23, 24, 25, 26, 27, 28, 29, 30}.
2. Control of SRAM
Roughly sketch the timing diagram of a SRAM, including both inputs and outputs, performing
the following series of operations.
Write 0x3E to address 0x04.
Write 0xFF to address 0x4C.
Read the contents of 0x04.
Your diagram should include the following signals: address (ADDR), data in (DIN), data out
(DOUT), write enable (WE_L), chip select (CS_L), and output enable (OE_L). All select/enable
lines are active low. Multi-bit lines like address, data in, and data out can each be represented
with a single signal showing the aggregate value.
3. DRAM Refresh Controller
In this problem, we will design a circuit to automatically perform refreshes for a DRAM. We will
design the refresh controller for a DRAM with 4096 rows. Each bit must be refreshed at least
once every 64 ms. With 4096 rows, a refresh must be initiated every 15.6 s. Our clock will be
running at 100 MHz.
a. Refresh Row
First, design a circuit to perform one refresh. The circuit takes as input CLK, REFRESH,
and ADDR_IN. It has two outputs, and RAS_L ADDR_OUT. RAS_L is active-low. When a
refresh cycle is to be performed, REFRESH will go high and ADDR_IN will be valid for one
cycle. To perform the refresh, active-low output RAS_L should go low for two cycles and
ADDR_OUT needs to be the valid ADDR_IN for at least one cycle. The timing diagram
below shows one refresh operation.
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ECE 2300
Problem Set 8
b. DRAM Timer
We must initiate a new refresh every 15.6 s. Suppose we have a 12-bit counter with
synchronous clear, count enable, and carry out as shown below.
Design a circuit that has one output, REFRESH, which will go high for one cycle at least
once every 15.6 s. (Note: Although refreshing faster than one row every 15.6 s will still
ensure the integrity of the data, refreshing more often than necessary wastes power.
Your circuit should not refresh more than necessary.)
c. Row Generator
Every refresh, a different address needs to be used so that all rows are refreshed. Using
the 12-bit counter from part (b), create a circuit that has inputs CLK and NEXT and
outputs a 12-bit address. Every time NEXT goes high, a new address should be output.
d. Full Controller
We now have the basic modules needed to refresh the DRAM.
Using these modules, create a circuit that will automatically refresh the DRAM as
needed with only a CLK signal as input. (Ignore resets for the modules.)
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