Sizing ECEN
4303
Digital
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Design
Transistor in Inverters
Maximizing Inverter Speed (minimize delay) It is important to understand that the DC transfer curve is not of much use in predicting transient behavior, i.e. switching delays, because the input, Vin, must change very slowly for the DC transfer curve to be valid. Correct determination of transient behavior during switching requires including effects of parasitic capacitances. These capacitances are a consequence of the IC fab process and cannot be entirely eliminated. Recall that earlier we found that the wire delay was 1 2 T d -- rcL 2 If we regard the FET as a (non-linear) wire, this formula holds for the FET also. The simplest thing a designer can do to minimize delay is to use minimum channel length (smallest possible L) for all FETs in the logic gate. This is always done when designing CMOS logic gates for both the p-channel and n-channel devices. This applies to all types of gates; not just in inverters. Finding a value for the transistor widths, W, that minimize delay is more difficult. Although the width does not effect the wire delay through the transistor itself, W does have an effect on the on channel resistance (recall Ron = RsL/W) and therefore also effects inverter delay. The inverter delay in our simplified switching model is RC which would seem to imply that the delay can be reduced by increasing W to make R smaller. However, we must first take into account how changing transistor widths changes the capacitance, C. Estimating Width Dependence of Load Capacitance Consider an inverter driving circuit node i. Assume that only another single inverter is driven by this node. Ci
driver
load
The interconnect resistances have been assumed to be negligible and the capacitances have been lumped into a single node capacitance, Ci, which includes parasitic capacitances from the transistors in the driver and transistors in the load as well as the wire connecting the gates together. It will be convenient to divide the node capacitance into three components, C i = C out + C wire + C in , where Cout depends on the width of the driver
driver
Transistor Sizing in Inverters
Cout
Cwire
Cin
load
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August 19, 2009
ECEN
4303
Digital
VLSI
Design
transistors, Cin depends on the width of the load inverter transistors, and Cwire is independent of transistor widths. When logic gates are connected with short wires, Cwire is negligible compared with the other two. Consider a horizontal style layout for an inverter driving another inverter of the same size.
Ci
poly Vdd p-channel Wp pdiff metal p-gate n-gate
n-channel
Wn GND
ndiff
Ci (the majority of logic gates in the circuit are about the same size to get good packing density of gates into the chip). The layout clearly shows that the sizes of parts of the node depend on Wn and WP. The three major components of the node capacitance are as follows. The MOSIS Deep Submicron SCMOS design rules are used.
Transistor Sizing in Inverters
August 19, 2009
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ECEN
4303
Digital
VLSI
Design
inverter output capacitance: Vdd p-channel Wp pdiff metal p-gate n-gate
poly
n-channel
Wn GND
ndiff
Cout The contributions from each layer to the inverter output capacitance are: C gn C gp 1 Cg 1 Cg --C g = -- ----- W n L n + -------- W n + -- ----- W p L p + -------- W p P P 2 A 2 A C nd C ndg C nd 2 C ndiff = -------- ( W n 4 + 4 ) + -------- ( W n + 10 ) + ---------- W n A P P C pd C pdg C pd 2 C pdiff = -------- ( W p 4 + 4 ) + -------- ( W p + 10 ) + ---------- W p A P P Cm1 ( W n -4 ) ( W p -4 ) C m 1 = --------- 4 12 + -------------------- + -------------------- A 2 2 Cm1 ( W n -4 ) ( W p -4 ) + --------- 12 + -------------------- + 4 + -------------------- + 4 P 2 2 The other half of the gate capacitance is not included since it is connected to the ground or power node, not the output node. Since both transistors are switching (one switching on and the other off), the Miller effect has been included in the gate contribution. The gate overlap capacitance is much more important in modern deep submicron processes and cannot be neglected. The metal area over diffusion does not contribute to the capacitance since the diffusion screens the metal from the substrate. If the parts of the capacitance that depend on Wn and Wp are grouped together, the total inverter output capacitance is
Transistor Sizing in Inverters
August 19, 2009
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ECEN
4303
Digital
VLSI
Design
C out = C g + C ndiff + C pdiff + C m 1 C out C out = --------- W n + --------- W p + C outI Wn Wp where C out = 1 C g L + C gn + C nd 4 + C nd + C ndg + C m 1 --------------------------------------- ----------- ----- n -P A P P A 2 Wn 2 A C out = 1 C g L + C gp + C pd 4 + C pd + C pdg + C m 1 --------------------------------------- ----------- ----- p -P A P P A 2 Wp 2 A C nd C nd C pd C pd Cm1 Cm1 2 2 2 C outI = -------- 4 + -------- 10 + -------- 4 + -------- 10 + --------- 44 + --------- 16 A P A P A P wire capacitance: Vdd Wp pdiff metal p-gate Cwire Cm Cm C wire = ------ [ 5 4 ] + ------ [ 5 + 5 ] A P n-gate poly
Wn GND
ndiff
Transistor Sizing in Inverters
August 19, 2009
page 4 of 11
ECEN
4303
Digital
VLSI
Design
inverter input capacitance: Vdd Wp pdiff metal p-gate Cin
poly
Wn GND
ndiff
Poly over thick oxide: C poly C poly = ----------- ( 4 4 + L 12 + 2 L 2.5 ) A C poly + ----------- [ ( 4 + 4 + 4 + 4 + 4 + 12 ) + 2 ( 2.5 + L + 2.5 ) ] P Poly over thin oxide (gate): C gn Cg C gn = ----- W n L n + 2 -------- W n A P
C gp Cg C gp = ----- W p L p + 2 -------- W p A P
The gate to source and gate to drain overlap capacitance is the same in modern processes. Lets first group the parts of the capacitance together that depend on the channel length L, Ci = ( ) + ( ) L which means that the delay is L2 t df = R sn ------ C i = ( ) L + ( ) L W n L2 t dr = R sp ------ C i = ( ) L + ( ) L Wp
Transistor Sizing in Inverters August 19, 2009 page 5 of 11
n-gate
ECEN
4303
Digital
VLSI
Design
which once again verifies that only minimum channel length should be used in digital designs. We will assume from now on that L = 2 which is the minimum design rule. However, the effective lengths, Ln and Lp can still be different. If the parts of the capacitance that depend on Wp and Wn are grouped together, the total inverter input capacitance is C in = C gn + C gp + C poly C in C in = ------- W n + ------- W p + C inI Wn Wp where C in = C g L + C gn 2 ----------------- Wn A n P C in = ------ Wp C g L + C gp 2 ----------- A p P
C poly C poly 2 C inI = ----------- 50 + ----------- 46 A P Single Stage Inverter The Delay capacitances we have just calculated may be used to estimate the delay of a single inverter driving the capacitive load from another inverter of the same size. Putting in the Wn and Wp dependence of Ci, the td equations become Ci 2 C it df = R sn ------ ------ W n + ------ W p + C I W p W n W n Ci 2 C it dr = R sp ------ ------ W n + ------ W p + C I W p W p W n where Rsn, Rsp are the n,p-FET on channel sheet resistances and Ci ------ = C out + C in -------------- W n Wn Wn Ci ------ = C out + C in -------------- W p Wp Wp C I = C outI + C wire + C inI As Wn increases the fall time decreases but the rise time increases. As Wp increases the rise time decreases but the fall time increases.
Transistor Sizing in Inverters
August 19, 2009
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ECEN
4303
Digital
VLSI
Design
td tdf
tdr Wn td tdr
tdf
Wp
The design criterion that is most frequently used is to minimize the worst case delay. The worst case delay is the largest (slowest) of the two delays. Suppose that we start with a small value of Wn. The fall time delay is reduced by increasing Wn until the fall time and rise time curves cross. Any further increase in Wn will increase the rise time which is now the worst case delay. Similarly for Wp. We can see that the minimum worst case delay is obtained when tdf = tdr. Setting the rise and fall delays equal gives R sn R sp ------- = ------Wn Wp W p R sp ------ = ------- 2 W n R sn The worst case delay is R sn C I R sp C I Ci Ci Ci Ci t d = R sn ------ + R sp ------ + ------------- 2 = R sn ------ + R sp ------ + ------------- 2 W n W p W n W p Wn Wp
td
diminishing returns Wn, Wp
Note that Ci Ci 1. The delay cannot be made smaller than R sn ------ + R sp ------ 2 . W n W p
Transistor Sizing in Inverters
August 19, 2009
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ECEN
4303
Digital
VLSI
Design
2. The last term, RsnCI/Wn, from interconnect can be made negligible by choosing large widths. There is a continuing decrease in delay as the transistor widths, Wn and Wp, are increased, but it takes larger and larger increases in W to get a significant improvement in delay typical of the law of diminishing returns. 3. Delay is minimized only for an infinite value of the transistor widths! Clearly, this is not an acceptable design criterion. The area taken up by the inverter must be taken into account. From the previous layout, the inverter area is approximately A inv = ( 2 + W n + 12 + W p + 2 ) ( 16 ) The reduction in delay must be traded off against the increased area (and power) when the widths are increased. This is a cost-performance trade-off (area ~ cost, 1/delay ~ performance) typically encountered in real world engineering designs. Inverter Pair Delay Replacing the transistors in two series inverters by the equivalent switching circuits, we have the two possibilities shown below, depending on whether the input, V0, is rising or
RonP V0
V1
RonP
V2
RonN
Cout
RonN
Cout
V0
RonP
V1
RonP
V2
RonN
Cout
RonN
Cout
falling. The capacitive load on each inverter is the same since we are assuming that all inverters are the same size. In either case, an edge on V0 causes the transistors in the first inverter to switch which causes a delayed edge on V1. The delayed edge on V1 causes the transistors in the second
Transistor Sizing in Inverters
August 19, 2009
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ECEN
4303
Digital
VLSI
Design
inverter to switch which in turn causes a further delayed edge on V2. The inverter pair delay is the sum of the delays of each individual inverter. If the first inverter output is rising then the second inverter output will be falling and the total delay is t d pair = t dr + t df This is the same delay one would obtain if the first inverter output is falling and the second rising. To analyze the inverter pair delay, it will be convenient to define new variables Z and W as Z Wp Wn W Wp + Wn so that Wn and Wp can be replaced by 1W n = ----------- W Z+1 ZW p = ----------- W Z+1 so that the pair delay becomes Ci R sp Ci Z+1 t d pair = ------- + R sn 2 ------ + Z ------ + C I ----------Z W n W p W
td
diminishing returns W
The delay again decreases with W but cannot be made smaller than Ci Ci R sp + R ------ + ( R + ZR ) ------ 2 . ------sn W - sp sn W - Z n p
Transistor Sizing in Inverters
August 19, 2009
page 9 of 11
ECEN
4303
Digital
VLSI
Design
We will choose W to satisfy the area-delay trade-off and adjust Z to give the minimum delay for any choice of W. The following plot shows the effects of choosing different Z tdpair
Z Zopt From the plot, Zopt is the value of Z that minimizes delay for a fixed W. Zopt can be found from solving
t d =0 Z
which gives after some algebra Z opt = R sp R sn ---------------------------------------------------------------------------------Ci Ci ------ + C W ------ + C W I I W n W p
The value for Zopt is process dependent, but typical values in modern processes are R sp R sn 2 Ci Ci ------ ------ 1 W n W p which gives Z opt pair 2 in modern processes. This applies to general situations when logic gates are driving another single logic gate of about the same size. Recall that the optimum size ratio for minimizing the delay of a single inverter was different. Z opt inv 2 This applies to situations where a single logic gate has a much larger load than any other logic gate, for example a bus line or other node with high capacitive load.
Transistor Sizing in Inverters August 19, 2009 page 10 of 11
ECEN
4303
Digital
VLSI
Design
Note that using the Zoptpair reduces the pair delay from 2 t d inv = t d pair
Z=2
2 = -- + 1 R sn 2 2
Ci Ci ------ + 2 ------ + C 2 + 1 I ---------- W n W p W
Ci 1= 6 R sn 2 ------ + C I --- W n W to t d pair Ci Ci 22+1 = ------ + 1 R sn 2 ------ + 2 ------ + C I --------------2 W n W p W Ci 1= ( 3 + 2 2 ) R sn 2 ------ + C I --- W n W which is a reduction of 5.83/6 or about a 3% improvement. From the previous plot of delay vs. Z, the delay has a very broad minimum so that any choice 1<Z<2 gives similar delay. Designers often use a smaller Z to save area. t d pair Ci Ci 2 1+1 = -- + 1 R sn 2 ------ + 1 ------ + C I ----------1 W n W p W Ci 1= 6 R sn 2 ------ + C I --- W n W Choosing Z = 1 gives the same average delay as Z = 2, but uses significantly less area. The authors choose Z = 2 to make analysis easier because rise time and fall time delays are the same. Most designers choose a smaller Z to get faster and smaller circuits. Therefore, we will not assume equal rise and fall time delays, and we will leave Z as a parameter that the designer can choose to optimize his circuits.
z=
2
z=1
Transistor Sizing in Inverters
August 19, 2009
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