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1.Introduction Systems and Codes 3.Digital Circuits 4.Combinational Logic Design Principles 5.Combinational Logic Design Practices 6.Combinational Design Examples 7.Sequential Logic Design principles 8.Sequential Logic Design practices 9.Sequential Design Examples
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Hi, I'm John . . . .
Introduction
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1.1 About Digital Design
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elcome to the world of digital design. Perhaps youre a computer science student who knows all about computer software and programming, but youre still trying to figure out how all that fancy hardware could possibly work. Or perhaps youre an electrical engineering student who already knows something about analog electronics and circuit design, but you wouldnt know a bit if it bit you. No matter. Starting from a fairly basic level, this book will show you how to design digital circuits and subsystems. Well give you the basic principles that you need to figure things out, and well give you lots of examples. Along with principles, well try to convey the flavor of real-world digital design by discussing current, practical considerations whenever possible. And I, the author, will often refer to myself as we in the hope that youll be drawn in and feel that were walking through the learning process together.
Some people call it logic design. Thats OK, but ultimately the goal of design is to build systems. To that end, well cover a whole lot more in this text than just logic equations and theorems. This book claims to be about principles and practices. Most of the principles that we present will continue to be important years from now; some
Copyright 1999 by John F. Wakerly
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Chapter 1
Introduction
IMPORTANT THEMES IN DIGITAL DESIGN
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of doing things right. design. design. as part of the cost. minute modifications. comes along. the outside world, and provide reliable synchronizers.
may be applied in ways that have not even been discovered yet. As for practices, they may be a little different from whats presented here by the time you start working in the field, and they will certainly continue to change throughout your career. So you should treat the practices material in this book as a way to reinforce principles, and as a way to learn design methods by example. One of the book's goals is to present enough about basic principles for you to know what's happening when you use software tools to turn the crank for you. The same basic principles can help you get to the root of problems when the tools happen to get in your way. Listed in the box on this page, there are several key points that you should learn through your studies with this text. Most of these items probably make no sense to you right now, but you should come back and review them later. Digital design is engineering, and engineering means problem solving. My experience is that only 5%10% of digital design is the fun stuffthe creative part of design, the flash of insight, the invention of a new approach. Much of the rest is just turning the crank. To be sure, turning the crank is much easier now than it was 20 or even 10 years ago, but you still cant spend 100% or even 50% of your time on the fun stuff.
Good tools do not guarantee good design, but they help a lot by taking the pain out Digital circuits have analog characteristics. Know when to worry and when not to worry about the analog aspects of digital Always document your designs to make them understandable by yourself and others. Associate active levels with signal names and practice bubble-to-bubble logic Understand and use standard functional building blocks. Design for minimum cost at the system level, including your own engineering effort State-machine design is like programming; approach it that way. Use programmable logic to simplify designs, reduce cost, and accommodate last Avoid asynchronous design. Practice synchronous design until a better methodology Pinpoint the unavoidable asynchronous interfaces between different subsystems and Catching a glitch in time saves nine.
Copyright 1999 by John F. Wakerly
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Section 1.2
Analog versus Digital
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Besides the fun stuff and turning the crank, there are many other areas in which a successful digital designer must be competent, including the following:
Debugging. Its next to impossible to be a good designer without being a good troubleshooter. Successful debugging takes planning, a systematic approach, patience, and logic: if you cant discover where a problem is, find out where it is not! Business requirements and practices. A digital designers work is affected by a lot of non-engineering factors, including documentation standards, component availability, feature definitions, target specifications, task scheduling, office politics, and going to lunch with vendors. Risk-taking. When you begin a design project you must carefully balance risks against potential rewards and consequences, in areas ranging from new-component selection (will it be available when Im ready to build the first prototype?) to schedule commitments (will I still have a job if Im late?). Communication. Eventually, youll hand off your successful designs to other engineers, other departments, and customers. Without good communication skills, youll never complete this step successfully. Keep in mind that communication includes not just transmitting but also receiving; learn to be a good listener!
In the rest of this chapter, and throughout the text, Ill continue to state some opinions about whats important and what is not. I think Im entitled to do so as a moderately successful practitioner of digital design. Of course, you are always welcome to share your own opinions and experience (send email to john@wakerly.com).
1.2 Analog versus Digital
Analog devices and systems process time-varying signals that can take on any value across a continuous range of voltage, current, or other metric. So do digital circuits and systems; the difference is that we can pretend that they dont! A digital signal is modeled as taking on, at any time, only one of two discrete values, which we call 0 and 1 (or LOW and HIGH, FALSE and TRUE, negated and asserted, Sam and Fred, or whatever). Digital computers have been around since the 1940s, and have been in widespread commercial use since the 1960s. Yet only in the past 10 to 20 years has the digital revolution spread to many other aspects of life. Examples of once-analog systems that have now gone digital include the following: Still pictures. The majority of cameras still use silver-halide film to record images. However, the increasing density of digital memory chips has allowed the development of digital cameras which record a picture as a
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analog digital 0 1
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640480 or larger array of pixels, where each pixel stores the intensities of its red, green and blue color components as 8 bits each. This large amount of data, over seven million bits in this example, may be processed and compressed into a format called JPEG with as little as 5% of the original storage size, depending on the amount of picture detail. So, digital cameras rely on both digital storage and digital processing.
Video recordings. A digital versatile disc (DVD) stores video in a highly compressed digital format called MPEG-2. This standard encodes a small fraction of the individual video frames in a compressed format similar to JPEG, and encodes each other frame as the difference between it and the previous one. The capacity of a single-layer, single-sided DVD is about 35 billion bits, sufficient for about 2 hours of high-quality video, and a twolayer, double-sided disc has four times that capacity. Audio recordings. Once made exclusively by impressing analog waveforms onto vinyl or magnetic tape, audio recordings now commonly use digital compact discs (CDs). A CD stores music as a sequence of 16-bit numbers corresponding to samples of the original analog waveform, one sample per stereo channel every 22.7 microseconds. A full-length CD recording (73 minutes) contains over six billion bits of information. Automobile carburetors. Once controlled strictly by mechanical linkages (including clever analog mechanical devices that sensed temperature, pressure, etc.), automobile engines are now controlled by embedded microprocessors. Various electronic and electromechanical sensors convert engine conditions into numbers that the microprocessor can examine to determine how to control the flow of fuel and oxygen to the engine. The microprocessors output is a time-varying sequence of numbers that operate electromechanical actuators which, in turn, control the engine. The telephone system. It started out a hundred years ago with analog microphones and receivers connected to the ends of a pair of copper wires (or was it string?). Even today, most homes still use analog telephones, which transmit analog signals to the phone companys central office (CO). However, in the majority of COs, these analog signals are converted into a digital format before they are routed to their destinations, be they in the same CO or across the world. For many years the private branch exchanges (PBXs) used by businesses have carried the digital format all the way to the desktop. Now many businesses, COs, and traditional telephony service providers are converting to integrated systems that combine digital voice with data traffic over a single IP (Internet Protocol) network. Traffic lights. Stop lights used to be controlled by electromechanical timers that would give the green light to each direction for a predetermined amount of time. Later, relays were used in controllers that could activate
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Movie effects. Special effects used to be made exclusively with miniature clay models, stop action, trick photography, and numerous overlays of film on a frame-by-frame basis. Today, spaceships, bugs, other-worldly scenes, and even babies from hell (in Pixars animated feature Tin Toy) are synthesized entirely using digital computers. Might the stunt man or woman someday no longer be needed, either? The electronics revolution has been going on for quite some time now, and the solid-state revolution began with analog devices and applications like transistors and transistor radios. So why has there now been a digital revolution? There are in fact many reasons to favor digital circuits over analog ones: Reproducibility of results. Given the same set of inputs (in both value and time sequence), a properly designed digital circuit always produces exactly the same results. The outputs of an analog circuit vary with temperature, power-supply voltage, component aging, and other factors.
Ease of design. Digital design, often called logic design, is logical. No special math skills are needed, and the behavior of small logic circuits can be visualized mentally without any special insights about the operation of capacitors, transistors, or other devices that require calculus to model. Flexibility and functionality. Once a problem has been reduced to digital form, it can be solved using a set of logical steps in space and time. For example, you can design a digital circuit that scrambles your recorded voice so that it is absolutely indecipherable by anyone who does not have your key (password), but can be heard virtually undistorted by anyone who does. Try doing that with an analog circuit. Programmability. Youre probably already quite familiar with digital computers and the ease with which you can design, write, and debug programs for them. Well, guess what? Much of digital design is carried out today by writing programs, too, in hardware description languages (HDLs). These languages allow both structure and function of a digital circuit to be specified or modeled. Besides a compiler, a typical HDL also comes with simulation and synthesis programs. These software tools are used to test the hardware models behavior before any real hardware is built, and then synthesize the model into a circuit in a particular component technology.
Speed. Todays digital devices are very fast. Individual transistors in the fastest integrated circuits can switch in less than 10 picoseconds, and a complete, complex device built from these transistors can examine its
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the lights according to the pattern of traffic detected by sensors embedded in the pavement. Todays controllers use microprocessors, and can control the lights in ways that maximize vehicle throughput or, in some California cities, frustrate drivers in all kinds of creative ways.
hardware model
hardware description language (HDL)
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Introduction
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SHORT TIMES
A microsecond (sec) is 106 second. A nanosecond (ns) is just 109 second, and a picosecond (ps) is 1012 second. In a vacuum, light travels about a foot in a nanosecond, and an inch in 85 picoseconds. With individual transistors in the fastest integrated circuits now switching in less than 10 picoseconds, the speed-of-light delay between these transistors across a half-inch-square silicon chip has become a limiting factor in circuit design.
inputs and produce an output in less than 2 nanoseconds. This means that such a device can produce 500 million or more results per second. Economy. Digital circuits can provide a lot of functionality in a small space. Circuits that are used repetitively can be integrated into a single chip and mass-produced at very low cost, making possible throw-away items like calculators, digital watches, and singing birthday cards. (You may ask, Is this such a good thing? Never mind!) Steadily advancing technology. When you design a digital system, you almost always know that there will be a faster, cheaper, or otherwise better technology for it in a few years. Clever designers can accommodate these expected advances during the initial design of a system, to forestall system obsolescence and to add value for customers. For example, desktop computers often have expansion sockets to accommodate faster processors or larger memories than are available at the time of the computers introduction.
So, thats enough of a sales pitch on digital design. The rest of this chapter will give you a bit more technical background to prepare you for the rest of the book.
1.3 Digital Devices
The most basic digital devices are called gates and no, they were not named after the founder of a large software company. Gates originally got their name from their function of allowing or retarding (gating) the flow of digital information. In general, a gate has one or more inputs and produces an output that is a function of the current input value(s). While the inputs and outputs may be analog conditions such as voltage, current, even hydraulic pressure, they are modeled as taking on just two discrete values, 0 and 1. Figure 1-1 shows symbols for the three most important kinds of gates. A 2-input AND gate, shown in (a), produces a 1 output if both of its inputs are 1; otherwise it produces a 0 output. The figure shows the same gate four times, with the four possible combinations of inputs that may be applied to it and the result-
Copyright 1999 by John F. Wakerly
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Electronic Aspects of Digital Design
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(a)
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Fig u re 1-1 Digital devices: (a) AND gate; (b) OR gate; (c) NOT gate or inverter.
ing outputs. A gate is called a combinational circuit because its output depends only on the current input combination. A 2-input OR gate, shown in (b), produces a 1 output if one or both of its inputs are 1; it produces a 0 output only if both inputs are 0. Once again, there are four possible input combinations, resulting in the outputs shown in the figure. A NOT gate, more commonly called an inverter, produces an output value that is the opposite of the input value, as shown in (c). We called these three gates the most important for good reason. Any digital function can be realized using just these three kinds of gates. In Chapter 3 well show how gates are realized using transistor circuits. You should know, however, that gates have been built or proposed using other technologies, such as relays, vacuum tubes, hydraulics, and molecular structures. A flip-flop is a device that stores either a 0 or 1. The state of a flip-flop is the value that it currently stores. The stored value can be changed only at certain times determined by a clock input, and the new value may further depend on the flip-flops current state and its control inputs. A flip-flop can be built from a collection of gates hooked up in a clever way, as well show in Section 7.2. A digital circuit that contains flip-flops is called a sequential circuit because its output at any time depends not only on its current input, but also on the past sequence of inputs that have been applied to it. In other words, a sequential circuit has memory of past events.
1.4 Electronic Aspects of Digital Design
Digital circuits are not exactly a binary version of alphabet soupwith all due respect to Figure 1-1, they dont have little 0s and 1s floating around in them. As well see in Chapter 3, digital circuits deal with analog voltages and currents, and are built with analog components. The digital abstraction allows analog behavior to be ignored in most cases, so circuits can be modeled as if they really did process 0s and 1s.
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Chapter 1
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noise margin
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Fig u re 1-2 Logic values and noise margins.
Outputs logic 1 Noise Margin Inputs Voltage logic 1 invalid logic 0 logic 0
One important aspect of the digital abstraction is to associate a range of analog values with each logic value (0 or 1). As shown in Figure 1-2, a typical gate is not guaranteed to have a precise voltage level for a logic 0 output. Rather, it may produce a voltage somewhere in a range that is a subset of the range guaranteed to be recognized as a 0 by other gate inputs. The difference between the range boundaries is called noise marginin a real circuit, a gates output can be corrupted by this much noise and still be correctly interpreted at the inputs of other gates. Behavior for logic 1 outputs is similar. Note in the figure that there is an invalid region between the input ranges for logic 0 and logic 1. Although any given digital device operating at a particular voltage and temperature will have a fairly well defined boundary (or threshold) between the two ranges, different devices may have different boundaries. Still, all properly operating devices have their boundary somewhere in the invalid range. Therefore, any signal that is within the defined ranges for 0 and 1 will be interpreted identically by different devices. This characteristic is essential for reproducibility of results. It is the job of an electronic circuit designer to ensure that logic gates produce and recognize logic signals that are within the appropriate ranges. This is an analog circuit-design problem; we touch upon some aspects of this in Chapter 3. It is not possible to design a circuit that has the desired behavior under every possible condition of power-supply voltage, temperature, loading, and other factors. Instead, the electronic circuit designer or device manufacturer provides specifications that define the conditions under which correct behavior is guaranteed. As a digital designer, then, you need not delve into the detailed analog behavior of a digital device to ensure its correct operation. Rather, you need only examine enough about the devices operating environment to determine that it is operating within its published specifications. Granted, some analog knowledge is needed to perform this examination, but not nearly what youd need to design a digital device starting from scratch. In Chapter 3, well give you just what you need.
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Section 1.5
Software Aspects of Digital Design
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1.5 Software Aspects of Digital Design
Digital design need not involve any software tools. For example, Figure 1-3 shows the primary tool of the old school of digital designa plastic template for drawing logic symbols in schematic diagrams by hand (the designers name was engraved into the plastic with a soldering iron). Today, however, software tools are an essential part of digital design. Indeed, the availability and practicality of hardware description languages (HDLs) and accompanying circuit simulation and synthesis tools have changed the entire landscape of digital design over the past several years. Well make extensive use of HDLs throughout this book. In computer-aided design (CAD) various software tools improve the designers productivity and help to improve the correctness and quality of designs. In a competitive world, the use of software tools is mandatory to obtain high-quality results on aggressive schedules. Important examples of software tools for digital design are listed below:
Schematic entry. This is the digital designers equivalent of a word processor. It allows schematic diagrams to be drawn on-line, instead of with paper and pencil. The more advanced schematic-entry programs also check for common, easy-to-spot errors, such as shorted outputs, signals that dont go anywhere, and so on. Such programs are discussed in greater detail in Section 12.1. HDLs. Hardware description languages, originally developed for circuit modeling, are now being used more and more for hardware design. They can be used to design anything from individual function modules to large, multi-chip digital systems. Well introduce two HDLs, ABEL and VHDL, at the end of Chapter 4, and well provide examples in both languages in the chapters that follow. HDL compilers, simulators, and synthesis tools. A typical HDL software package contains several components. In a typical environment, the designer writes a text-based program, and the HDL compiler analyzes
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Quarter-size logic symbols, copyright 1976 by Micro Systems Engineering
Fi gure 1- 3 A logic-design template.
computer-aided design (CAD)
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the program for syntax errors. If it compiles correctly, the designer has the option of handing it over to a synthesis tool that creates a corresponding circuit design targeted to a particular hardware technology. Most often, before synthesis the designer will use the compilers results as input to a simulator to verify the behavior of the design. Simulators. The design cycle for a customized, single-chip digital integrated circuit is long and expensive. Once the first chip is built, its very difficult, often impossible, to debug it by probing internal connections (they are really tiny), or to change the gates and interconnections. Usually, changes must be made in the original design database and a new chip must be manufactured to incorporate the required changes. Since this process can take months to complete, chip designers are highly motivated to get it right (or almost right) on the first try. Simulators help designers predict the electrical and functional behavior of a chip without actually building it, allowing most if not all bugs to be found before the chip is fabricated. Simulators are also used in the design of programmable logic devices, introduced later, and in the overall design of systems that incorporate many individual components. They are somewhat less critical in this case because its easier for the designer to make changes in components and interconnections on a printed-circuit board. However, even a little bit of simulation can save time by catching simple but stupid mistakes. Test benches. Digital designers have learned how to formalize circuit simulation and testing into software environments called test benches. The idea is to build a set of programs around a design to automatically exercise its functions and check both its functional and its timing behavior. This is especially useful when small design changes are madethe test bench can be run to ensure that bug fixes or improvements in one area do not break something else. Test-bench programs may be written in the same HDL as the design itself, in C or C++, or in combination of languages including scripting languages like PERL. Timing analyzers and verifiers. The time dimension is very important in digital design. All digital circuits take time to produce a new output value in response to an input change, and much of a designers effort is spent ensuring that such output changes occur quickly enough (or, in some cases, not too quickly). Specialized programs can automate the tedious task of drawing timing diagrams and specifying and verifying the timing relationships between different signals in a complex system. Word processors. Lets not forget the lowly text editor and word processor. These tools are obviously useful for creating the source code for HDLbased designs, but they have an important use in every designto create documentation!
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Software Aspects of Digital Design
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PROGRAMMABLE LOGIC DEVICES VERSUS SIMULATION
In addition to using the tools above, designers may sometimes write specialized programs in high-level languages like C or C++, or scripts in languages like PERL, to solve particular design problems. For example, Section 11.1 gives a few examples of C programs that generate the truth tables for complex combinational logic functions. Although CAD tools are important, they dont make or break a digital designer. To take an analogy from another field, you couldnt consider yourself to be a great writer just because youre a fast typist or very handy with a word processor. During your study of digital design, be sure to learn and use all the
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Later in this book youll learn how programmable logic devices (PLDs) and fieldprogrammable gate arrays (FPGAs) allow you to design a circuit or subsystem by writing a sort of program. PLDs and FPGAs are now available with up to millions of gates, and the capabilities of these technologies are ever increasing. If a PLD- or FPGA-based design doesnt work the first time, you can often fix it by changing the program and physically reprogramming the device, without changing any components or interconnections at the system level. The ease of prototyping and modifying PLD- and FPGA-based systems can eliminate the need for simulation in board-level design; simulation is required only for chip-level designs. The most widely held view in industry trends says that as chip technology advances, more and more design will be done at the chip level, rather than the board level. Therefore, the ability to perform complete and accurate simulation will become increasingly important to the typical digital designer. However, another view is possible. If we extrapolate trends in PLD and FPGA capabilities, in the next decade we will witness the emergence of devices that include not only gates and flip-flops as building blocks, but also higher-level functions such as processors, memories, and input/output controllers. At this point, most digital designers will use complex on-chip components and interconnections whose basic functions have already been tested by the device manufacturer. In this future view, it is still possible to misapply high-level programmable functions, but it is also possible to fix mistakes simply by changing a program; detailed simulation of a design before simply trying it out could be a waste of time. Another, compatible view is that the PLD or FPGA is merely a full-speed simulator for the program, and this full-speed simulator is what gets shipped in the product! Does this extreme view have any validity? To guess the answer, ask yourself the following question. How many software programmers do you know who debug a new program by simulating its operation rather than just trying it out? In any case, modern digital systems are much too complex for a designer to have any chance of testing every possible input condition, with or without simulation. As in software, correct operation of digital systems is best accomplished through practices that ensure that the systems are correct by design. It is a goal of this text to encourage such practices.
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Chapter 1
Introduction
integrated circuit (IC)
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1.6 Integrated Circuits
A DICEY DECISION There is, indeed, much dispute over this term. We actually stopped using the term dice in Microprocessor Report more than four years ago. I actually prefer the plural die, but perhaps it is best to avoid using the plural whenever possible. So there you have it, even the experts dont agree with the dictionary! Rather than cop out, I boldly chose to use dice anyway, by rolling the dice. Copyright 1999 by John F. Wakerly
tools that are available to you, such as schematic-entry programs, simulators, and HDL compilers. But remember that learning to use tools is no guarantee that youll be able to produce good results. Please pay attention to what youre producing with them!
A collection of one or more gates fabricated on a single silicon chip is called an integrated circuit (IC). Large ICs with tens of millions of transistors may be half an inch or more on a side, while small ICs may be less than one-tenth of an inch on a side. Regardless of its size, an IC is initially part of a much larger, circular wafer, up to ten inches in diameter, containing dozens to hundreds of replicas of the same IC. All of the IC chips on the wafer are fabricated at the same time, like pizzas that are eventually sold by the slice, except in this case, each piece (IC chip) is called a die. After the wafer is fabricated, the dice are tested in place on the wafer and defective ones are marked. Then the wafer is sliced up to produce the individual dice, and the marked ones are discarded. (Compare with the pizzamaker who sells all the pieces, even the ones without enough pepperoni!) Each unmarked die is mounted in a package, its pads are connected to the package pins, and the packaged IC is subjected to a final test and is shipped to a customer. Some people use the term IC to refer to a silicon die. Some use chip to refer to the same thing. Still others use IC or chip to refer to the combination of a silicon die and its package. Digital designers tend to use the two terms interchangeably, and they really dont care what theyre talking about. They dont require a precise definition, since theyre only looking at the functional and electrical behavior of these things. In the balance of this text, well use the term IC to refer to a packaged die.
A reader of the second edition wrote to me to collect a $5 reward for pointing out my glaring misuse of dice as the plural of die. According to the dictionary, she said, the plural form of die is dice only when describing those little cubes with dots on each side; otherwise its dies, and she produced the references to prove it. Being stubborn, I asked my friends at the Microprocessor Report about this issue. According to the editor,
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In the early days of integrated circuits, ICs were classified by sizesmall, medium, or largeaccording to how many gates they contained. The simplest type of commercially available ICs are still called small-scale integration (SSI), and contain the equivalent of 1 to 20 gates. SSI ICs typically contain a handful of gates or flip-flops, the basic building blocks of digital design. The SSI ICs that youre likely to encounter in an educational lab come in a 14-pin dual in-line-pin (DIP) package. As shown in Figure 1-4(a), the spacing between pins in a column is 0.1 inch and the spacing between columns is 0.3 inch. Larger DIP packages accommodate functions with more pins, as shown in (b) and (c). A pin diagram shows the assignment of device signals to package pins, or pinout. Figure 1-5 shows the pin diagrams for a few common SSI ICs. Such diagrams are used only for mechanical reference, when a designer needs to determine the pin numbers for a particular IC. In the schematic diagram for a
Fig u re 1-5 Pin diagrams for a few 7400-series SSI ICs.
7400 7402 7404
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medium-scale integration (MSI)
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TINY-SCALE INTEGRATION
In the coming years, perhaps the most popular remaining use of SSI and MSI, especially in DIP packages, will be in educational labs. These devices will afford students the opportunity to get their hands dirty by breadboarding and wiring up simple circuits in the same way that their professors did years ago. However, much to my surprise and delight, a segment of the IC industry has actually gone downscale from SSI in the past few years. The idea has been to sell individual logic gates in very small packages. These devices handle simple functions that are sometimes needed to match larger-scale components to a particular design, or in some cases they are used to work around bugs in the larger-scale components or their interfaces. An example of such an IC is Motorolas 74VHC1G00. This chip is a single 2-input NAND gate housed in a 5-pin package (power, ground, two inputs, and one output). The entire package, including pins, measures only 0.08 inches on a side, and is only 0.04 inches high! Now thats what I would call tiny-scale integration!
digital circuit, pin diagrams are not used. Instead, the various gates are grouped functionally, as well show in Section 5.1. Although SSI ICs are still sometimes used as glue to tie together largerscale elements in complex systems, they have been largely supplanted by programmable logic devices, which well study in Sections 5.3 and 8.3. The next larger commercially available ICs are called medium-scale integration (MSI), and contain the equivalent of about 20 to 200 gates. An MSI IC typically contains a functional building block, such as a decoder, register, or counter. In Chapters 5 and 8, well place a strong emphasis on these building blocks. Even though the use of discrete MSI ICs is declining, the equivalent building blocks are used extensively in the design of larger ICs. Large-scale integration (LSI) ICs are bigger still, containing the equivalent of 200 to 200,000 gates or more. LSI parts include small memories, microprocessors, programmable logic devices, and customized devices.
STANDARD LOGIC FUNCTIONS
Many standard high-level functions appear over and over as building blocks in digital design. Historically, these functions were first integrated in MSI circuits. Subsequently, they have appeared as components in the macro libraries for ASIC design, as standard cells in VLSI design, as canned functions in PLD programming languages, and as library functions in hardware-description languages such as VHDL. Standard logic functions are introduced in Chapters 5 and 8 as 74-series MSI parts, as well as in HDL form. The discussion and examples in these chapters provide a basis for understanding and using these functions in any form.
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Section 1.7
Programmable Logic Devices
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The dividing line between LSI and very large-scale integration (VLSI) is fuzzy, and tends to be stated in terms of transistor count rather than gate count. Any IC with over 1,000,000 transistors is definitely VLSI, and that includes most microprocessors and memories nowadays, as well as larger programmable logic devices and customized devices. In 1999, the VLSI ICs as large as 50 million transistors were being designed.
1.7 Programmable Logic Devices
There are a wide variety of ICs that can have their logic function programmed into them after they are manufactured. Most of these devices use technology that also allows the function to be reprogrammed, which means that if you find a bug in your design, you may be able to fix it without physically replacing or rewiring the device. In this book, well frequently refer to the design opportunities and methods for such devices. Historically, programmable logic arrays (PLAs) were the first programmable logic devices. PLAs contained a two-level structure of AND and OR gates with user-programmable connections. Using this structure, a designer could accommodate any logic function up to a certain level of complexity using the well-known theory of logic synthesis and minimization that well present in Chapter 4. PLA structure was enhanced and PLA costs were reduced with the introduction of programmable array logic (PAL) devices. Today, such devices are generically called programmable logic devices (PLDs), and are the MSI of the programmable logic industry. Well have a lot to say about PLD architecture and technology in Sections 5.3 and 8.3. The ever-increasing capacity of integrated circuits created an opportunity for IC manufacturers to design larger PLDs for larger digital-design applications. However, for technical reasons that well discuss in \secref{CPLDs}, the basic two-level AND-OR structure of PLDs could not be scaled to larger sizes. Instead, IC manufacturers devised complex PLD (CPLD) architectures to achieve the required scale. A typical CPLD is merely a collection of multiple PLDs and an interconnection structure, all on the same chip. In addition to the individual PLDs, the on-chip interconnection structure is also programmable, providing a rich variety of design possibilities. CPLDs can be scaled to larger sizes by increasing the number of individual PLDs and the richness of the interconnection structure on the CPLD chip. At about the same time that CPLDs were being invented, other IC manufacturers took a different approach to scaling the size of programmable logic chips. Compared to a CPLD, a field-programmable gate arrays (FPGA) contains a much larger number of smaller individual logic blocks, and provides a large, distributed interconnection structure that dominates the entire chip. Figure 1-6 illustrates the difference between the two chip-design approaches.
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very large-scale integration (VLSI) programmable logic array (PLA) programmable array logic (PAL) device programmable logic device (PLD) field-programmable gate array (FPGA)
complex PLD (CPLD)
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Chapter 1
Introduction
semicustom IC application-specific IC (ASIC) nonrecurring engineering (NRE) cost
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PLD PLD PLD PLD Programmable Interconnect PLD PLD PLD PLD (a) (b) = logic block
F igu r e 1 - 6 Large programmable-logic-device scaling approaches: (a) CPLD; (b) FPGA.
Proponents of one approach or the other used to get into religious arguments over which way was better, but the largest manufacturer of large programmable logic devices, Xilinx Corporation, acknowledges that there is a place for both approaches and manufactures both types of devices. Whats more important than chip architecture is that both approaches support a style of design in which products can be moved from design concept to prototype and production in a very period of time short time. Also important in achieving short time-to-market for all kinds of PLDbased products is the use of HDLs in their design. Languages like ABEL and VHDL, and their accompanying software tools, allow a design to be compiled, synthesized, and downloaded into a PLD, CPLD, or FPGA literally in minutes. The power of highly structured, hierarchical languages like VHDL is especially important in helping designers utilize the hundreds of thousands or millions of gates that are provided in the largest CPLDs and FPGAs.
1.8 Application-Specific ICs
Perhaps the most interesting developments in IC technology for the average digital designer are not the ever-increasing chip sizes, but the ever-increasing opportunities to design your own chip. Chips designed for a particular, limited product or application are called semicustom ICs or application-specific ICs (ASICs). ASICs generally reduce the total component and manufacturing cost of a product by reducing chip count, physical size, and power consumption, and they often provide higher performance. The nonrecurring engineering (NRE) cost for designing an ASIC can exceed the cost of a discrete design by $5,000 to $250,000 or more. NRE charges are paid to the IC manufacturer and others who are responsible for designing the
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Application-Specific ICs
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internal structure of the chip, creating tooling such as the metal masks for manufacturing the chips, developing tests for the manufactured chips, and actually making the first few sample chips. The NRE cost for a typical, medium-complexity ASIC with about 100,000 gates is $30$50,000. An ASIC design normally makes sense only when the NRE cost can be offset by the per-unit savings over the expected sales volume of the product. The NRE cost to design a custom LSI chipa chip whose functions, internal architecture, and detailed transistor-level design is tailored for a specific customeris very high, $250,000 or more. Thus, full custom LSI design is done only for chips that have general commercial application or that will enjoy very high sales volume in a specific application (e.g., a digital watch chip, a network interface, or a bus-interface circuit for a PC). To reduce NRE charges, IC manufacturers have developed libraries of standard cells including commonly used MSI functions such as decoders, registers, and counters, and commonly used LSI functions such as memories, programmable logic arrays, and microprocessors. In a standard-cell design, the logic designer interconnects functions in much the same way as in a multichip MSI/LSI design. Custom cells are created (at added cost, of course) only if absolutely necessary. All of the cells are then laid out on the chip, optimizing the layout to reduce propagation delays and minimize the size of the chip. Minimizing the chip size reduces the per-unit cost of the chip, since it increases the number of chips that can be fabricated on a single wafer. The NRE cost for a standard-cell design is typically on the order of $150,000. Well, $150,000 is still a lot of money for most folks, so IC manufacturers have gone one step further to bring ASIC design capability to the masses. A gate array is an IC whose internal structure is an array of gates whose interconnections are initially unspecified. The logic designer specifies the gate types and interconnections. Even though the chip design is ultimately specified at this very low level, the designer typically works with macrocells, the same high-level functions used in multichip MSI/LSI and standard-cell designs; software expands the high-level design into a low-level one. The main difference between standard-cell and gate-array design is that the macrocells and the chip layout of a gate array are not as highly optimized as those in a standard-cell design, so the chip may be 25% or more larger, and therefore may cost more. Also, there is no opportunity to create custom cells in the gate-array approach. On the other hand, a gate-array design can be completed faster and at lower NRE cost, ranging from about $5000 (what youre told initially) to $75,000 (what you find youve spent when youre all done). The basic digital design methods that youll study throughout this book apply very well to the functional design of ASICs. However, there are additional opportunities, constraints, and steps in ASIC design, which usually depend on the particular ASIC vendor and design environment.
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Chapter 1
Introduction
printed-circuit board (PCB)
printed-wiring board (PWB) PCB traces mil fine-line
surface-mount technology (SMT)
multichip module (MCM)
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1.9 Printed-Circuit Boards 1.10 Digital-Design Levels
Copyright 1999 by John F. Wakerly
An IC is normally mounted on a printed-circuit board (PCB) [or printed-wiring board (PWB)] that connects it to other ICs in a system. The multilayer PCBs used in typical digital systems have copper wiring etched on multiple, thin layers of fiberglass that are laminated into a single board about 1/16 inch thick. Individual wire connections, or PCB traces are usually quite narrow, 10 to 25 mils in typical PCBs. (A mil is one-thousandth of an inch.) In fine-line PCB technology, the traces are extremely narrow, as little as 4 mils wide with 4-mil spacing between adjacent traces. Thus, up to 125 connections may be routed in a one-inch-wide band on a single layer of the PCB. If higher connection density is needed, then more layers are used. Most of the components in modern PCBs use surface-mount technology (SMT). Instead of having the long pins of DIP packages that poke through the board and are soldered to the underside, the leads of SMT IC packages are bent to make flat contact with the top surface of the PCB. Before such components are mounted on the PCB, a special solder paste is applied to contact pads on the PCB using a stencil whose hole pattern matches the contact pads to be soldered. Then the SMT components are placed (by hand or by machine) on the pads, where they are held in place by the solder paste (or in some cases, by glue). Finally, the entire assembly is passed through an oven to melt the solder paste, which then solidifies when cooled. Surface-mount component technology, coupled with fine-line PCB technology, allows extremely dense packing of integrated circuits and other components on a PCB. This dense packing does more than save space. For very high-speed circuits, dense packing goes a long way toward minimizing adverse analog phenomena, including transmission-line effects and speed-of-light limitations. To satisfy the most stringent requirements for speed and density, multichip modules (MCMs) have been developed. In this technology, IC dice are not mounted in individual plastic or ceramic packages. Instead, the IC dice for a high-speed subsystem (say, a processor and its cache memory) are bonded directly to a substrate that contains the required interconnections on multiple layers. The MCM is hermetically sealed and has its own external pins for power, ground, and just those signals that are required by the system that contains it.
Digital design can be carried out at several different levels of representation and abstraction. Although you may learn and practice design at a particular level, from time to time youll need to go up or down a level or two to get the job done. Also, the industry itself and most designers have been steadily moving to higher levels of abstraction as circuit density and functionality have increased.
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Digital-Design Levels
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The lowest level of digital design is device physics and IC manufacturing processes. This is the level that is primarily responsible for the breathtaking advances in IC speed and density that have occurred over the past decades. The effects of these advances are summarized in Moores Law, first stated by Intel founder Gordon Moore in 1965: that the number of transistors per square inch in an IC doubles every year. In recent years, the rate of advance has slowed down to doubling about every 18 months, but it is important to note that with each doubling of density has also come a doubling of speed. This book does not reach down to the level of device physics and IC processes, but you need to recognize the importance of that level. Being aware of likely technology advances and other changes is important in system and product planning. For example, decreases in chip geometries have recently forced a move to lower logic-power-supply voltages, causing major changes in the way designers plan and specify modular systems and upgrades. In this book, we jump into digital design at the transistor level and go all the way up to the level of logic design using HDLs. We stop short of the next level, which includes computer design and overall system design. The center of our discussion is at the level of functional building blocks. To get a preview of the levels of design that well cover, consider a simple design example. Suppose you are to build a multiplexer with two data input bits, A and B, a control input bit S, and an output bit Z. Depending on the value of S, 0 or 1, the circuit is to transfer the value of either A or B to the output Z. This idea is illustrated in the switch model of Figure 1-7. Let us consider the design of this function at several different levels. Although logic design is usually carried out at higher level, for some functions it is advantageous to optimize them by designing at the transistor level. The multiplexer is such a function. Figure 1-8 shows how the multiplexer can be designed in CMOS technology using specialized transistor circuit structures
VCC
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Moores Law
A B S
Z
F igu re 1 - 7 Switch model for multiplexer function.
Fig u re 1-8 Multiplexer design using CMOS transmission gates.
A
Z
B S
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Chapter 1
Introduction
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T ab l e 1 - 1 Truth table for the multiplexer function.
S A B Z
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 1 0 1 0 1
called transmission gates, discussed in Section 3.7.1. Using this approach, the multiplexer can be built with just six transistors. Any of the other approaches that we describe require at least 14 transistors. In the traditional study of logic design, we would use a truth table to describe the multiplexers logic function. A truth table list all possible combinations of input values and the corresponding output values for the function. Since the multiplexer has three inputs, it has 23 or 8 possible input combinations, as shown in the truth table in Table 1-1. Once we have a truth table, traditional logic design methods, described in Section 4.3, use Boolean algebra and well understood minimization algorithms to derive an optimal two-level AND-OR equation from the truth table. For the multiplexer truth table, we would derive the following equation:
Z = S A + S B
This equation is read Z equals not S and A or S and B. Going one step further, we can convert the equation into a corresponding set of logic gates that perform the specified logic function, as shown in Figure 1-9. This circuit requires 14 transistors if we use standard CMOS technology for the four gates shown. A multiplexer is a very commonly used function, and most digital logic technologies provide predefined multiplexer building blocks. For example, the 74x157 is an MSI chip that performs multiplexing on two 4-bit inputs simultaneously. Figure 1-10 is a logic diagram that shows how we can hook up just one bit of this 4-bit building block to solve the problem at hand. The numbers in color are pin numbers of a 16-pin DIP package containing the device.
Figure 1-9 Gate-level logic diagram for multiplexer function.
A ASN
SN
S
Z
SB
B
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Section 1.10
74x157
Digital-Design Levels
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We can also realize the multiplexer function as part of a programmable logic device. Languages like ABEL allow us to specify outputs using Boolean equations similar to the one on the previous page, but its usually more convenient to use higher-level language elements. For example, Table 1-2 is an ABEL program for the multiplexer function. The first three lines define the name of the program module and specify the type of PLD in which the function will be realized. The next two lines specify the device pin numbers for inputs and output. The WHEN statement specifies the actual logic function in a way thats very easy to understand, even though we havent covered ABEL yet. An even higher level language, VHDL, can be used to specify the multiplexer function in a way that is very flexible and hierarchical. Table 1-3 is an example VHDL program for the multiplexer. The first two lines specify a standard library and set of definitions to use in the design. The next four lines specify only the inputs and outputs of the function, and purposely hide any details about the way the function is realized internally. The architecture section of the program specifies the functions behavior. VHDL syntax takes a little getting used to, but the single when statement says basically the same thing that the ABEL version did. A VHDL synthesis tool can start with this
module chap1mux title 'Two-input multiplexer example' CHAP1MUX device 'P16V8' A, B, S Z pin 1, 2, 3; pin 13 istype 'com';
equations
WHEN S == 0 THEN Z = A; end chap1mux
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G
S A B
1
2 3 5 6
11 10 14 13
S 1A 1B 2A 2B 3A 3B 4A 4B
1Y 2Y 3Y 4Y
4
Z
7
9
12
Fi gure 1 - 10 Logic diagram for a multiplexer using an MSI building block.
Ta ble 1-2 ABEL program for the multiplexer.
ELSE Z = B;
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Chapter 1
Introduction
board-level design
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Ta ble 1-3 VHDL program for the multiplexer.
library IEEE; use IEEE.std_logic_1164.all; entity Vchap1mux is port ( A, B, S: in STD_LOGIC; Z: out STD_LOGIC ); end Vchap1mux; architecture Vchap1mux_arch of Vchap1mux is begin Z <= A when S = '0' else B; end Vchap1mux_arch;
behavioral description and produce a circuit that has this behavior in a specified target digital-logic technology. By explicitly enforcing a separation of input/output definitions (entity) and internal realization (architecture), VHDL makes it easy for designers to define alternate realizations of functions without having to make changes elsewhere in the design hierarchy. For example, a designer could specify an alternate, structural architecture for the multiplexer as shown in Table 1-4. This architecture is basically a text equivalent of the logic diagram in Figure 1-9. Going one step further, VHDL is powerful enough that we could actually define operations that model functional behavioral at the transistor level (though we wont explore such capabilities in this book). Thus, we could come full circle by writing a VHDL program that specifies a transistor-level realization of the multiplexer equivalent to Figure 1-8.
Ta ble 1-4 Structural VHDL program for the multiplexer.
architecture Vchap1mux_gate_arch of Vchap1mux is signal SN, ASN, SB: STD_LOGIC; begin U1: INV (S, SN); U2: AND2 (A, SN, ASN); U3: AND2 (S, B, SB); U4: OR2 (ASN, SB, Z); end Vchap1mux_gate_arch;
1.11 The Name of the Game
Given the functional and performance requirements for a digital system, the name of the game in practical digital design is to minimize cost. For board-level designssystems that are packaged on a single PCBthis usually means minimizing the number of IC packages. If too many ICs are required, they wont all fit on the PCB. Well, just use a bigger PCB, you say. Unfortunately, PCB sizes are usually constrained by factors such as pre-existing standards (e.g., add-in
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Section 1.12
Going Forward
23
boards for PCs), packaging constraints (e.g., it has to fit in a toaster), or edicts from above (e.g., in order to get the project approved three months ago, you foolishly told your manager that it would all fit on a 3 5 inch PCB, and now youve got to deliver!). In each of these cases, the cost of using a larger PCB or multiple PCBs may be unacceptable. Minimizing the number of ICs is usually the rule even though individual IC costs vary. For example, a typical SSI or MSI IC may cost 25 cents, while an small PLD may cost a dollar. It may be possible to perform a particular function with three SSI and MSI ICs (75 cents) or one PLD (a dollar). In most situations, the more expensive PLD solution is used, not because the designer owns stock in the IC company, but because the PLD solution uses less PCB area and is also a lot easier to change if its not right the first time. In ASIC design, the name of the game is a little different, but the importance of structured, functional design techniques is the same. Although its easy to burn hours and weeks creating custom macrocells and minimizing the total gate count of an ASIC, only rarely is this advisable. The per-unit cost reduction achieved by having a 10% smaller chip is negligible except in high-volume applications. In applications with low to medium volume (the majority), two other factors are more important: design time and NRE cost. A shorter design time allows a product to reach the market sooner, increasing revenues over the lifetime of the product. A lower NRE cost also flows right to the bottom line, and in small companies may be the only way the project can be completed before the company runs out of money (believe me, Ive been there!). If the product is successful, its always possible and profitable to tweak the design later to reduce per-unit costs. The need to minimize design time and NRE cost argues in favor of a structured, as opposed to highly optimized, approach to ASIC design, using standard building blocks provided in the ASIC manufacturers library. The considerations in PLD, CPLD, and FPGA design are a combination of the above. The choice of a particular PLD technology and device size is usually made fairly early in the design cycle. Later, as long as the design fits in the selected device, theres no point in trying to optimize gate count or board area the device has already been committed. However, if new functions or bug fixes push the design beyond the capacity of the selected device, thats when you must work very hard to modify the design to make it fit.
1.12 Going Forward
This concludes the introductory chapter. As you continue reading this book, keep in mind two things. First, the ultimate goal of digital design is to build systems that solve problems for people. While this book will give you the basic tools for design, its still your job to keep the big picture in the back of your mind. Second, cost is an important factor in every design decision; and you must
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ASIC design
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Chapter 1
Introduction
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Drill Problems
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Copyright 1999 by John F. Wakerly
consider not only the cost of digital components, but also the cost of the design activity itself. Finally, as you get deeper into the text, if you encounter something that you think youve seen before but dont remember where, please consult the index. Ive tried to make it as helpful and complete as possible.
Suggest some better-looking chapter-opening artwork to put on page 1 of the next edition of this book. Give three different definitions for the word bit as used in this chapter. Define the following acronyms: ASIC, CAD, CD, CO, CPLD, DIP, DVD, FPGA, HDL, IC, IP, LSI, MCM, MSI, NRE, OK, PBX, PCB, PLD, PWB, SMT, SSI, VHDL, VLSI. Research the definitions of the following acronyms: ABEL, CMOS, JPEG, MPEG, OK, PERL, VHDL. (Is OK really an acronym?) Excluding the topics in Section 1.2, list three once-analog systems that have gone digital since you were born. Draw a digital circuit consisting of a 2-input AND gate and three inverters, where an inverter is connected to each of the AND gates inputs and its output. For each of the four possible combinations of inputs applied to the two primary inputs of this circuit, determine the value produced at the primary output. Is there a simpler circuit that gives the same input/output behavior? When should you use the pin diagrams of Figure 1-5 in the schematic diagram of a circuit? What is the relationship between die and dice?
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Number Systems and Codes
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2
igital systems are built from circuits that process binary digits 0s and 1syet very few real-life problems are based on binary numbers or any numbers at all. Therefore, a digital system designer must establish some correspondence between the binary digits processed by digital circuits and real-life numbers, events, and conditions. The purpose of this chapter is to show you how familiar numeric quantities can be represented and manipulated in a digital system, and how nonnumeric data, events, and conditions also can be represented. The first nine sections describe binary number systems and show how addition, subtraction, multiplication, and division are performed in these systems. Sections 2.102.13 show how other things, such as decimal numbers, text characters, mechanical positions, and arbitrary conditions, can be encoded using strings of binary digits. Section 2.14 introduces n-cubes, which provide a way to visualize the relationship between different bit strings. The n-cubes are especially useful in the study of error-detecting codes in Section 2.15. We conclude the chapter with an introduction to codes for transmitting and storing data one bit at a time.
Copyright 1999 by John F. Wakerly
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22
Chapter 2
Number Systems and Codes
positional number system weight
base radix
radix point
high-order digit most significant digit low-order digit least significant digit binary digit bit binary radix
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2.1 Positional Number Systems
1734 = 11000 + 7 100 + 310 + 41 5185.68 = 5 1000 + 1100 + 810 + 5 1 + 60.1 + 80.01 D = d1 101 + d0 100 + d1 101 + d2 102 In general, a number D of the form d1d0 . d1d2 has the value dp1dp2 d1d0 . d1d2 dn D=
The traditional number system that we learned in school and use every day in business is called a positional number system. In such a system, a number is represented by a string of digits where each digit position has an associated weight. The value of a number is a weighted sum of the digits, for example:
Each weight is a power of 10 corresponding to the digits position. A decimal point allows negative as well as positive powers of 10 to be used:
Here, 10 is called the base or radix of the number system. In a general positional number system, the radix may be any integer r 2, and a digit in position i has weight r i. The general form of a number in such a system is
where there are p digits to the left of the point and n digits to the right of the point, called the radix point. If the radix point is missing, it is assumed to be to the right of the rightmost digit. The value of the number is the sum of each digit multiplied by the corresponding power of the radix:
di r i = n
p1
i
Except for possible leading and trailing zeroes, the representation of a number in a positional number system is unique. (Obviously, 0185.6300 equals 185.63, and so on.) The leftmost digit in such a number is called the high-order or most significant digit; the rightmost is the low-order or least significant digit. As well learn in Chapter 3, digital circuits have signals that are normally in one of only two conditionslow or high, charged or discharged, off or on. The signals in these circuits are interpreted to represent binary digits (or bits) that have one of two values, 0 and 1. Thus, the binary radix is normally used to represent numbers in a digital system. The general form of a binary number is bp1bp2 b1b0 . b1b2 bn
and its value is
B=
bi 2 i = n
p1
i
Copyright 1999 by John F. Wakerly
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Section 2.2
Octal and Hexadecimal Numbers
23
In a binary number, the radix point is called the binary point. When dealing with binary and other nondecimal numbers, we use a subscript to indicate the radix of each number, unless the radix is clear from the context. Examples of binary numbers and their decimal equivalents are given below. 100112 = 1 16 + 0 8 + 0 4 + 1 2 + 1 1 = 1910 1000102 = 1 32 + 0 16 + 08 + 04 + 1 2 + 01 = 34 10
The leftmost bit of a binary number is called the high-order or m ost significant bit (MSB); the rightmost is the low-order or least significant bit (LSB).
2.2 Octal and Hexadecimal Numbers
Radix 10 is important because we use it in everyday business, and radix 2 is important because binary numbers can be processed directly by digital circuits. Numbers in other radices are not often processed directly, but may be important for documentation or other purposes. In particular, the radices 8 and 16 provide convenient shorthand representations for multibit numbers in a digital system. The octal number system uses radix 8, while the hexadecimal number system uses radix 16. Table 2-1 shows the binary integers from 0 to 1111 and their octal, decimal, and hexadecimal equivalents. The octal system needs 8 digits, so it uses digits 07 of the decimal system. The hexadecimal system needs 16 digits, so it supplements decimal digits 09 with the letters AF. The octal and hexadecimal number systems are useful for representing multibit numbers because their radices are powers of 2. Since a string of three bits can take on eight different combinations, it follows that each 3-bit string can be uniquely represented by one octal digit, according to the third and fourth columns of Table 2-1. Likewise, a 4-bit string can be represented by one hexadecimal digit according to the fifth and sixth columns of the table. Thus, it is very easy to convert a binary number to octal. Starting at the binary point and working left, we simply separate the bits into groups of three and replace each group with the corresponding octal digit: 1000110011102 = 100 011 001 1102 = 43168 111011011101010012 = 011 101 101 110 101 0012 = 3556518
The procedure for binary to hexadecimal conversion is similar, except we use groups of four bits: 1000110011102 = 1000 1100 11102 = 8CE16 111011011101010012 = 00011101 1011 1010 1001 2 = 1DBA916
In these examples we have freely added zeroes on the left to make the total number of bits a multiple of 3 or 4 as required.
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binary point
101. 0012 = 1 4 + 02 + 1 1 + 00.5 + 0 0.25 + 1 0.125 = 5.12510
MSB LSB
octal number system hexadecimal number system hexadecimal digits AF
binary to octal conversion
binary to hexadecimal conversion
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Chapter 2
Number Systems and Codes
3-Bit String 4-Bit String
Ta b l e 2 - 1 Binary, decimal, octal, and hexadecimal numbers.
octal or hexadecimal to binary conversion
byte
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Binary Decimal Octal Hexadecimal
0 1 10 11 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17
000 001 010 011 100 101 110 111
0 1 2 3 4 5 6 7 8 9 A B C D E F
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
If a binary number contains digits to the right of the binary point, we can convert them to octal or hexadecimal by starting at the binary point and working right. Both the left-hand and right-hand sides can be padded with zeroes to get multiples of three or four bits, as shown in the example below: 10.10110010112 = 010 . 101 100 101 1002 = 2.54548 = 0010 . 1011 0010 11002 = 2 .B2C16
Converting in the reverse direction, from octal or hexadecimal to binary, is very easy. We simply replace each octal or hexadecimal digit with the corresponding 3- or 4-bit string, as shown below: 13578 = 001 011 101 1112 2046 .178 = 010 000 100 110 . 001 1112 BEAD16 = 1011 1110 1010 11012
9F. 46C16 = 1001 111 . 0100 0110 11002
The octal number system was quite popular 25 years ago because of certain minicomputers that had their front-panel lights and switches arranged in groups of three. However, the octal number system is not used much today, because of the preponderance of machines that process 8-bit bytes. It is difficult to extract individual byte values in multibyte quantities in the octal representation; for
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Section 2.3
General Positional Number System Conversions
25
example, what are the octal values of the four 8-bit bytes in the 32-bit number with octal representation 123456701238? In the hexadecimal system, two digits represent an 8-bit byte, and 2n digits represent an n-byte word; each pair of digits constitutes exactly one byte. For example, the 32-bit hexadecimal number 5678ABCD 16 consists of four bytes with values 5616, 7816, AB16, and CD16. In this context, a 4-bit hexadecimal digit is sometimes called a nibble; a 32-bit (4-byte) number has eight nibbles. Hexadecimal numbers are often used to describe a computers memory address space. For example, a computer with 16-bit addresses might be described as having read/write memory installed at addresses 0EFFF16, and read-only memory at addresses F000FFFF16. Many computer programming languages use the prefix 0x to denote a hexadecimal number, for example, 0xBFC0000.
2.3 General Positional Number System Conversions
In general, conversion between two radices cannot be done by simple substitutions; arithmetic operations are required. In this section, we show how to convert a number in any radix to radix 10 and vice versa, using radix-10 arithmetic. In Section 2.1, we indicated that the value of a number in any radix is given by the formula D=
where r is the radix of the number and there are p digits to the left of the radix point and n to the right. Thus, the value of the number can be found by converting each digit of the number to its radix-10 equivalent and expanding the formula using radix-10 arithmetic. Some examples are given below: 1CE816 F1A316 436.58 132.34 = = = = 1163 + 12 162 + 14161 + 8 16 0 = 740010 15163 + 1 162 + 10161 + 3 16 0 = 6185910 482 + 3 81 + 6 8 0 + 5 81 = 286.62510 142 + 3 41 + 2 4 0 + 3 41 = 30.7510
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WHEN IM 64 As you grow older, youll find that the hexadecimal number system is useful for more than just computers. When I turned 40, I told friends that I had just turned 2816. The 16 was whispered under my breath, of course. At age 50, Ill be only 3216 . People get all excited about decennial birthdays like 20, 30, 40, 50, , but you should be able to convince your friends that the decimal system is of no fundamental significance. More significant life changes occur around birthdays 2, 4, 8, 16, 32, and 64, when you add a most significant bit to your age. Why do you think the Beatles sang When Im sixty-four? nibble 0x prefix radix-r to decimal conversion
di r i = n
p1
i
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Chapter 2
Number Systems and Codes
decimal to radix-r conversion
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D = (( ((dp1) r + dp2) r + ) r + d1) r + d0 F1AC16 = (((15) 16 + 1 16 + 10) 16 + 12 Q = ( ((dp1) r + dp2) r + ) r + d1 179 2 = 89 remainder 1 (LSB) 2 = 44 remainder 1 2 = 22 remainder 0 2 = 11 remainder 0 2 = 5 remainder 1 2 = 2 remainder 1 2 = 1 remainder 0 2 = 0 remainder 1 17910 = 101100112 (MSB) 467 8 = 58 remainder 3 (least significant digit) 8 = 7 remainder 2 8 = 0 remainder 7 (most significant digit) 46710 = 7238 3417 16 = 213 remainder 9 (least significant digit) 16 = 13 remainder 5 16 = 0 remainder 13 (most significant digit) 341710 = D5916
Copyright 1999 by John F. Wakerly
A shortcut for converting whole numbers to radix 10 is obtained by rewriting the expansion formula as follows:
That is, we start with a sum of 0; beginning with the leftmost digit, we multiply the sum by r and add the next digit to the sum, repeating until all digits have been processed. For example, we can write
Although this formula is not too exciting in itself, it forms the basis for a very convenient method of converting a decimal number D to a radix r. Consider what happens if we divide the formula by r. Since the parenthesized part of the formula is evenly divisible by r, the quotient will be
and the remainder will be d0. Thus, d0 can be computed as the remainder of the long division of D by r. Furthermore, the quotient Q has the same form as the original formula. Therefore, successive divisions by r will yield successive digits of D from right to left, until all the digits of D have been derived. Examples are given below:
Table 2-2 summarizes methods for converting among the most common radices.
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General Positional Number System Conversions
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Conversion
Binary to Octal
Octal to
Hexadecimal to Binary
Decimal to Binary
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Ta b l e 2 - 2 Conversion methods for common radices.
Method Example
Substitution
101110110012 = 10 111 011 0012 = 27318 101110110012 = 101 1101 10012 = 5D916
Hexadecimal Substitution Decimal Summation
101110110012 = 1 1024 + 0 512 + 1 256 + 1 128 + 1 64 + 0 32 + 1 16 + 1 8 + 0 4 + 0 2 + 1 1 = 149710
Binary
Substitution
12348 = 001 010 011 1002
Hexadecimal Substitution Decimal Summation
12348 = 001 010 011 1002 = 0010 1001 11002 = 29C16 12348 = 1 512 + 2 64 + 3 8 + 4 1 = 66810
Substitution
C0DE16 = 1100 0000 1101 11102
Octal
Substitution
C0DE16 = 1100 0000 1101 11102 = 1 100 000 011 011 1102 = 1403368
Decimal
Summation
C0DE16 = 12 4096 + 0 256 + 13 16 + 14 1 = 4937410 10810 2 = 54 remainder 0 (LSB) 2 = 27 remainder 0 2 = 13 remainder 1 2 = 6 remainder 1 2 = 3 remainder 0 2 = 1 remainder 1 2 = 0 remainder 1 10810 = 11011002
Division
(MSB)
Octal
Division
10810 8 = 13 remainder 4 (least significant digit) 8 = 1 remainder 5 8 = 0 remainder 1 (most significant digit) 10810 = 1548
Hexadecimal Division
10810 16 = 6 remainder 12 (least significant digit) 16 = 0 remainder 6 (most significant digit) 10810 = 6C16
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Chapter 2
Number Systems and Codes
binary addition
binary subtraction minuend subtrahend
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Ta b l e 2 - 3 Binary addition and subtraction table.
cin or bin
0 0 0 0 1 1 1 1
x
y
cout
0 0 0 1 0 1 1 1
s
bout
0 1 0 0 1 1 0 1
d
0
0
0
0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 0 1 0 0 1
1 1 0 1 0 0 1
2.4 Addition and Subtraction of Nondecimal Numbers
Addition and subtraction of nondecimal numbers by hand uses the same technique that we learned in grammar school for decimal numbers; the only catch is that the addition and subtraction tables are different. Table 2-3 is the addition and subtraction table for binary digits. To add two binary numbers X and Y, we add together the least significant bits with an initial carry (cin) of 0, producing carry (cout) and sum (s) bits according to the table. We continue processing bits from right to left, adding the carry out of each column into the next columns sum. Two examples of decimal additions and the corresponding binary additions are shown in Figure 2-1, using a colored arrow to indicate a carry of 1. The same examples are repeated below along with two more, with the carries shown as a bit string C: C X 190 +141 Y X + Y 331 101111000 10111110 + 10001101 101001011 C X 173 + 44 Y X+Y 217 C X 170 + 85 Y X+Y 255 001011000 10101101 + 00101100 11011001 000000000 10101010 + 01010101 11111111
C X 127 + 63 Y X + Y 190
011111110 01111111 + 00111111 10111110
Binary subtraction is performed similarly, using borrows (bin and bout) instead of carries between steps, and producing a difference bit d. Two examples of decimal subtractions and the corresponding binary subtractions are shown in Figure 2-2. As in decimal subtraction, the binary minuend values in the columns are modified when borrows occur, as shown by the colored arrows and bits. The
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Copying Prohibited
Section 2.4
1111
Addition and Subtraction of Nondecimal Numbers
1 11
29
X+Y
examples from the figure are repeated below along with two more, this time showing the borrows as a bit string B: B X Y 001111100 11100101 00101110 B X Y 011011010 11010010 01101101 01100101
A very common use of subtraction in computers is to compare two numbers. For example, if the operation X Y produces a borrow out of the most significant bit position, then X is less than Y; otherwise, X is greater than or equal to Y. The relationship between carries and borrow in adders and subtractors will be explored in Section 5.10. Addition and subtraction tables can be developed for octal and hexadecimal digits, or any other desired radix. However, few computer engineers bother to memorize these tables. If you rarely need to manipulate nondecimal numbers,
Must borrow 1, yielding the new subtraction 101 = 1
minuend
subtrahend difference
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X Y 190 10111110 X 173 10101101 + 141 331 +10001101 101001011 Y + 44 217 +00101100 11011001 X+Y
Figure 2-1 Examples of decimal and corresponding binary additions.
229 46 183
210 109 101
XY B X Y
10110111
XY B X Y
170 85
010101010 10101010 01010101
221 76 145
000000000 11011101 01001100 10010001
XY
85
01010101
XY
comparing numbers
After the first borrow, the new subtraction for this column is 01, so we must borrow again.
Figure 2-2 Examples of decimal and corresponding binary subtractions.
The borrow ripples through three columns to reach a borrowable 1, i.e., 100 = 011 (the modified bits) + 1 (the borrow)
0 10 1 1 10 10
0 10 10 0 1 10 0 10 11010010
X Y
229
11100101
X Y
210
46
00101110 10110111
109
01101101 01100101
XY
183
XY
101
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Chapter 2
Number Systems and Codes
hexadecimal addition
signed-magnitude system
sign bit
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C X Y 1100 19B9 +C7E6
16 16 16
then its easy enough on those occasions to convert them to decimal, calculate results, and convert back. On the other hand, if you must perform calculations in binary, octal, or hexadecimal frequently, then you should ask Santa for a programmers hex calculator from Texas Instruments or Casio. If the calculators battery wears out, some mental shortcuts can be used to facilitate nondecimal arithmetic. In general, each column addition (or subtraction) can be done by converting the column digits to decimal, adding in decimal, and converting the result to corresponding sum and carry digits in the nondecimal radix. (A carry is produced whenever the column sum equals or exceeds the radix.) Since the addition is done in decimal, we rely on our knowledge of the decimal addition table; the only new thing that we need to learn is the conversion from decimal to nondecimal digits and vice versa. The sequence of steps for mentally adding two hexadecimal numbers is shown below: 1 1 + 12 14 14 E 1 9 7 0 11 14 0 9 6
X+Y
E19F
17 16+1 1
25 16 +9 9
15 15 F
2.5 Representation of Negative Numbers
So far, we have dealt only with positive numbers, but there are many ways to represent negative numbers. In everyday business, we use the signed-magnitude system, discussed next. However, most computers use one of the complement number systems that we introduce later. 2.5.1 Signed-Magnitude Representation In the signed-magnitude system, a number consists of a magnitude and a symbol indicating whether the magnitude is positive or negative. Thus, we interpret decimal numbers +98, 57, +123.5, and 13 in the usual way, and we also assume that the sign is + if no sign symbol is written. There are two possible representations of zero, +0 and 0, but both have the same value. The signed-magnitude system is applied to binary numbers by using an extra bit position to represent the sign (the sign bit). Traditionally, the most significant bit (MSB) of a bit string is used as the sign bit (0 = plus, 1 = minus), and the lower-order bits contain the magnitude. Thus, we can write several 8-bit signed-magnitude integers and their decimal equivalents: 010101012 = +8510 000000002 = +010 110101012 = 8510 100000002 = 010 011111112 = +12710 111111112 = 12710
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Section 2.5
Representation of Negative Numbers
31
The signed-magnitude system has an equal number of positive and negative integers. An n-bit signed-magnitude integer lies within the range (2n11) through +(2 n11), and there are two possible representations of zero. Now suppose that we wanted to build a digital logic circuit that adds signed-magnitude numbers. The circuit must examine the signs of the addends to determine what to do with the magnitudes. If the signs are the same, it must add the magnitudes and give the result the same sign. If the signs are different, it must compare the magnitudes, subtract the smaller from the larger, and give the result the sign of the larger. All of these ifs, adds, subtracts, and compares translate into a lot of logic-circuit complexity. Adders for complement number systems are much simpler, as well show next. Perhaps the one redeeming feature of a signed-magnitude system is that, once we know how to build a signed-magnitude adder, a signed-magnitude subtractor is almost trivial to buildit need only change the sign of the subtrahend and pass it along with the minuend to an adder. 2.5.2 Complement Number Systems While the signed-magnitude system negates a number by changing its sign, a complement number system negates a number by taking its complement as defined by the system. Taking the complement is more difficult than changing the sign, but two numbers in a complement number system can be added or subtracted directly without the sign and magnitude checks required by the signedmagnitude system. We shall describe two complement number systems, called the radix complement and the diminished radix-complement. In any complement number system, we normally deal with a fixed number of digits, say n. (However, we can increase the number of digits by sign extension as shown in Exercise 2.23, and decrease the number by truncating highorder digits as shown in Exercise 2.24.) We further assume that the radix is r, and that numbers have the form D = dn1dn2 d1d0 .
The radix point is on the right and so the number is an integer. If an operation produces a result that requires more than n digits, we throw away the extra highorder digit(s). If a number D is complemented twice, the result is D. 2.5.3 Radix-Complement Representation In a radix-complement system, the complement of an n-digit number is obtained by subtracting it from r n. In the decimal number system, the radix complement is called the 10s complement. Some examples using 4-digit decimal numbers (and subtraction from 10,000) are shown in Table 2-4. By definition, the radix complement of an n-digit number D is obtained by subtracting it from r n. If D is between 1 and r n 1, this subtraction produces
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signed-magnitude adder signed-magnitude subtractor complement number system radix-complement system 10s complement Copying Prohibited
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Number Systems and Codes
computing the radix complement
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Ta b l e 2 - 4 Examples of 10s and 9s complements.
Number 10s complement 9s complement
1849 2067 100 7 8151 0
8151 7933 9900 9993 1849 10000 (= 0)
8150 7932 9899 9992 1848 9999
another number between 1 and r n 1. If D is 0, the result of the subtraction is rn, which has the form 100 00, where there are a total of n + 1 digits. We throw away the extra high-order digit and get the result 0. Thus, there is only one representation of zero in a radix-complement system. It seems from the definition that a subtraction operation is needed to compute the radix complement of D. However, this subtraction can be avoided by rewriting r n as (r n 1) + 1 and r n D as ((r n 1) D) + 1. The number r n 1 has the form mm mm, where m = r 1 and there are n ms. For example, 10,000 equals 9,999 + 1. If we define the complement of a digit d to be r 1 d, then (r n 1) D is obtained by complementing the digits of D. Therefore, the radix complement of a number D is obtained by complementing the individual
Ta b l e 2 - 5 Digit complements.
Complement Decimal
Digit
Binary
Octal
Hexadecimal
0 1 2 3 4 5 6 7 8 9 A B C D E F
1 0
7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
F E D C B A 9 8 7 6 5 4 3 2 1 0
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Section 2.5
Representation of Negative Numbers
33
digits of D and adding 1. For example, the 10s complement of 1849 is 8150 + 1, or 8151. You should confirm that this trick also works for the other 10s-complement examples above. Table 2-5 lists the digit complements for binary, octal, decimal, and hexadecimal numbers. 2.5.4 Twos-Complement Representation For binary numbers, the radix complement is called the twos complement. The MSB of a number in this system serves as the sign bit; a number is negative if and only if its MSB is 1. The decimal equivalent for a twos-complement binary number is computed the same way as for an unsigned number, except that the weight of the MSB is 2 n1 instead of +2 n1. The range of representable numbers is (2 n1) through +(2 n1 1). Some 8-bit examples are shown below: 1710 = 000100012 . complement bits 11101110 +1 111011112 = 1710
11910 =
010 =
A carry out of the MSB position occurs in one case, as shown in color above. As in all twos-complement operations, this bit is ignored and only the low-order n bits of the result are used. In the twos-complement number system, zero is considered positive because its sign bit is 0. Since twos complement has only one representation of zero, we end up with one extra negative number, (2 n1), that doesnt have a positive counterpart. We can convert an n-bit twos-complement number X into an m-bit one, but some care is needed. If m > n, we must append m n copies of Xs sign bit to the left of X (see Exercise 2.23). That is, we pad a positive number with 0s and a negative one with 1s; this is called sign extension. If m < n, we discard Xs n m
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twos complement weight of MSB
9910 = 100111012 . complement bits 01100010 +1 011000112 = 9910
12710 = 10000001 01110111 . complement bits . complement bits 10001000 01111110 +1 +1 100010012 = 11910 011111112 = 12710
12810 = 100000002 000000002 . complement bits . complement bits 11111111 01111111 +1 +1 2 =0 1 00000000 100000002 = 12810 10
extra negative number
sign extension
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Chapter 2
Number Systems and Codes
diminished radixcomplement system 9s complement
ones complement
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1710 = 000100012 . 111011102 = 1710 9910 = 100111002 . 011000112 = 9910 11910 = 011101112 . 100010002 = 11910 12710 = 100000002 . 011111112 = 12710 010 = 000000002 (positive zero)0000000 . 000 0111111112 = 0 10 (negative zero)
* Throughout this book, optional sections are marked with an asterisk.
leftmost bits; however, the result is valid only if all of the discarded bits are the same as the sign bit of the result (see Exercise 2.24). Most computers and other digital systems use the twos-complement system to represent negative numbers. However, for completeness, well also describe the diminished radix-complement and ones-complement systems.
*2.5.5 Diminished Radix-Complement Representation In a diminished radix-complement system, the complement of an n-digit number D is obtained by subtracting it from r n1. This can be accomplished by complementing the individual digits of D, without adding 1 as in the radix-complement system. In decimal, this is called the 9s complement; some examples are given in the last column of Table 2-4 on page 32.
*2.5.6 Ones-Complement Representation The diminished radix-complement system for binary numbers is called the ones complement. As in twos complement, the most significant bit is the sign, 0 if positive and 1 if negative. Thus there are two representations of zero, positive zero (00 00) and negative zero (11 11). Positive number representations are the same for both ones and twos complements. However, negative number representations differ by 1. A weight of (2n1 1), rather than 2n1, is given to the most significant bit when computing the decimal equivalent of a onescomplement number. The range of representable numbers is (2n1 1) through +(2n1 1). Some 8-bit numbers and their ones complements are shown below:
The main advantages of the ones-complement system are its symmetry and the ease of complementation. However, the adder design for onescomplement numbers is somewhat trickier than a twos-complement adder (see Exercise 7.67). Also, zero-detecting circuits in a ones-complement system
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Section 2.6
Twos-Complement Addition and Subtraction
35
either must check for both representations of zero, or must always convert 11 11 to 00 00.
*2.5.7 Excess Representations Yes, the number of different systems for representing negative numbers is excessive, but theres just one more for us to cover. In excess-B representation, an m -bit string whose unsigned integer value is M (0 M < 2m) represents the signed integer M B, where B is called the bias of the number system. For example, an excess2m1 system represents any number X in the range m1 through +2m1 1 by the m-bit binary representation of X + 2m1 (which 2 is always nonnegative and less than 2m). The range of this representation is exactly the same as that of m-bit twos-complement numbers. In fact, the representations of any number in the two systems are identical except for the sign bits, which are always opposite. (Note that this is true only when the bias is 2m1.) The most common use of excess representations is in floating-point number systems (see References).
2.6 Twos-Complement Addition and Subtraction
2.6.1 Addition Rules A table of decimal numbers and their equivalents in different number systems, Table 2-6, reveals why the twos complement is preferred for arithmetic operations. If we start with 10002 (810) and count up, we see that each successive twos-complement number all the way to 01112 (+710) can be obtained by adding 1 to the previous one, ignoring any carries beyond the fourth bit position. The same cannot be said of signed-magnitude and ones-complement numbers. Because ordinary addition is just an extension of counting, twos-complement numbers can thus be added by ordinary binary addition, ignoring any carries beyond the MSB. The result will always be the correct sum as long as the range of the number system is not exceeded. Some examples of decimal addition and the corresponding 4-bit twos-complement additions confirm this: +3 + +4 +7 0011 + 0100 0111 2 + 6 8 1110 + 1010 11000
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bias excess-2m1 system twos-complement addition
excess-B representation
+6 + 3 +3
0110 + 1101 10011
+4 + 7 3
0100 + 1001 1101
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Chapter 2
Number Systems and Codes
Figure 2-3 A modular counting representation of 4-bit twos-complement numbers.
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Ta b l e 2 - 6 Decimal and 4-bit numbers.
Twos Complement Ones Complement D ecimal Signed Magnitude Excess 2 m1
8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
1000 1001 1010 1011 1100 1101 1110 1111
0000
1000 1001 1010 1011 1100 1101 1110
1111 1110 1101 1100 1011 1010 1001
0001 0010 0011 0100 0101 0110 0111
0000
1111 or 0000 0001 0010 0011 0100 0101 0110 0111
1000 or 0000 0001 0010 0011 0100 0101 0110 0111
1000
0001 0010 0011 0100 0101 0110 0111
1001 1010 1011 1100 1101 1110 1111
2.6.2 A Graphical View Another way to view the twos-complement system uses the 4-bit counter shown in Figure 2-3. Here we have shown the numbers in a circular or modular representation. The operation of this counter very closely mimics that of a real up/down counter circuit, which well study in Section 8.4. Starting
0000 +0
1111
0001
1110
1
+1
0010
1101
2
+2
0011
3
+3
Subtraction of positive numbers
1100
4
+4
0100
Addition of positive numbers
5
+5
1011
6
+6
0101
7
1010
8
+7
0110
1001
1000
0111
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Twos-Complement Addition and Subtraction
37
with the arrow pointing to any number, we can add +n to that number by counting up n times, that is, by moving the arrow n positions clockwise. It is also evident that we can subtract n from a number by counting down n times, that is, by moving the arrow n positions counterclockwise. Of course, these operations give correct results only if n is small enough that we dont cross the discontinuity between 8 and +7. What is most interesting is that we can also subtract n (or add n) by moving the arrow 16 n positions clockwise. Notice that the quantity 16 n is what we defined to be the 4-bit twos complement of n, that is, the twos-complement representation of n. This graphically supports our earlier claim that a negative number in twos-complement representation may be added to another number simply by adding the 4-bit representations using ordinary binary addition. Adding a number in Figure 2-3 is equivalent to moving the arrow a corresponding number of positions clockwise. 2.6.3 Overflow If an addition operation produces a result that exceeds the range of the number system, overflow is said to occur. In the modular counting representation of Figure 2-3, overflow occurs during addition of positive numbers when we count past +7. Addition of two numbers with different signs can never produce overflow, but addition of two numbers of like sign can, as shown by the following examples: 3 + 6 9 1101 + 1010 10111 = +7 +5 + +6 +11 0101 + 0110 1011 = 5
Fortunately, there is a simple rule for detecting overflow in addition: An addition overflows if the signs of the addends are the same and the sign of the sum is different from the addends sign. The overflow rule is sometimes stated in terms of carries generated during the addition operation: An addition overflows if the carry bits cin into and cout out of the sign position are different. Close examination of Table 2-3 on page 28 shows that the two rules are equivalentthere are only two cases where cin cout, and these are the only two cases where x = y and the sum bit is different. 2.6.4 Subtraction Rules Twos-complement numbers may be subtracted as if they were ordinary unsigned binary numbers, and appropriate rules for detecting overflow may be formulated. However, most subtraction circuits for twos-complement numbers
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overflow
8 + 8 16
1000 + 1000 10000 = +0
+7 + +7 +14
0111 + 0111 1110 = 2
overflow rules
twos-complement subtraction
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+4 +3 +3 0100 0011 1 cin 0100 + 1100 10001 1 cin 0011 + 0011 0111 +3 +4 1 0011 0100 1 cin 0011 + 1011 1111 1 cin 1101 + 0011 1 0001 +3 4 +7 0011 1100 3 4 +1 1101 1100 (8) = 1000 = 0111 + 0001 1000 = 8 +4 + 8 4 0100 + 1000 1100 3 8 +5 1101 1000 1 cin 1101 + 0111 1 0101
Copyright 1999 by John F. Wakerly
do not perform subtraction directly. Rather, they negate the subtrahend by taking its twos complement, and then add it to the minuend using the normal rules for addition. Negating the subtrahend and adding the minuend can be accomplished with only one addition operation as follows: Perform a bit-by-bit complement of the subtrahend and add the complemented subtrahend to the minuend with an initial carry (cin) of 1 instead of 0. Examples are given below:
Overflow in subtraction can be detected by examining the signs of the minuend and the complemented subtrahend, using the same rule as in addition. Or, using the technique in the preceding examples, the carries into and out of the sign position can be observed and overflow detected irrespective of the signs of inputs and output, again using the same rule as in addition. An attempt to negate the extra negative number results in overflow according to the rules above, when we add 1 in the complementation process:
However, this number can still be used in additions and subtractions as long as the final result does not exceed the number range:
2.6.5 Twos-Complement and Unsigned Binary Numbers Since twos-complement numbers are added and subtracted by the same basic binary addition and subtraction algorithms as unsigned numbers of the same length, a computer or other digital system can use the same adder circuit to handle numbers of both types. However, the results must be interpreted differently
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Section 2.6
Twos-Complement Addition and Subtraction
39
depending on whether the system is dealing with signed numbers (e.g., 8 through +7) or unsigned numbers (e.g., 0 through 15). We introduced a graphical representation of the 4-bit twos-complement system in Figure 2-3. We can relabel this figure as shown in Figure 2-4 to obtain a representation of the 4-bit unsigned numbers. The binary combinations occupy the same positions on the wheel, and a number is still added by moving the arrow a corresponding number of positions clockwise, and subtracted by moving the arrow counterclockwise. An addition operation can be seen to exceed the range of the 4-bit unsigned number system in Figure 2-4 if the arrow moves clockwise through the discontinuity between 0 and 15. In this case a carry out of the most significant bit position is said to occur. Likewise a subtraction operation exceeds the range of the number system if the arrow moves counterclockwise through the discontinuity. In this case a borrow out of the most significant bit position is said to occur. From Figure 2-4 it is also evident that we may subtract an unsigned number n by counting clockwise 16 n positions. This is equivalent to adding the 4-bit twos-complement of n. The subtraction produces a borrow if the corresponding addition of the twos complement does not produce a carry. In summary, in unsigned addition the carry or borrow in the most significant bit position indicates an out-of-range result. In signed, twos-complement addition the overflow condition defined earlier indicates an out-of-range result. The carry from the most significant bit position is irrelevant in signed addition in the sense that overflow may or may not occur independently of whether or not a carry occurs.
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signed vs. unsigned numbers carry borrow
0000 0 1111 0001 1110 15 1 0010 1101 14 2 0011 13 3 Subtraction 1100 12 4 0100 Addition 11 5 1011 10 6 0101 9 1010 8 7 0110 1001 1000 0111
Figure 2-4 A modular counting representation of 4-bit unsigned numbers.
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Chapter 2
Number Systems and Codes
ones-complement addition
end-around carry
ones-complement subtraction
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*2.7 Ones-Complement Addition and Subtraction
+3 + +4 +7 0011 + 0100 0111 +4 + 7 3 0100 + 1000 1100 +5 + 5 0 0101 + 1010 1111 2 + 5 7 1101 + 1010 10111 + 1 1000 +6 + 3 +3 0110 + 1100 10010 + 1 0011 0 + 0 0 1111 + 1111 1 1110 + 1 1111
Copyright 1999 by John F. Wakerly
Another look at Table 2-6 helps to explain the rule for adding ones-complement numbers. If we start at 10002 (710) and count up, we obtain each successive ones-complement number by adding 1 to the previous one, except at the transition from 11112 (negative 0) to 00012 (+110). To maintain the proper count, we must add 2 instead of 1 whenever we count past 11112. This suggests a technique for adding ones-complement numbers: Perform a standard binary addition, but add an extra 1 whenever we count past 1111 2. Counting past 11112 during an addition can be detected by observing the carry out of the sign position. Thus, the rule for adding ones-complement numbers can be stated quite simply: Perform a standard binary addition; if there is a carry out of the sign position, add 1 to the result.
This rule is often called end-around carry. Examples of ones-complement addition are given below; the last three include an end-around carry:
Following the two-step addition rule above, the addition of a number and its ones complement produces negative 0. In fact, an addition operation using this rule can never produce positive 0 unless both addends are positive 0. As with twos complement, the easiest way to do ones-complement subtraction is to complement the subtrahend and add. Overflow rules for onescomplement addition and subtraction are the same as for twos complement. Table 2-7 summarizes the rules that we presented in this and previous sections for negation, addition, and subtraction in binary number systems.
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Section *2.8
Binary Multiplication
41
Number System
Unsigned
Signed magnitude
Twos complement
Ones complement
*2.8 Binary Multiplication
In grammar school we learned to multiply by adding a list of shifted multiplicands computed according to the digits of the multiplier. The same method can be used to obtain the product of two unsigned binary numbers. Forming the shifted multiplicands is trivial in binary multiplication, since the only possible values of the multiplier digits are 0 and 1. An example is shown below: 11 13 33 110 143 1011 1101 1011 00000 101100 1011000 10001111 multiplicand multiplier
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T a b l e 2 - 7 Summary of addition and subtraction rules for binary numbers.
Addition Rules Negation Rules Subtraction Rules
Add the numbers. Result is out of Not applicable range if a carry out of the MSB occurs.
Subtract the subtrahend from the minuend. Result is out of range if a borrow out of the MSB occurs. Change the sign bit of the subtrahend and proceed as in addition.
(same sign) Add the magnitudes; Change the numbers overflow occurs if a carry out of sign bit. MSB occurs; result has the same sign. (opposite sign) Subtract the smaller magnitude from the larger; overflow is impossible; result has the sign of the larger.
Add, ignoring any carry out of Complement all bits of the MSB. Overflow occurs if the the number; add 1 to the carries into and out of MSB are result. different. Add; if there is a carry out of the Complement all bits of MSB, add 1 to the result. Over- the number. flow if carries into and out of MSB are different.
Complement all bits of the subtrahend and add to the minuend with an initial carry of 1. Complement all bits of the subtrahend and proceed as in addition.
shift-and-add multiplication
unsigned binary multiplication
shifted multiplicands
product
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Chapter 2
Number Systems and Codes
partial product
signed multiplication
twos-complement multiplication
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11 13
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Instead of listing all the shifted multiplicands and then adding, in a digital system it is more convenient to add each shifted multiplicand as it is created to a partial product. Applying this technique to the previous example, four additions and partial products are used to multiply 4-bit numbers:
1011 multiplicand 1101 multiplier 0000 partial product 1011 shifted multiplicand 01011 partial product 0000 shifted multiplicand 001011 partial product 1011 shifted multiplicand 0110111 partial product 1011 shifted multiplicand 10001111 product In general, when we multiply an n-bit number by an m-bit number, the resulting product requires at most n + m bits to express. The shift-and-add algorithm requires m partial products and additions to obtain the result, but the first addition is trivial, since the first partial product is zero. Although the first partial product has only n significant bits, after each addition step the partial product gains one more significant bit, since each addition may produce a carry. At the same time, each step yields one more partial product bit, starting with the rightmost and working toward the left, that does not change. The shift-and-add algorithm can be performed by a digital circuit that includes a shift register, an adder, and control logic, as shown in Section 8.7.2. Multiplication of signed numbers can be accomplished using unsigned multiplication and the usual grammar school rules: Perform an unsigned multiplication of the magnitudes and make the product positive if the operands had the same sign, negative if they had different signs. This is very convenient in signed-magnitude systems, since the sign and magnitude are separate. In the twos-complement system, obtaining the magnitude of a negative number and negating the unsigned product are nontrivial operations. This leads us to seek a more efficient way of performing twos-complement multiplication, described next. Conceptually, unsigned multiplication is accomplished by a sequence of unsigned additions of the shifted multiplicands; at each step, the shift of the multiplicand corresponds to the weight of the multiplier bit. The bits in a twoscomplement number have the same weights as in an unsigned number, except for the MSB, which has a negative weight (see Section 2.5.4). Thus, we can perform twos-complement multiplication by a sequence of twos-complement additions of shifted multiplicands, except for the last step, in which the shifted
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Section *2.9
Binary Division
43
multiplicand corresponding to the MSB of the multiplier must be negated before it is added to the partial product. Our previous example is repeated below, this time interpreting the multiplier and multiplicand as twos-complement numbers: 5 3
1011 multiplicand 1101 multiplier 00000 partial product 11011 shifted multiplicand 111011 partial product 00000 shifted multiplicand 1111011 partial product 11011 shifted multiplicand 11100111 partial product 00101 shifted and negated multiplicand 00001111 product Handling the MSBs is a little tricky because we gain one significant bit at each step and we are working with signed numbers. Therefore, before adding each shifted multiplicand and k-bit partial product, we change them to k + 1 significant bits by sign extension, as shown in color above. Each resulting sum has k + 1 bits; any carry out of the MSB of the k + 1-bit sum is ignored.
*2.9 Binary Division
The simplest binary division algorithm is based on the shift-and-subtract method that we learned in grammar school. Table 2-8 gives examples of this method for unsigned decimal and binary numbers. In both cases, we mentally compare the 19 11 )217 110 107 99 8 10011 1011 )11011001 10110000 0101000 0000000 101000 000000 101000 10110 10011 1011 1000 quotient dividend shifted divisor reduced dividend shifted divisor reduced dividend shifted divisor reduced dividend shifted divisor reduced dividend shifted divisor remainder
Ta b l e 2 - 8 Example of long division.
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shift-and-subtract division unsigned division Copying Prohibited
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Chapter 2
Number Systems and Codes
division overflow signed division
code code word
binary-coded decimal (BCD)
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2.10 Binary Codes for Decimal Numbers
Copyright 1999 by John F. Wakerly
reduced dividend with multiples of the divisor to determine which multiple of the shifted divisor to subtract. In the decimal case, we first pick 11 as the greatest multiple of 11 less than 21, and then pick 99 as the greatest multiple less than 107. In the binary case, the choice is somewhat simpler, since the only two choices are zero and the divisor itself. Division methods for binary numbers are somewhat complementary to binary multiplication methods. A typical division algorithm accepts an n+m-bit dividend and an n-bit divisor, and produces an m-bit quotient and an n-bit remainder. A division overflows if the divisor is zero or the quotient would take more than m bits to express. In most computer division circuits, n = m. Division of signed numbers can be accomplished using unsigned division and the usual grammar school rules: Perform an unsigned division of the magnitudes and make the quotient positive if the operands had the same sign, negative if they had different signs. The remainder should be given the same sign as the dividend. As in multiplication, there are special techniques for performing division directly on twos-complement numbers; these techniques are often implemented in computer division circuits (see References).
Even though binary numbers are the most appropriate for the internal computations of a digital system, most people still prefer to deal with decimal numbers. As a result, the external interfaces of a digital system may read or display decimal numbers, and some digital devices actually process decimal numbers directly. The human need to represent decimal numbers doesnt change the basic nature of digital electronic circuitsthey still process signals that take on one of only two states that we call 0 and 1. Therefore, a decimal number is represented in a digital system by a string of bits, where different combinations of bit values in the string represent different decimal numbers. For example, if we use a 4-bit string to represent a decimal number, we might assign bit combination 0000 to decimal digit 0, 0001 to 1, 0010 to 2, and so on. A set of n-bit strings in which different bit strings represent different numbers or other things is called a code. A particular combination of n bit-values is called a code word. As well see in the examples of decimal codes in this section, there may or may not be an arithmetic relationship between the bit values in a code word and the thing that it represents. Furthermore, a code that uses n-bit strings need not contain 2n valid code words. At least four bits are needed to represent the ten decimal digits. There are billions and billions of different ways to choose ten 4-bit code words, but some of the more common decimal codes are listed in Table 2-9. Perhaps the most natural decimal code is binary-coded decimal (BCD), which encodes the digits 0 through 9 by their 4-bit unsigned binary representaCopying Prohibited
Section 2.10
Binary Codes for Decimal Numbers
45
Decimal digit
tions, 0000 through 1001. The code words 1010 through 1111 are not used. Conversions between BCD and decimal representations are trivial, a direct substitution of four bits for each decimal digit. Some computer programs place two BCD digits in one 8-bit byte in packed-BCD representation; thus, one byte may represent the values from 0 to 99 as opposed to 0 to 255 for a normal unsigned 8bit binary number. BCD numbers with any desired number of digits may be obtained by using one byte for each two digits. As with binary numbers, there are many possible representations of negative BCD numbers. Signed BCD numbers have one extra digit position for the
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Ta b l e 2 - 9 Decimal codes.
BCD (8421) 2421 Excess-3 Biquinary 1-out-of-10
0 1 2 3 4 5 6 7 8 9
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
0000 0001 0010 0011 0100 1011 1100 1101 1110 1111
0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
0100001 0100010 0100100 0101000 0110000 1000001 1000010 1000100 1001000 1010000
1000000000 0100000000 0010000000 0001000000 0000100000 0000010000 0000001000 0000000100 0000000010 0000000001
Unused code words
1010 1011 1100 1101 1110 1111
0101 0110 0111 1000 1001 1010
0000 0001 0010 1101 1110 1111
0000000 0000001 0000010 0000011 0000101
0000000000 0000000011 0000000101 0000000110 0000000111
packed-BCD representation
BINOMIAL COEFFICIENTS
The number of different ways to choose m items from a set of n items is given by n! a binomial coefficient, denoted n , whose value is ------------------------------ . For a 4-bit m m! ( n m! ) decimal code, there are 16 different ways to choose 10 out of 16 4-bit code 10 words, and 10! ways to assign each different choice to the 10 digits. So there are 16! ---------------- 10! or 29,059,430,400 different 4-bit decimal codes. 10! 6! Copying Prohibited
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Chapter 2
Number Systems and Codes
BCD addition
weighted code
8421 code 2421 code self-complementing code excess-3 code
biquinary code
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+ 5 9 14 10+4 0101 + 1001 1110 + 0110 correction 1 0100 + 4 5 9 0100 + 0101 1001 8 +8 16
Copyright 1999 by John F. Wakerly
sign. Both the signed-magnitude and 10s-complement representations are popular. In signed-magnitude BCD, the encoding of the sign bit string is arbitrary; in 10s-complement, 0000 indicates plus and 1001 indicates minus. Addition of BCD digits is similar to adding 4-bit unsigned binary numbers, except that a correction must be made if a result exceeds 1001. The result is corrected by adding 6; examples are shown below:
1001 9 1000 + 9 + 1001 + 1000 18 1 0010 1 0000 + 0110 correction + 0110 correction 10+6 1 0110 10+8 1 1000 Notice that the addition of two BCD digits produces a carry into the next digit position if either the initial binary addition or the correction factor addition produces a carry. Many computers perform packed-BCD arithmetic using special instructions that handle the carry correction automatically. Binary-coded decimal is a weighted code because each decimal digit can be obtained from its code word by assigning a fixed weight to each code-word bit. The weights for the BCD bits are 8, 4, 2, and 1, and for this reason the code is sometimes called the 8421 code. Another set of weights results in the 2421 code shown in Table 2-9. This code has the advantage that it is selfcomplementing, that is, the code word for the 9s complement of any digit may be obtained by complementing the individual bits of the digits code word. Another self-complementing code shown in Table 2-9 is the excess-3 code. Although this code is not weighted, it has an arithmetic relationship with the BCD codethe code word for each decimal digit is the corresponding BCD code word plus 00112. Because the code words follow a standard binary counting sequence, standard binary counters can easily be made to count in excess-3 code, as well show in Figure 8-37 on page 600. Decimal codes can have more than four bits; for example, the biquinary code in Table 2-9 uses seven. The first two bits in a code word indicate whether the number is in the range 04 or 59, and the last five bits indicate which of the five numbers in the selected range is represented. One potential advantage of using more than the minimum number of bits in a code is an error-detecting property. In the biquinary code, if any one bit in a code word is accidentally changed to the opposite value, the resulting code word
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Section 2.11
Gray Code
47
does not represent a decimal digit and can therefore be flagged as an error. Out of 128 possible 7-bit code words, only 10 are valid and recognized as decimal digits; the rest can be flagged as errors if they appear. A 1-out-of-10 code such as the one shown in the last column of Table 2-9 is the sparsest encoding for decimal digits, using 10 out of 1024 possible 10-bit code words.
2.11 Gray Code
In electromechanical applications of digital systemssuch as machine tools, automotive braking systems, and copiersit is sometimes necessary for an input sensor to produce a digital value that indicates a mechanical position. For example, Figure 2-5 is a conceptual sketch of an encoding disk and a set of contacts that produce one of eight 3-bit binary-coded values depending on the rotational position of the disk. The dark areas of the disk are connected to a signal source corresponding to logic 1, and the light areas are unconnected, which the contacts interpret as logic 0. The encoder in Figure 2-5 has a problem when the disk is positioned at certain boundaries between the regions. For example, consider the boundary between the 001 and 010 regions of the disk; two of the encoded bits change here. What value will the encoder produce if the disk is positioned right on the theoretical boundary? Since were on the border, both 001 and 010 are acceptable. However, because the mechanical assembly is not perfect, the two righthand contacts may both touch a 1 region, giving an incorrect reading of 011. Likewise, a reading of 000 is possible. In general, this sort of problem can occur at any boundary where more than one bit changes. The worst problems occur when all three bits are changing, as at the 000111 and 011100 boundaries. The encoding-disk problem can be solved by devising a digital code in which only one bit changes between each pair of successive code words. Such a code is called a Gray code; a 3-bit Gray code is listed in Table 2-10. Weve rede-
110
101
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1-out-of-10 code Gray code
111 000 001
Figure 2-5 A mechanical encoding disk using a 3-bit binary code.
001
010
100
011
Copyright 1999 by John F. Wakerly
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Chapter 2
Number Systems and Codes
reflected code
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Ta b l e 2 - 1 0 A comparison of 3-bit binary code and Gray code.
Decimal number Binary code Gray code
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
000 001 011 010 110 111 101 100
signed the encoding disk using this code as shown in Figure 2-6. Only one bit of the new disk changes at each border, so borderline readings give us a value on one side or the other of the border. There are two convenient ways to construct a Gray code with any desired number of bits. The first method is based on the fact that Gray code is a reflected code; it can be defined (and constructed) recursively using the following rules: 1. A 1-bit Gray code has two code words, 0 and 1. 2. The first 2 n code words of an n+1-bit Gray code equal the code words of an n-bit Gray code, written in order with a leading 0 appended. 3. The last 2n code words of an n+1-bit Gray code equal the code words of an n-bit Gray code, but written in reverse order with a leading 1 appended.
If we draw a line between rows 3 and 4 of Table 2-10, we can see that rules 2 and 3 are true for the 3-bit Gray code. Of course, to construct an n-bit Gray code for an arbitrary value of n with this method, we must also construct a Gray code of each length smaller than n.
Figure 2-6 A mechanical encoding disk using a 3-bit Gray code.
100
000
101
001
001
111
011
110
010
Copyright 1999 by John F. Wakerly
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Section *2.12
Character Codes
49
The second method allows us to derive an n-bit Gray-code code word directly from the corresponding n-bit binary code word:
1. The bits of an n-bit binary or Gray-code code word are numbered from right to left, from 0 to n 1. 2. Bit i of a Gray-code code word is 0 if bits i and i + 1 of the corresponding binary code word are the same, else bit i is 1. (When i + 1 = n, bit n of the binary code word is considered to be 0.) Again, inspection of Table 2-10 shows that this is true for the 3-bit Gray code.
*2.12 Character Codes
As we showed in the preceding section, a string of bits need not represent a number, and in fact most of the information processed by computers is nonnumeric. The most common type of nonnumeric data is text, strings of characters from some character set. Each character is represented in the computer by a bit string according to an established convention. The most commonly used character code is ASCII (pronounced ASS key), the American Standard Code for Information Interchange. ASCII represents each character with a 7-bit string, yielding a total of 128 different characters shown in Table 2-11. The code contains the uppercase and lowercase alphabet, numerals, punctuation, and various nonprinting control characters. Thus, the text string Yeccch! is represented by a rather innocuous-looking list of seven 7-bit numbers: 1011001 1100101 1100011 1100011 1100011 1101000 0100001
2.13 Codes for Actions, Conditions, and States
The codes that weve described so far are generally used to represent things that we would probably consider to be datathings like numbers, positions, and characters. Programmers know that dozens of different data types can be used in a single computer program. In digital system design, we often encounter nondata applications where a string of bits must be used to control an action, to flag a condition, or to represent the current state of the hardware. Probably the most commonly used type of code for such an application is a simple binary code. If there are n different actions, conditions, or states, we can represent them with a b-bit binary code with b = log2 n bits. (The brackets denote the ceiling functionthe smallest integer greater than or equal to the bracketed quantity. Thus, b is the smallest integer such that 2b n.) For example, consider a simple traffic-light controller. The signals at the intersection of a north-south (N-S) and an east-west (E-W) street might be in any
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text ASCII ceiling function
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Chapter 2
Number Systems and Codes
b3b2b1b0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI
SP
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Ta b l e 2 - 1 1 American Standard Code for Information Interchange (ASCII), Standard No. X3.4-1968 of the American National Standards Institute.
b6b5b4 (column) 011 3 Row (hex) 000 0 001 1 010 2 100 4 101 5 110 6 111 7
0 1 2 3 4 5 6 7 8 9 A B C D E F
NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI
DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US
SP ! " # $ % & ( ) * + , . /
0 1 2 3 4 5 6 7 8 9 : ; < = > ?
@ A B C D E F G H I J K L M N O
P Q R S T U V W X Y Z [ \ ] ^ _
a b c d e f g h i j k l m n o
p q r s t u v w x y z { | } ~ DEL
Control codes
Null Start of heading Start of text End of text End of transmission Enquiry Acknowledge Bell Backspace Horizontal tab Line feed Vertical tab Form feed Carriage return Shift out Shift in
DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US
Data link escape Device control 1 Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronize End transmitted block Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator
Space
DEL
Delete or rubout
Copyright 1999 by John F. Wakerly
Copying Prohibited
Section 2.13
Codes for Actions, Conditions, and States
51
N-S go
N-S wait
N-S delay E-W go
E-W wait
E-W delay
of the six states listed in Table 2-12. These states can be encoded in three bits, as shown in the last column of the table. Only six of the eight possible 3-bit code words are used, and the assignment of the six chosen code words to states is arbitrary, so many other encodings are possible. An experienced digital designer chooses a particular encoding to minimize circuit cost or to optimize some other parameter (like design timetheres no need to try billions and billions of possible encodings). Another application of a binary code is illustrated in Figure 2-7(a). Here, we have a system with n devices, each of which can perform a certain action. The characteristics of the devices are such that they may be enabled to operate only one at a time. The control unit produces a binary-coded device select word with log2 n bits to indicate which device is enabled at any time. The device select code word is applied to each device, which compares it with its own device ID to determine whether it is enabled.Although its code words have the minimum number of bits, a binary code isnt always the best choice for encoding actions, conditions, or states. Figure 2-7(b) shows how to control n devices with a 1-out-of-n code, an n-bit code in which valid code words have one bit equal to 1 and the rest of the bits equal to 0. Each bit of the 1-out-of-n code word is connected directly to the enable input of a corresponding device. This simplifies the design of the devices, since they no longer have device IDs; they need only a single enable input bit. The code words of a 1-out-of-10 code were listed in Table 2-9. Sometimes an all-0s word may also be included in a 1-out-of-n code, to indicate that no device is selected. Another common code is an inverted 1-out-of-n code, in which valid code words have one 0~bit and the rest of the bits equal to 1. In complex systems, a combination of coding techniques may be used. For example, consider a system similar to Figure 2-7(b), in which each of the n devices contains up to s subdevices. The control unit could produce a device
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Ta b l e 2 - 1 2 States in a traffic-light controller.
Lights State N-S green N-S yellow N-S red E-W green E-W yellow E-W red Code word
ON off
off
off
off
off off
ON
000
ON off
off
off
ON
001
off
ON
off
off off
ON off
010
off
off
ON
ON off
100
off
off
ON
ON off
off
101
off
off
ON
off
ON
110
1-out-of-n code
inverted 1-out-of-n code
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(a)
(b)
m-out-of-n code
8B10B code
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Control Unit binary-coded device select compare device ID compare device ID compare device ID device enable device enable device enable Device Device Device 1-out-of-n coded device select Control Unit device enable device enable device enable Device Device Device
Figure 2-7 Control structure for a digital system with n devices: (a) using a binary code; (b) using a 1-out-of-n code.
select code word with a 1-out-of-n coded field to select a device, and a log2 sbit binary-coded field to select one of the s subdevices of the selected device. An m-out-of-n code is a generalization of the 1-out-of-n code in which valid code words have m bits equal to 1 and the rest of the bits equal to 0. A valid m -out-of-n code word can be detected with an m-input AND gate, which produces a 1 output if all of its inputs are 1. This is fairly simple and inexpensive to do, yet for most values of m, an m-out-of-n code typically has far more valid code words than a 1-out-of-n code. The total number of code words is given by the
n! binomial coefficient n , which has the value ------------------------------ . Thus, a 2-out-of-4 m m! ( n m )!
code has 6 valid code words, and a 3-out-of-10 code has 120. An important variation of an m-out-of-n code is the 8B10B code used in the 802.3z Gigabit Ethernet standard. This code uses 10 bits to represent 256 valid code words, or 8 bits worth of data. Most code words use a 5-out-of-10 coding. However, since 5 is only 252, some 4- and 6-out-of-10 words are also used to 10 complete the code in a very interesting way; more on this in Section 2.16.2.
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10 11
n-Cubes and Distance
53
010
000
*2.14 n-Cubes and Distance
An n-bit string can be visualized geometrically, as a vertex of an object called an n-cube. Figure 2-8 shows n-cubes for n = 1, 2, 3, 4. An n-cube has 2n vertices, each of which is labeled with an n-bit string. Edges are drawn so that each vertex is adjacent to n other vertices whose labels differ from the given vertex in only one bit. Beyond n = 4, n-cubes are really tough to draw. For reasonable values of n, n-cubes make it easy to visualize certain coding and logic minimization problems. For example, the problem of designing an n-bit Gray code is equivalent to finding a path along the edges of an n-cube, a path that visits each vertex exactly once. The paths for 3- and 4-bit Gray codes are shown in Figure 2-9.
1110 1111
010
000
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0 1 00 01 1-cube 2-cube 1110 1111 110 111 0110 1011 0111 1010 011 0010 1100 0011 1101 1000 100 101 0100 0101 1001 001 0000 0001 3-cube 4-cube
Figure 2-8 n-cubes for n = 1, 2, 3, and 4.
n-cube
110
111
0110
1011
0111
1010
011
0010
1100
0011
1101
Figure 2-9 Traversing n-cubes in Gray-code order: (a) 3-cube; (b) 4-cube.
1000
100
101
0100
0101
1001
001
0000
0001
(a)
(b)
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distance Hamming distance
m-subcube
dont-care
error failure temporary failure permanent failure
error model independent error model single error multiple error
error-detecting code noncode word
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Cubes also provide a geometrical interpretation for the concept of distance, also called Hamming distance. The distance between two n-bit strings is the number of bit positions in which they differ. In terms of an n-cube, the distance is the minimum length of a path between the two corresponding vertices. Two adjacent vertices have distance 1; vertices 001 and 100 in the 3-cube have distance 2. The concept of distance is crucial in the design and understanding of error-detecting codes, discussed in the next section. An m-subcube of an n-cube is a set of 2m vertices in which n m of the bits have the same value at each vertex, and the remaining m bits take on all 2m combinations. For example, the vertices (000, 010, 100, 110) form a 2-subcube of the 3-cube. This subcube can also be denoted by a single string, xx0, where x denotes that a particular bit is a dont-care; any vertex whose bits match in the non-x positions belongs to this subcube. The concept of subcubes is particularly useful in visualizing algorithms that minimize the cost of combinational logic functions, as well show in Section 4.4.
An error in a digital system is the corruption of data from its correct value to some other value. An error is caused by a physical failure. Failures can be either temporary or permanent. For example, a cosmic ray or alpha particle can cause a temporary failure of a memory circuit, changing the value of a bit stored in it. Letting a circuit get too hot or zapping it with static electricity can cause a permanent failure, so that it never works correctly again. The effects of failures on data are predicted by error models. The simplest error model, which we consider here, is called the independent error model. In this model, a single physical failure is assumed to affect only a single bit of data; the corrupted data is said to contain a single error. Multiple failures may cause multiple errorstwo or more bits in errorbut multiple errors are normally assumed to be less likely than single errors. 2.15.1 Error-Detecting Codes Recall from our definitions in Section 2.10 that a code that uses n-bit strings need not contain 2n valid code words; this is certainly the case for the codes that we now consider. An error-detecting code has the property that corrupting or garbling a code word will likely produce a bit string that is not a code word (a noncode word). A system that uses an error-detecting code generates, transmits, and stores only code words. Thus, errors in a bit string can be detected by a simple ruleif the bit string is a code word, it is assumed to be correct; if it is a noncode word, it contains an error. An n-bit code and its error-detecting properties under the independent error model are easily explained in terms of an n-cube. A code is simply a subset
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110 111
Codes for Detecting and Correcting Errors
110 111
55
of the vertices of the n-cube. In order for the code to detect all single errors, no code-word vertex can be immediately adjacent to another code-word vertex. For example, Figure 2-10(a) shows a 3-bit code with five code words. Code word 111 is immediately adjacent to code words 110, 011 and 101. Since a single failure could change 111 to 110, 011 or 101 this code does not detect all single errors. If we make 111 a noncode word, we obtain a code that does have the single-error-detecting property, as shown in (b). No single error can change one code word into another. The ability of a code to detect single errors can be stated in terms of the concept of distance introduced in the preceding section: A code detects all single errors if the minimum distance between all possible pairs of code words is 2.
In general, we need n + 1 bits to construct a single-error-detecting code with 2n code words. The first n bits of a code word, called information bits, may be any of the 2 n n-bit strings. To obtain a minimum-distance-2 code, we add one more bit, called a parity bit, that is set to 0 if there are an even number of 1s among the information bits, and to 1 otherwise. This is illustrated in the first two columns of Table 2-13 for a code with three information bits. A valid n+1-bit code word has an even number of 1s, and this code is called an even-parity code.
Information Bits Even-parity Code Odd-parity Code
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010 011 010 011 = code word = noncode word 100 101 100 101 000 001 000 001 (a) (b)
Figure 2-10 Code words in two different 3-bit codes: (a) minimum distance = 1, does not detect all single errors; (b) minimum distance = 2, detects all single errors.
minimum distance
information bit parity bit
even-parity code
Ta b l e 2 - 1 3 Distance-2 codes with three information bits.
000 001 010 011 100 101 110 111
000 0 001 1 010 1 011 0 100 1 101 0 110 0 111 1
000 1 001 0 010 0 011 1 100 0 101 1 110 1 111 0
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odd-parity code 1-bit parity code
check bits
Figure 2-11 Some code words and noncode words in a 7-bit, distance-3 code.
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0001010 1011000 1001011 0001001 1011011 0011001 0001011 0001111 1011001 0101011 0000011 1011101 1001001 0011011 1010011 1010001 0010010 1010000 1010010 1010110 = code word = noncode word 1110010 1011010 1000010
We can also construct a code in which the total number of 1s in a valid n+1-bit code word is odd; this is called an odd-parity code and is shown in the third column of the table. These codes are also sometimes called 1-bit parity codes, since they each use a single parity bit. The 1-bit parity codes do not detect 2-bit errors, since changing two bits does not affect the parity. However, the codes can detect errors in any odd number of bits. For example, if three bits in a code word are changed, then the resulting word has the wrong parity and is a noncode word. This doesnt help us much, though. Under the independent error model, 3-bit errors are much less likely than 2-bit errors, which are not detectable. Thus, practically speaking, the 1-bit parity codes error detection capability stops after 1-bit errors. Other codes, with minimum distance greater than 2, can be used to detect multiple errors. 2.15.2 Error-Correcting and Multiple-Error-Detecting Codes By using more than one parity bit, or check bits, according to some well-chosen rules, we can create a code whose minimum distance is greater than 2. Before showing how this can be done, lets look at how such a code can be used to correct single errors or detect multiple errors. Suppose that a code has a minimum distance of 3. Figure 2-11 shows a fragment of the n-cube for such a code. As shown, there are at least two noncode words between each pair of code words. Now suppose we transmit code words
1111001
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and assume that failures affect at most one bit of each received code word. Then a received noncode word with a 1-bit error will be closer to the originally transmitted code word than to any other code word. Therefore, when we receive a noncode word, we can correct the error by changing the received noncode word to the nearest code word, as indicated by the arrows in the figure. Deciding which code word was originally transmitted to produce a received word is called decoding, and the hardware that does this is an error-correcting decoder. A code that is used to correct errors is called an error-correcting code. In general, if a code has minimum distance 2c + 1, it can be used to correct errors that affect up to c bits (c = 1 in the preceding example). If a codes minimum distance is 2c + d + 1, it can be used to correct errors in up to c bits and to detect errors in up to d additional bits. For example, Figure 2-12(a) shows a fragment of the n-cube for a code with minimum distance 4 (c = 1, d = 1). Single-bit errors that produce noncode words 00101010 and 11010011 can be corrected. However, an error that produces 10100011 cannot be corrected, because no single-bit error can produce this noncode word, and either of two 2-bit errors could have produced it. So the code can detect a 2-bit error, but it cannot correct it. When a noncode word is received, we dont know which code word was originally transmitted; we only know which code word is closest to what weve received. Thus, as shown in Figure 2-12(b), a 3-bit error may be corrected to the wrong value. The possibility of making this kind of mistake may be acceptable if 3-bit errors are very unlikely to occur. On the other hand, if we are concerned about 3-bit errors, we can change the decoding policy for the code. Instead of trying to correct errors, we just flag all noncode words as uncorrectable errors. Thus, as shown in (c), we can use the same distance-4 code to detect up to 3-bit errors but correct no errors (c = 0, d = 3).
2.15.3 Hamming Codes In 1950, R. W. Hamming described a general method for constructing codes with a minimum distance of 3, now called Hamming codes. For any value of i, his method yields a 2 i1-bit code with i check bits and 2 i 1 i information bits. Distance-3 codes with a smaller number of information bits are obtained by deleting information bits from a Hamming code with a larger number of bits. The bit positions in a Hamming code word can be numbered from 1 through 2 i 1. In this case, any position whose number is a power of 2 is a check bit, and the remaining positions are information bits. Each check bit is grouped with a subset of the information bits, as specified by a parity-check matrix. As
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error correction decoding decoder Hamming code parity-check matrix DECISIONS, DECISIONS The names decoding and decoder make sense, since they are just distance-1 perturbations of deciding and decider. Copying Prohibited
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detectable 2-bit errors
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(a)
Figure 2-12 Some code words and noncode words in an 8-bit, distance-4 code: (a) correcting 1-bit and detecting 2-bit errors; (b) incorrectly correcting a 3-bit error; (c) correcting no errors but detecting up to 3-bit errors.
00101010
11010011
10100011
00101011
11000011
00100011
11100011
detectable 2-bit errors
correctable 1-bit errors
(b)
00101010
11010011
10100011
00101011
00100011
11100011
11000011
3-bit error looks like a 1-bit error
(c)
00101011
11000011
all 1- to 3-bit errors are detectable
shown in Figure 2-13(a), each check bit is grouped with the information positions whose numbers have a 1 in the same bit when expressed in binary. For example, check bit 2 (010) is grouped with information bits 3 (011), 6 (110), and 7 (111). For a given combination of information-bit values, each check bit is chosen to produce even parity, that is, so the total number of 1s in its group is even.
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(a) Bit position 4
Codes for Detecting and Correcting Errors
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Group name
(b)
Group name
Traditionally, the bit positions of a parity-check matrix and the resulting code words are rearranged so that all of the check bits are on the right, as in Figure 2-13(b). The first two columns of Table 2-14 list the resulting code words. We can prove that the minimum distance of a Hamming code is 3 by proving that at least a 3-bit change must be made to a code word to obtain another code word. That is, well prove that a 1-bit or 2-bit change in a code word yields a noncode word. If we change one bit of a code word, in position j, then we change the parity of every group that contains position j. Since every information bit is contained in at least one group, at least one group has incorrect parity, and the result is a noncode word. What happens if we change two bits, in positions j and k? Parity groups that contain both positions j and k will still have correct parity, since parity is unaffected when an even number of bits are changed. However, since j and k are different, their binary representations differ in at least one bit, corresponding to one of the parity groups. This group has only one bit changed, resulting in incorrect parity and a noncode word. If you understand this proof, you should also see how the position numbering rules for constructing a Hamming code are a simple consequence of the proof. For the first part of the proof (1-bit errors), we required that the position numbers be nonzero. And for the second part (2-bit errors), we required that no
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7 6 5 3 2 1 C B A Groups Check bits 7 6 5 Bit position 3 4 2 1 C B A Groups Information bits Check bits
Figure 2-13 Parity-check matrices for 7-bit Hamming codes: (a) with bit positions in numerical order; (b) with check bits and information bits separated.
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error-correcting decoder
syndrome
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Minimum-distance-3 code Minimum-distance-4 code Information Bits Parity Bits Information Bits
Ta b l e 2 - 1 4 Code words in distance-3 and distance-4 Hamming codes with four information bits.
Parity Bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
000 011 101 110 110 101 011 000 111 100 010 001 001 010 100 111
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 0111 1011 1100 1101 1010 0110 0001 1110 1001 0101 0010 0011 0100 1000 1111
two positions have the same number. Thus, with an i-bit position number, you can construct a Hamming code with up to 2 i 1 bit positions. The proof also suggests how we can design an error-correcting decoder for a received Hamming code word. First, we check all of the parity groups; if all have even parity, then the received word is assumed to be correct. If one or more groups have odd parity, then a single error is assumed to have occurred. The pattern of groups that have odd parity (called the syndrome) must match one of the columns in the parity-check matrix; the corresponding bit position is assumed to contain the wrong value and is complemented. For example, using the code defined by Figure 2-13(b), suppose we receive the word 0101011. Groups B and C have odd parity, corresponding to position 6 of the parity-check matrix (the
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syndrome is 110, or 6). By complementing the bit in position 6 of the received word, we determine that the correct word is 0001011. A distance-3 Hamming code can easily be modified to increase its minimum distance to 4. We simply add one more check bit, chosen so that the parity of all the bits, including the new one, is even. As in the 1-bit even-parity code, this bit ensures that all errors affecting an odd number of bits are detectable. In particular, any 3-bit error is detectable. We already showed that 1- and 2-bit errors are detected by the other parity bits, so the minimum distance of the modified code must be 4. Distance-3 and distance-4 Hamming codes are commonly used to detect and correct errors in computer memory systems, especially in large mainframe computers where memory circuits account for the bulk of the systems failures. These codes are especially attractive for very wide memory words, since the required number of parity bits grows slowly with the width of the memory word, as shown in Table 2-15.
Ta b l e 2 - 1 5 Word sizes of distance-3 and distance-4 Hamming codes.
Minimum-distance-3 Codes Parity Bits Total Bits
Information Bits
2.15.4 CRC Codes Beyond Hamming codes, many other error-detecting and -correcting codes have been developed. The most important codes, which happen to include Hamming codes, are the cyclic redundancy check (CRC) codes. A rich set of knowledge has been developed for these codes, focused both on their error detecting and correcting properties and on the design of inexpensive encoders and decoders for them (see References). Two important applications of CRC codes are in disk drives and in data networks. In a disk drive, each block of data (typically 512 bytes) is protected by a CRC code, so that errors within a block can be detected and, in some drives, corrected. In a data network, each packet of data ends with check bits in a CRC
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Minimum-distance-4 Codes Parity Bits Total Bits
1
2
3
3
4
4
3
7
4
8
11 26 57
4 5 6
15 31 63
5 6 7
16 32 64
120
7
127
8
128
cyclic redundancy check (CRC) code
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two-dimensional code
product code
Figure 2-14 Two-dimensional codes: (a) general structure; (b) using even parity for both the row and column codes to obtain minimum distance 4; (c) typical pattern of an undetectable error.
(b)
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(a) information bits checks on rows checks on columns checks on checks Columns are code words in Ccol (c) information bits Rows are code words in 1-bit even-parity code No effect on row parity Columns are code words in 1-bit even-parity code No effect on column parity
code. The CRC codes for both applications were selected because of their bursterror detecting properties. In addition to single-bit errors, they can detect multibit errors that are clustered together within the disk block or packet. Such errors are more likely than errors of randomly distributed bits, because of the likely physical causes of errors in the two applicationssurface defects in disc drives and noise bursts in communication links.
2.15.5 Two-Dimensional Codes Another way to obtain a code with large minimum distance is to construct a twodimensional code, as illustrated in Figure 2-14(a). The information bits are conceptually arranged in a two-dimensional array, and parity bits are provided to check both the rows and the columns. A code Crow with minimum distance drow is used for the rows, and a possibly different code Ccol with minimum distance dcol is used for the columns. That is, the row-parity bits are selected so that each row is a code word in Crow and the column-parity bits are selected so that each column is a code word in Ccol. (The corner parity bits can be chosen according to either code.) The minimum distance of the two-dimensional code is the product of drow and dcol; in fact, two-dimensional codes are sometimes called product codes.
Rows are code words in Crow
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As shown in Figure 2-14(b), the simplest two-dimensional code uses 1-bit even-parity codes for the rows and columns, and has a minimum distance of 2 2, or 4. You can easily prove that the minimum distance is 4 by convincing yourself that any pattern of one, two, or three bits in error causes incorrect parity of a row or a column or both. In order to obtain an undetectable error, at least four bits must be changed in a rectangular pattern as in (c). The error detecting and correcting procedures for this code are straightforward. Assume we are reading information one row at a time. As we read each row, we check its row code. If an error is detected in a row, we cant tell which bit is wrong from the row check alone. However, assuming only one row is bad, we can reconstruct it by forming the bit-by-bit Exclusive OR of the columns, omitting the bad row, but including the column-check row. To obtain an even larger minimum distance, a distance-3 or -4 Hamming code can be used for the row or column code or both. It is also possible to construct a code in three or more dimensions, with minimum distance equal to the product of the minimum distances in each dimension. An important application of two-dimensional codes is in RAID storage systems. RAID stands for redundant array of inexpensive disks. In this scheme, n+1 identical disk drives are used to store n disks worth of data. For example, eight 8-Gigabyte drives could be use to store 64 Gigabytes of nonredundant data, and a ninth 8-gigabyte drive would be used to store checking information. Figure 2-15 shows the general scheme of a two-dimensional code for a RAID system; each disk drive is considered to be a row in the code. Each drive stores m blocks of data, where a block typically contains 512 bytes. For example, an 8-gigabyte drive would store about 16 million blocks. As shown in the figure, each block includes its own check bits in a CRC code, to detect errors within that block. The first n drives store the nonredundant data. Each block in drive n+1
Disk 1 Disk 2 Disk 3 Disk 4 Disk 5 Disk 6 ...
Disk n
Disk n+1
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RAID
Block number 1 2 3 4 5 6 7 8 9 10 11 12 . . .
m
Figure 2-15 Structure of errorcorrecting code for a RAID system.
information blocks
...
Data bytes 123
4
5
6
7
... ...
512
CRC
...
One block
...
check blocks
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checksum checksum code
ones-complement checksum code
unidirectional error
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stores parity bits for the corresponding blocks in the first n drives. That is, each bit i in drive n+1 block b is chosen so that there are an even number of 1s in block b bit position i across all the drives. In operation, errors in the information blocks are detected by the CRC code. Whenever an error is detected in a block on one of the drives, the correct contents of that block can be constructed simply by computing the parity of the corresponding blocks in all the other drives, including drive n+1. Although this requires n extra disk read operations, its better than losing your data! Write operations require extra disk accesses as well, to update the corresponding check block when an information block is written (see Exercise 2.46). Since disk writes are much less frequent than reads in typical applications, this overhead usually is not a problem. 2.15.6 Checksum Codes The parity-checking operation that weve used in the previous subsections is essentially modulo-2 addition of bitsthe sum modulo 2 of a group of bits is 0 if the number of 1s in the group is even, and 1 if it is odd. The technique of modular addition can be extended to other bases besides 2 to form check digits. For example, a computer stores information as a set of 8-bit bytes. Each byte may be considered to have a decimal value from 0 to 255. Therefore, we can use modulo-256 addition to check the bytes. We form a single check byte, called a checksum, that is the sum modulo 256 of all the information bytes. The resulting checksum code can detect any single byte error, since such an error will cause a recomputed sum of bytes to disagree with the checksum. Checksum codes can also use a different modulus of addition. In particular, checksum codes using modulo-255, ones-complement addition are important because of their special computational and error detecting properties, and because they are used to check packet headers in the ubiquitous Internet Protocol (IP) (see References).
2.15.7 m-out-of-n Codes The 1-out-of-n and m-out-of-n codes that we introduced in Section 2.13 have a minimum distance of 2, since changing only one bit changes the total number of 1s in a code word and therefore produces a noncode word. These codes have another useful error-detecting propertythey detect unidirectional multiple errors. In a unidirectional error, all of the erroneous bits change in the same direction (0s change to 1s, or vice versa). This property is very useful in systems where the predominant error mechanism tends to change all bits in the same direction.
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CLOCK
SERDATA
bit number
2.16 Codes for Serial Data Transmission and Storage
2.16.1 Parallel and Serial Data Most computers and other digital systems transmit and store data in a parallel format. In parallel data transmission, a separate signal line is provided for each bit of a data word. In parallel data storage, all of the bits of a data word can be written or read simultaneously. Parallel formats are not cost-effective for some applications. For example, parallel transmission of data bytes over the telephone network would require eight phone lines, and parallel storage of data bytes on a magnetic disk would require a disk drive with eight separate read/write heads. Serial formats allow data to be transmitted or stored one bit at a time, reducing system cost in many applications. Figure 2-16 illustrates some of the basic ideas in serial data transmission. A repetitive clock signal, named CLOCK in the figure, defines the rate at which bits are transmitted, one bit per clock cycle. Thus, the bit rate in bits per second (bps) numerically equals the clock frequency in cycles per second (hertz, or Hz). The reciprocal of the bit rate is called the bit time and numerically equals the clock period in seconds (s). This amount of time is reserved on the serial data line (named SERDATA in the figure) for each bit that is transmitted. The time occupied by each bit is sometimes called a bit cell. The format of the actual signal that appears on the line during each bit cell depends on the line code. In the simplest line code, called Non-Return-to-Zero (NRZ), a 1 is transmitted by placing a 1 on the line for the entire bit cell, and a 0 is transmitted as a 0. However, more complex line codes have other rules, as discussed in the next subsection.
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bit time bit cell bit cell bit cell bit cell bit cell bit cell bit cell bit cell bit cell bit cell SYNC 1 2 3 4 5 6 7 8 1 2
Figure 2-16 Basic concepts for serial data transmission.
parallel data
serial data
bit rate, bps bit time
bit cell line code Non-Return-to-Zero (NRZ)
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synchronization signal
Figure 2-17 Commonly used line codes for serial data.
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time bit value NRZ 0 1 1 1 0 0 1 0 NRZI RZ BPRZ Manchester
Regardless of the line code, a serial data transmission or storage system needs some way of identifying the significance of each bit in the serial stream. For example, suppose that 8-bit bytes are transmitted serially. How can we tell which is the first bit of each byte? A synchronization signal, named SYNC in Figure 2-16, provides the necessary information; it is 1 for the first bit of each byte. Evidently, we need a minimum of three signals to recover a serial data stream: a clock to define the bit cells, a synchronization signal to define the word boundaries, and the serial data itself. In some applications, like the interconnection of modules in a computer or telecommunications system, a separate wire is used for each of these signals, since reducing the number of wires per connection from n to three is savings enough. Well give an example of a 3-wire serial data system in Section 8.5.4. In many applications, the cost of having three separate signals is still too high (e.g., three phone lines, three read/write heads). Such systems typically combine all three signals into a single serial data stream and use sophisticated analog and digital circuits to recover the clock and synchronization information from the data stream. *2.16.2 Serial Line Codes The most commonly used line codes for serial data are illustrated in Figure 2-17. In the NRZ code, each bit value is sent on the line for the entire bit cell. This is the simplest and most reliable coding scheme for short distance transmission. However, it generally requires a clock signal to be sent along with the data to define the bit cells. Otherwise, it is not possible for the receiver to determine how many 0s or 1s are represented by a continuous 0 or 1 level. For example, without a clock to define the bit cells, the NRZ waveform in Figure 2-17 might be erroneously interpreted as 01010.
Copyright 1999 by John F. Wakerly
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A digital phase-locked loop (DPLL) is an analog/digital circuit that can be used to recover a clock signal from a serial data stream. The DPLL works only if the serial data stream contains enough 0-to-1 and 1-to-0 transitions to give the DPLL hints about when the original clock transitions took place. With NRZcoded data, the DPLL works only if the data does not contain any long, continuous streams of 1s or 0s. Some serial transmission and storage media are transition sensitive; they cannot transmit or store absolute 0 or 1 levels, only transitions between two discrete levels. For example, a magnetic disk or tape stores information by changing the polarity of the mediums magnetization in regions corresponding to the stored bits. When the information is recovered, it is not feasible to determine the absolute magnetization polarity of a region, only that the polarity changes between one region and the next. Data stored in NRZ format on transition-sensitive media cannot be recovered unambiguously; the data in Figure 2-17 might be interpreted as 01110010 or 10001101. The Non-Return-to-Zero Invert-on-1s (NRZI) code overcomes this limitation by sending a 1 as the opposite of the level that was sent during the previous bit cell, and a 0 as the same level. A DPLL can recover the clock from NRZI-coded data as long as the data does not contain any long, continuous streams of 0s. The Return-to-Zero (RZ) code is similar to NRZ except that, for a 1 bit, the 1 level is transmitted only for a fraction of the bit time, usually 1/2. With this code, data patterns that contain a lot of 1s create lots of transitions for a DPLL to use to recover the clock. However, as in the other line codes, a string of 0s has no transitions, and a long string of 0s makes clock recovery impossible. Another requirement of some transmission media, such as high-speed fiber-optic links, is that the serial data stream be DC balanced . That is, it must have an equal number of 1s and 0s; any long-term DC component in the stream (created by have a lot more 1s than 0s or vice versa) creates a bias at the receiver that reduces its ability to distinguish reliably between 1s and 0s. Ordinarily, NRZ, NRZI or RZ data has no guarantee of DC balance; theres nothing to prevent a user data stream from having a long string of words with more than 1s than 0s or vice versa. However, DC balance can still be achieved using a few extra bits to code the user data in a balanced code, in which each code word has an equal number of 1s and 0s, and then sending these code words in NRZ format. For example, in Section 2.13 we introduced the 8B10B code, which codes 8 bits of user data into 10 bits in a mostly 5-out-of-10 code. Recall that there are only 252 5-out-of-10 code words, but there are another 4 = 210 4-out-of-10 10 code words and an equal number of 6-out-of-10 code words. Of course, these code words arent quite DC balanced. The 8B10B code solves this problem by associating with each 8-bit value to be encoded a pair of unbalanced code words, one 4-out-of-10 (light) and the other 6-out-of-10 (heavy). The coder also
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digital phase-locked loop (DPLL) transition-sensitive media Return-to-Zero (RZ) DC balance balanced code
Non-Return-to-Zero Invert-on-1s (NRZI)
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running disparity
Bipolar Return-to-Zero (BPRZ) Alternate Mark Inversion (AMI)
zero-code suppression
Manchester diphase
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KILO-, MEGA-, GIGA-, TERACopyright 1999 by John F. Wakerly
The prefixes K (kilo-), M (mega-), G (giga-), and T (tera-) mean 103, 106, 109, and 1012 , respectively, when referring to bps, hertz, ohms, watts, and most other engineering quantities. However, when referring to memory sizes, the prefixes mean 2 10, 220 , 230, and 2 40. Historically, the prefixes were co-opted for this purpose because memory sizes are normally powers of 2, and 210 (1024) is very close to 1000, Now, when somebody offers you 50 kilobucks a year for your first engineering job, its up to you to negotiate what the prefix means!
keeps track of the running disparity, a single bit of information indicating whether the last unbalanced code word that it transmitted was heavy or light. When it comes time to transmit another unbalanced code word, the coder selects the one of the pair with the opposite weight. This simple trick makes available 252 + 210 = 462 code words for the 8B10B to encode 8 bits of user data. Some of the extra code words are used to conveniently encode non-data conditions on the serial line, such as IDLE, SYNC , and ERROR. Not all the unbalanced code words are used. Also, some of the balanced code words, such as 0000011111, are not used either, in favor of unbalanced pairs that contain more transitions. All of the preceding codes transmit or store only two signal levels. The Bipolar Return-to-Zero (BPRZ) code transmits three signal levels: +1, 0, and 1. The code is like RZ except that 1s are alternately transmitted as +1 and 1; for this reason, the code is also known as Alternate Mark Inversion (AMI). The big advantage of BPRZ over RZ is that its DC balanced. This makes it possible to send BPRZ streams over transmission media that cannot tolerate a DC component, such as transformer-coupled phone lines. In fact, the BPRZ code has been used in T1 digital telephone links for decades, where analog speech signals are carried as streams of 8000 8-bit digital samples per second that are transmitted in BPRZ format on 64 Kbps serial channels. As with RZ, it is possible to recover a clock signal from a BPRZ stream as long as there arent too many 0s in a row. Although TPC (The Phone Company) has no control over what you say (at least, not yet), they still have a simple way of limiting runs of 0s. If one of the 8-bit bytes that results from sampling your analog speech pattern is all 0s, they simply change second-least significant bit to 1! This is called zero-code suppression and Ill bet you never noticed it. And this is also why, in many data applications of T1 links, you get only 56 Kbps of usable data per 64 Kbps channel; the LSB of each byte is always set to 1 to prevent zero-code suppression from changing the other bits. The last code in Figure 2-17 is called Manchester or diphase code. The major strength of this code is that, regardless of the transmitted data pattern, it provides at least one transition per bit cell, making it very easy to recover the clock. As shown in the figure, a 0 is encoded as a 0-to-1 transition in the middle
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of the bit cell, and a 1 is encoded as a 1-to-0 transition. The Manchester codes major strength is also its major weakness. Since it has more transitions per bit cell than other codes, it also requires more media bandwidth to transmit a given bit rate. Bandwidth is not a problem in coaxial cable, however, which was used in the original Ethernet local area networks to carry Manchester-coded serial data at the rate of 10 Mbps (megabits per second).
References
The presentation in the first nine sections of this chapter is based on Chapter 4 of Microcomputer Architecture and Programming, by John F. Wakerly (Wiley, 1981). Precise, thorough, and entertaining discussions of these topics can also be found in Donald E. Knuths Seminumerical Algorithms, 3rd edition (Addison-Wesley, 1997). Mathematically inclined readers will find Knuths analysis of the properties of number systems and arithmetic to be excellent, and all readers should enjoy the insights and history sprinkled throughout the text. Descriptions of digital logic circuits for arithmetic operations, as well as an introduction to properties of various number systems, appear in Computer Arithmetic by Kai Hwang (Wiley, 1979). Decimal Computation by Hermann Schmid (Wiley, 1974) contains a thorough description of techniques for BCD arithmetic. An introduction to algorithms for binary multiplication and division and to floating-point arithmetic appears in Microcomputer Architecture and Programming: The 68000 Family by John F. Wakerly (Wiley, 1989). A more thorough discussion of arithmetic techniques and floating-point number systems can be found in Introduction to Arithmetic for Digital Systems Designers by Shlomo Waser and Michael J. Flynn (Holt, Rinehart and Winston, 1982). CRC codes are based on the theory of finite fields, which was developed by French mathematician variste Galois (18111832) shortly before he was killed in a duel with a political opponent. The classic book on error-detecting and error-correcting codes is Error-Correcting Codes by W. W. Peterson and E. J. Weldon, Jr. (MIT Press, 1972, 2nd ed.); however, this book is recommended only for mathematically sophisticated readers. A more accessible introduction can be found in Error Control Coding: Fundamentals and Applications by S. Lin and D. J. Costello, Jr. (Prentice Hall, 1983). Another recent, communication-oriented introduction to coding theory can be found in Error-Control
Copyright 1999 by John F. Wakerly
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ABOUT TPC Watch the 1967 James Coburn movie, The Presidents Analyst, for an amusing view of TPC. With the growing pervasiveness of digital technology and cheap wireless communications, the concept of universal, personal connectivity to the phone network presented in the movies conclusion has become much less far-fetched. finite fields Copying Prohibited
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Drill Problems
2.1 Perform the following number system conversions: (a) 11010112 = ?16 (c) 101101112 = ?16 (g) 110110012 = ?8 (d) 67.248 = ?2 (b) 1740038 = ?2 (f) F3A516 = ?2 (e) 10100.11012 = ?16 (h) AB3D 16 = ?2 (i) 101111.01112 = ?8 (a) 10238 = ?2 = ?16 (j) 15C.3816 = ?2 2.2 Convert the following octal numbers into binary and hexadecimal: (b) 7613028 = ?2 = ?16 (c) 1634178 = ?2 = ?16 (d) 5522738 = ?2 = ?16 (e) 5436.158 = ?2 = ?16 (a) 102316 = ?2 = ?8 (f) 13705.2078 = ?2 = ?16 (b) 7E6A16 = ?2 = ?8 (d) C35016 = ?2 = ?8 2.3 Convert the following hexadecimal numbers into binary and octal: (c) ABCD 16 = ?2 = ?8 (e) 9E36.7A16 = ?2 = ?8 (f) DEAD.BEEF16 = ?2 = ?8 Copyright 1999 by John F. Wakerly
Techniques for Digital Communication by A. M. Michelson and A. H. Levesque (Wiley-Interscience, 1985). Hardware applications of codes in computer systems are discussed in Error-Detecting Codes, Self-Checking Circuits, and Applications by John F. Wakerly (Elsevier/North-Holland, 1978). As shown in the above reference by Wakerly, ones-complement checksum codes have the ability to detect long bursts of unidirectional errors; this is useful in communication channels where errors all tend to be in the same direction. The special computational properties of these codes also make them quite amenable to efficient checksum calculation by software programs, important for their use in the Internet Protocol; see RFC-1071 and RFC-1141. An introduction to coding techniques for serial data transmission, including mathematical analysis of the performance and bandwidth requirements of several codes, appears in Introduction to Communications Engineering by R. M. Gagliardi (Wiley-Interscience, 1988, 2nd ed.). A nice introduction to the serial codes used in magnetic disks and tapes is given in Computer Storage Systems and Technology by Richard Matick (Wiley-Interscience, 1977). The structure of the 8B10B code and the rationale behind it is explained nicely in the original IBM patent by Peter Franaszek and Albert Widmer, U.S. patent number 4,486,739 (1984). This and almost all U.S. patents issued after 1971 can be found on the web at www.patents.ibm.com. When youre done reading Franaszek, for a good time do a boolean search for inventor wakerly.
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2.4 2.5
2.6
2.7
2.8 2.9
2.10 Add the following pairs of hexadecimal numbers: (a) + 1372 4631 (b) + 4F1A5 B8D5 (c)
2.11
Write the 8-bit signed-magnitude, twos-complement, and ones-complement representations for each of these decimal numbers: +18, +115, +79, 49, 3, 100. 2.12 Indicate whether or not overflow occurs when adding the following 8-bit twoscomplement numbers: (a) 11010100 + 10101011 (b) 10111001 + 11010110 (c) 01011101 + 00100001 (d) 00100110 + 01011010
2.13 How many errors can be detected by a code with minimum distance d? 2.14 What is the minimum number of parity bits required to obtain a distance-4, twodimensional code with n information bits?
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What are the octal values of the four 8-bit bytes in the 32-bit number with octal representation 123456701238? Convert the following numbers into decimal: (a) 11010112 = ?10 (b) 1740038 = ?10 (d) 67.248 = ?10 (f) F3A516 = ?10 (c) 101101112 = ?10 (g) 120103 = ?10 (i) 71568 = ?10 (e) 10100.11012 = ?10 (h) AB3D 16 = ?10 (j) 15C.3816 = ?10 Perform the following number system conversions: (a) 12510 = ?2 (c) 20910 = ?2 (e) 13210 = ?2 (g) 72710 = ?5 (b) 348910 = ?8 (d) 971410 = ?8 (f) 2385110 = ?16 (h) 5719010 = ?16 (j) 6511310 = ?16 (i) 143510 = ?8 Add the following pairs of binary numbers, showing all carries: (a) 110101 + 11001 (b) 101110 + 100101 (c) 11011101 + 1100011 (d) 1110010 + 1101101 Repeat Drill 2.7 using subtraction instead of addition, and showing borrows instead of carries. Add the following pairs of octal numbers: (a) + 1372 4631 (b) 47135 + 5125 (c) 175214 + 152405 (d) 110321 + 56573 F35B + 27E6 (d) 1B90F + C44E Copying Prohibited
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Exercises
(a) 1234 + 5432 = 6666 (c) 33/3 = 11 (e) 302/20 = 12.1 (b) 41 / 3 = 13 (d) 23+44+14+32 = 223 (f) 14 = 5 5x2 50x + 125 = 0 [ x + y ] = ( [ x ] + [y ] ) modulo 2n Copyright 1999 by John F. Wakerly
2.15 Heres a problem to whet your appetite. What is the hexadecimal equivalent of 6145310? 2.16 Each of the following arithmetic operations is correct in at least one number system. Determine possible radices of the numbers in each operation.
2.17 The first expedition to Mars found only the ruins of a civilization. From the artifacts and pictures, the explorers deduced that the creatures who produced this civilization were four-legged beings with a tentacle that branched out at the end with a number of grasping fingers. After much study, the explorers were able to translate Martian mathematics. They found the following equation:
with the indicated solutions x = 5 and x = 8. The value x = 5 seemed legitimate enough, but x = 8 required some explanation. Then the explorers reflected on the way in which Earths number system developed, and found evidence that the Martian system had a similar history. How many fingers would you say the Martians had? (From The Bent of Tau Beta Pi , February, 1956.)
2.18 Suppose a 4n-bit number B is represented by an n-digit hexadecimal number H. Prove that the twos complement of B is represented by the 16s complement of H. Make and prove true a similar statement for octal representation. 2.19 Repeat Exercise 2.18 using the ones complement of B and the 15s complement of H. 2.20 Given an integer x in the range 2n1 x 2n1 1, we define [ x ] to be the twoscomplement representation of x, expressed as a positive number: [ x ] = x if x 0 and [x] = 2n | x | if x < 0, where | x | is the absolute value of x. Let y be another integer in the same range as x. Prove that the twos-complement addition rules given in Section 2.6 are correct by proving that the following equation is always true:
(Hints: Consider four cases based on the signs of x and y. Without loss of generality, you may assume that | x | | y |.)
2.21 Repeat Exercise 2.20 using appropriate expressions and rules for ones-complement addition. 2.22 State an overflow rule for addition of twos-complement numbers in terms of counting operations in the modular representation of Figure 2-3. 2.23 Show that a twos-complement number can be converted to a representation with more bits by sign extension. That is, given an n-bit twos-complement number X, show that the m-bit twos-complement representation of X, where m > n, can be
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2.24
2.25 2.26
2.27
2.28
2.29
2.30
2.31 2.32 2.33
2.34
2.35
2.36 2.37
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obtained by appending m n copies of Xs sign bit to the left of the n-bit representation of X. Show that a twos-complement number can be converted to a representation with fewer bits by removing higher-order bits. That is, given an n-bit twos-complement number X, show that the m-bit twos-complement number Y obtained by discarding the d leftmost bits of X represents the same number as X if and only if the discarded bits all equal the sign bit of Y. Why is the punctuation of twos complement and ones complement inconsistent? (See the first two citations in the References.) A n-bit binary adder can be used to perform an n-bit unsigned subtraction operation X Y, by performing the operation X + Y + 1, where X and Y are n-bit unsigned numbers and Y represents the bit-by-bit complement of Y. Demonstrate this fact as follows. First, prove that ( X Y) = (X + Y + 1) 2n. Second, prove that the carry out of the n-bit adder is the opposite of the borrow from the n-bit subtraction. That is, show that the operation X Y produces a borrow out of the MSB position if and only if the operation X + Y + 1 does not produce a carry out of the MSB position. In most cases, the product of two n-bit twos-complement numbers requires fewer than 2n bits to represent it. In fact, there is only one case in which 2n bits are neededfind it. Prove that a twos-complement number can be multiplied by 2 by shifting it one bit position to the left, with a carry of 0 into the least significant bit position and disregarding any carry out of the most significant bit position, assuming no overflow. State the rule for detecting overflow. State and prove correct a technique similar to the one described in Exercise 2.28, for multiplying a ones-complement number by 2. Show how to subtract BCD numbers, by stating the rules for generating borrows and applying a correction factor. Show how your rules apply to each of the following subtractions: 9 3, 5 7, 4 9, 1 8. How many different 3-bit binary state encodings are possible for the traffic-light controller of Table 2-12? List all of the bad boundaries in the mechanical encoding disc of Figure 2-5, where an incorrect position may be sensed. As a function of n, how many bad boundaries are there in a mechanical encoding disc that uses an n-bit binary code? On-board altitude transponders on commercial and private aircraft use Gray code to encode the altitude readings that are transmitted to air traffic controllers. Why? An incandescent light bulb is stressed every time it is turned on, so in some applications the lifetime of the bulb is limited by the number of on/off cycles rather than the total time it is illuminated. Use your knowledge of codes to suggest a way to double the lifetime of 3-way bulbs in such applications. As a function of n, how many different distinct subcubes of an n-cube are there? Find a way to draw a 3-cube on a sheet of paper (or other two-dimensional object) so that none of the lines cross, or prove that its impossible.
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2.38 Repeat Exercise 2.37 for a 4-cube. 2.39 Write a formula that gives the number of m-subcubes of an n-cube for a specific value of m. (Your answer should be a function of n and m.) 2.40 Define parity groups for a distance-3 Hamming code with 11 information bits. 2.41 Write the code words of a Hamming code with one information bit. 2.42 Exhibit the pattern for a 3-bit error that is not detected if the corner parity bits are not included in the two-dimensional codes of Figure 2-14. 2.43 The rate of a code is the ratio of the number of information bits to the total number of bits in a code word. High rates, approaching 1, are desirable for efficient transmission of information. Construct a graph comparing the rates of distance-2 parity codes and distance-3 and -4 Hamming codes for up to 100 information bits. 2.44 Which type of distance-4 code has a higher ratea two-dimensional code or a Hamming code? Support your answer with a table in the style of Table 2-15, including the rate as well as the number of parity and information bits of each code for up to 100 information bits. 2.45 Show how to construct a distance-6 code with four information bits. Write a list of its code words. 2.46 Describe the operations that must be performed in a RAID system to write new data into information block b in drive d, so the data can be recovered in the event of an error in block b in any drive. Minimize the number of disk accesses required. 2.47 In the style of Figure 2-17, draw the waveforms for the bit pattern 10101110 when sent serially using the NRZ, NRZI, RZ, BPRZ, and Manchester codes, assuming that the bits are transmitted in order from left to right.
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Digital Circuits
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chapter
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arketing hype notwithstanding, we live in an analog world, not a digital one. Voltages, currents, and other physical quantities in real circuits take on values that are infinitely variable, depending on properties of the real devices that comprise the circuits. Because real values are continuously variable, we could use a physical quantity such as a signal voltage in a circuit to represent a real number (e.g., 3.14159265358979 volts represents the mathematical constant pi to 14 decimal digits of precision). Unfortunately, stability and accuracy in physical quantities are difficult to obtain in real circuits. They are affected by manufacturing tolerances, temperature, power-supply voltage, cosmic rays, and noise created by other circuits, among other things. If we used an analog voltage to represent pi, we might find that instead of being an absolute mathematical constant, pi varied over a range of 10% or more. Also, many mathematical and logical operations are difficult or impossible to perform with analog quantities. While it is possible with some cleverness to build an analog circuit whose output voltage is the square root of its input voltage, no one has ever built a 100-input, 100-output analog circuit whose outputs are a set of voltages identical to the set of input voltages, but sorted arithmetically. The purpose of this chapter is to give you a solid working knowledge of the electrical aspects of digital circuits, enough for you to understand and
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Digital Circuits
digital logic logic values
binary digit bit
LOW HIGH
positive logic negative logic
buffer amplifier
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3.1 Logic Signals and Gates
Copyright 1999 by John F. Wakerly
build real circuits and systems. Well see in later chapters that with modern software tools, its possible to build circuits in the abstract, using hardware design languages to specify their design and simulators to test their operation. Still, to build real, production-quality circuits, either at the board level or the chip level, you need to understand most of the material in this chapter. However, if youre anxious to start designing and simulating abstract circuits, you can just read the first section of this chapter and come back to the rest of it later.
Digital logic hides the pitfalls of the analog world by mapping the infinite set of real values for a physical quantity into two subsets corresponding to just two possible numbers or logic values0 and 1. As a result, digital logic circuits can be analyzed and designed functionally, using switching algebra, tables, and other abstract means to describe the operation of well-behaved 0s and 1s in a circuit. A logic value, 0 or 1, is often called a binary digit, or bit. If an application requires more than two discrete values, additional bits may be used, with a set of n bits representing 2 n different values. Examples of the physical phenomena used to represent bits in some modern (and not-so-modern) digital technologies are given in Table 3-1. With most phenomena, there is an undefined region between the 0 and 1 states (e.g., voltage = 1.8 V, dim light, capacitor slightly charged, etc.). This undefined region is needed so that the 0 and 1 states can be unambiguously defined and reliably detected. Noise can more easily corrupt results if the boundaries separating the 0 and 1 states are too close. When discussing electronic logic circuits such as CMOS and TTL, digital designers often use the words LOW and HIGH in place of 0 and 1 to remind them that they are dealing with real circuits, not abstract quantities:
LOW A signal in the range of algebraically lower voltages, which is interpret-
ed as a logic 0. HIGH A signal in the range of algebraically higher voltages, which is interpreted as a logic 1.
Note that the assignments of 0 and 1 to LOW and H IGH are somewhat arbitrary. Assigning 0 to LOW and 1 to HIGH seems most natural, and is called positive logic. The opposite assignment, 1 to LOW and 0 to HIGH, is not often used, and is called negative logic. Because a wide range of physical values represent the same binary value, digital logic is highly immune to component and power supply variations and noise. Furthermore, buffer amplifier circuits can be used to regenerate weak values into strong ones, so that digital signals can be transmitted over arbitrary distances without loss of information. For example, a buffer amplifier for CMOS
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Pneumatic logic Relay logic
Complementary metal-oxide semi conductor (CMOS) logic Transistor-transistor logic (TTL) Fiber optics
Dynamic memory
Nonvolatile, erasable memory Bipolar read-only memory Bubble memory
Magnetic tape or disk Polymer memory
Read-only compact disc
Rewriteable compact disc
logic converts any HIGH input voltage into an output very close to 5.0 V, and any LOW input voltage into an output very close to 0.0 V. A logic circuit can be represented with a minimum amount of detail simply as a black box with a certain number of inputs and outputs. For example, Figure 3-1 shows a logic circuit with three inputs and one output. However, this representation does not describe how the circuit responds to input signals. From the point of view of electronic circuit design, it takes a lot of information to describe the precise electrical behavior of a circuit. However, since the inputs of a digital logic circuit can be viewed as taking on only discrete 0 and 1 values, the circuits logical operation can be described with a table that ignores electrical behavior and lists only discrete 0 and 1 values.
Inputs X Y Z Output F
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Ta b l e 3 - 1 Physical states representing bits in different computer logic and memory technologies.
State Representing Bit Technology 0 1
Fluid at low pressure Circuit open 01.5 V
Fluid at high pressure Circuit closed 3.55.0 V
00.8 V
2.05.0 V
Light off
Light on
Capacitor discharged
Capacitor charged
Electrons trapped Fuse blown
Electrons released Fuse intact
No magnetic bubble
Bubble present
Flux direction north Molecule in state A No pit
Flux direction south Molecule in state B Pit
Dye in crystalline state
Dye in non-crystalline state
logic circuit
Figure 3-1 Black box representation of a three-input, one-output logic circuit.
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combinational circuit truth table
sequential circuit state table
AND gate OR gate
NOT gate
inverter
Figure 3-2 Basic logic elements: (a) AND; (b) OR; (c) NOT(inverter).
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Ta b l e 3 - 2 Truth table for a combinational logic circuit.
X Y Z F
A logic circuit whose outputs depend only on its current inputs is called a combinational circuit. Its operation is fully described by a truth table that lists all combinations of input values and the output value(s) produced by each one. Table 3-2 is the truth table for a logic circuit with three inputs X, Y, and Z and a single output F.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 0 0 0 0 1 1
A circuit with memory, whose outputs depend on the current input and the sequence of past inputs, is called a sequential circuit. The behavior of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input. Sequential circuits will be introduced in \chapref{SeqPrinc}. As well show in Section 4.1, just three basic logic functions, AND , OR, and NOT, can be used to build any combinational digital logic circuit. Figure 3-2 shows the truth tables and symbols for logic gates that perform these functions. The symbols and truth tables for AND and OR may be extended to gates with any number of inputs. The gates functions are easily defined in words: An AND gate produces a 1 output if and only if all of its inputs are 1. An OR gate produces a 1 if and only if one or more of its inputs are 1. A NOT gate, usually called an inverter, produces an output value that is the opposite of its input value.
X Y
X Y
(a)
X AND Y XY
(b)
X OR Y X+Y
(c)
X
NOT X X
X 0 0 1 1
Y 0 1 0 1
X AND Y 0 0 0 1
X 0 0 1 1
Y 0 1 0 1
X OR Y 0 1 1 1
X
NOT X 1 0
0 1
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X Y X Y
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The circle on the inverter symbols output is called an inversion bubble, and is used in this and other gate symbols to denote inverting behavior. Notice that in the definitions of AND and OR functions, we only had to state the input conditions for which the output is 1, because there is only one possibility when the output is not 1it must be 0. Two more logic functions are obtained by combining NOT with an AND or OR function in a single gate. Figure 3-3 shows the truth tables and symbols for these gates; Their functions are also easily described in words:
A NAND gate produces the opposite of an AND gates output, a 0 if and only if all of its inputs are 1. A NOR gate produces the opposite of an OR gates output, a 0 if and only if one or more of its inputs are 1.
As with AND and OR gates, the symbols and truth tables for NAND and NOR may be extended to gates with any number of inputs. Figure 3-4 is a logic circuit using AND, OR, and NOT gates that functions according to the truth table of Table 3-2. In Chapter 4 youll learn how to go from a truth table to a logic circuit, and vice versa, and youll also learn about the switching-algebra notation used in Figures 3-2 through 3-4. Real logic circuits also function in another analog dimensiontime. For example, Figure 3-5 is a timing diagram that shows how the circuit of Figure 3-4 might respond to a time-varying pattern of input signals. The timing diagram shows that the logic signals do not change between 0 and 1 instantaneously, and also that there is a lag between an input change and the corresponding output
X Y
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(a) X NAND Y (X Y) (b) X NOR Y (X + Y) X 0 0 1 1 Y X NAND Y 0 1 0 1 1 1 1 0 X 0 0 1 1 Y 0 1 0 1 X NOR Y 1 0 0 0
Figure 3-3 Inverting gates: (a) NAND; (b) NOR.
inversion bubble
NAND gate NOR gate
timing diagram
XY
X Y
F
X Y + X Y Z
F igure 3-4 Logic circuit with the truth table of Table 3-2.
X Y Z
Z
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Figure 3-5 Timing diagram for a logic circuit.
semiconductor diode bipolar junction transistor
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X Y Z F TIME
change. Later in this chapter, youll learn some of the reasons for this timing behavior, and how it is specified and handled in real circuits. And once again, youll learn in a later chapter how this analog timing behavior can be generally ignored in most sequential circuits, and instead the circuit can be viewed as moving between discrete states at precise intervals defined by a clock signal. Thus, even if you know nothing about analog electronics, you should be able to understand the logical behavior of digital circuits. However, there comes a time in design and debugging when every digital logic designer must temporarily throw out the digital abstraction and consider the analog phenomena that limit or disrupt digital performance. The rest of this chapter prepares you for that day by discussing the electrical characteristics of digital logic circuits.
THERES HOPE FOR NON-EES
If all of this electrical stuff bothers you, dont worry, at least for now. The rest of this book is written to be as independent of this stuff as possible. But youll need it later, if you ever have to design and build digital systems in the real world.
3.2 Logic Families
There are many, many ways to design an electronic logic circuit. The first electrically controlled logic circuits, developed at Bell Laboratories in 1930s, were based on relays. In the mid-1940s, the first electronic digital computer, the Eniac, used logic circuits based on vacuum tubes. The Eniac had about 18,000 tubes and a similar number of logic gates, not a lot by todays standards of microprocessor chips with tens of millions of transistors. However, the Eniac could hurt you a lot more than a chip could if it fell on youit was 100 feet long, 10 feet high, 3 feet deep, and consumed 140,000 watts of power! The inventions of the semiconductor diode and the bipolar junction transistor allowed the development of smaller, faster, and more capable computers in the late 1950s. In the 1960s, the invention of the integrated circuit (IC)
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allowed multiple diodes, transistors, and other components to be fabricated on a single chip, and computers got still better. The 1960s also saw the introduction of the first integrated-circuit logic families. A logic family is a collection of different integrated-circuit chips that have similar input, output, and internal circuit characteristics, but that perform different logic functions. Chips from the same family can be interconnected to perform any desired logic function. On the other hand, chips from differing families may not be compatible; they may use different power-supply voltages or may use different input and output conditions to represent logic values. The most successful bipolar logic family (one based on bipolar junction transistors) is transistor-transistor logic (TTL). First introduced in the 1960s, TTL now is actually a family of logic families that are compatible with each other but differ in speed, power consumption, and cost. Digital systems can mix components from several different TTL families, according to design goals and constraints in different parts of the system. Although TTL was largely replaced by CMOS in the 1990s, youre still likely to encounter TTL components in academic labs; therefore, we introduce TTL families in Section 3.10. Ten years before the bipolar junction transistor was invented, the principles of operation were patented for another type of transistor, called the metal-oxide semiconductor field effect transistor (MOSFET), or simply MOS transistor. However, MOS transistors were difficult to fabricate in the early days, and it wasnt until the 1960s that a wave of developments made MOS-based logic and memory circuits practical. Even then, MOS circuits lagged bipolar circuits considerably in speed, and were attractive only in selected applications because of their lower power consumption and higher levels of integration. Beginning in the mid-1980s, advances in the design of MOS circuits, in particular complementary MOS (CMOS) circuits, vastly increased their performance and popularity. By far the majority of new large-scale integrated circuits, such as microprocessors and memories, use CMOS. Likewise, small- to medium-scale applications, for which TTL was once the logic family of choice, are now likely to use CMOS devices with equivalent functionality but higher speed and lower power consumption. CMOS circuits now account for the vast majority of the worldwide IC market. CMOS logic is both the most capable and the easiest to understand commercial digital logic technology. Beginning in the next section, we describe the basic structure of CMOS logic circuits and introduce the most commonly used commercial CMOS logic families.
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logic family bipolar logic family transistor-transistor logic (TTL) metal-oxide semiconductor field effect transistor (MOSFET) MOS transistor complementary MOS (CMOS) GREEN STUFF Nowadays, the acronym MOS is usually spoken as moss, rather than spelled out. And CMOS has always been spoken as sea moss. Copying Prohibited
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3.3 CMOS Logic
5.0 V 3.5 V
As a consequence of the industrys transition from TTL to CMOS over a long period of time, many CMOS families were designed to be somewhat compatible with TTL. In Section 3.12, we show how TTL and CMOS families can be mixed within a single system.
The functional behavior of a CMOS logic circuit is fairly easy to understand, even if your knowledge of analog electronics is not particularly deep. The basic (and typically only) building blocks in CMOS logic circuits are MOS transistors, described shortly. Before introducing MOS transistors and CMOS logic circuits, we must talk about logic levels. 3.3.1 CMOS Logic Levels Abstract logic elements process binary digits, 0 and 1. However, real logic circuits process electrical signals such as voltage levels. In any logic circuit, there is a range of voltages (or other circuit conditions) that is interpreted as a logic 0, and another, nonoverlapping range that is interpreted as a logic 1. A typical CMOS logic circuit operates from a 5-volt power supply. Such a circuit may interpret any voltage in the range 01.5 V as a logic 0, and in the range 3.55.0 V as a logic 1. Thus, the definitions of LOW and HIGH for 5-volt CMOS logic are as shown in Figure 3-6. Voltages in the intermediate range (1.53.5 V) are not expected to occur except during signal transitions, and yield undefined logic values (i.e., a circuit may interpret them as either 0 or 1). CMOS circuits using other power supply voltages, such as 3.3 or 2.7 volts, partition the voltage range similarly. 3.3.2 MOS Transistors A MOS transistor can be modeled as a 3-terminal device that acts like a voltagecontrolled resistance. As suggested by Figure 3-7, an input voltage applied to one terminal controls the resistance between the remaining two terminals. In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is off) or very low (and the transistor is on).
Figure 3-6 Logic levels for typical CMOS logic circuits.
Logic 1 (HIGH)
undefined logic level
1.5 V 0.0 V
Logic 0 (LOW)
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There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of semiconductor material used for the resistance-controlled terminals. The circuit symbol for an n-channel MOS (NMOS) transistor is shown in Figure 3-8. The terminals are called gate, source, and drain. (Note that the gate of a MOS transistor has nothing to do with a logic gate.) As you might guess from the orientation of the circuit symbol, the drain is normally at a higher voltage than the source.
drain Voltage-controlled resistance: increase Vgs ==> decrease Rds Note: normally, Vgs 0
gate +
The voltage from gate to source (Vgs) in an NMOS transistor is normally zero or positive. If Vgs = 0, then the resistance from drain to source (Rds) is very high, on the order of a megohm (106 ohms) or more. As we increase Vgs (i.e., increase the voltage on the gate), Rds decreases to a very low value, 10 ohms or less in some devices. The circuit symbol for a p-channel MOS (PMOS) transistor is shown in Figure 3-9. Operation is analogous to that of an NMOS transistor, except that the source is normally at a higher voltage than the drain, and Vgs is normally zero or negative. If Vgs is zero, then the resistance from source to drain (Rds) is very high. As we algebraically decrease Vgs (i.e., decrease the voltage on the gate), Rds decreases to a very low value. The gate of a MOS transistor has a very high impedance. That is, the gate is separated from the source and the drain by an insulating material with a very high resistance. However, the gate voltage creates an electric field that enhances or retards the flow of current between source and drain. This is the field effect in the MOSFET name. Regardless of gate voltage, almost no current flows from the gate to source, or from the gate to drain for that matter. The resistance between the gate and the
Voltage-controlled resistance: decrease Vgs ==> decrease Rds Note: normally, Vgs 0
+
gate
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VIN
Figure 3-7 The MOS transistor as a voltage-controlled resistance.
n-channel MOS (NMOS) transistor gate source drain
source
Vgs
Figure 3-8 Circuit symbol for an n-channel MOS (NMOS) transistor.
p-channel MOS (PMOS) transistor
Vgs
source drain
Figure 3-9 Circuit symbol for a p-channel MOS (PMOS) transistor.
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leakage current
CMOS logic
Figure 3-10 CMOS inverter: (a) circuit diagram; (b) functional behavior; (c) logic symbol.
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IMPEDANCE VS. RESISTANCE Technically, theres a difference between impedance and resistance, but electrical engineers often use the terms interchangeably. So do we in this text.
(a) VDD = +5.0 V (b) VIN Q1 Q2 VOUT Q2
(p-channel)
other terminals of the device is extremely high, well over a megohm. The small amount of current that flows across this resistance is very small, typically less than one microampere (A, 106 A), and is called a leakage current. The MOS transistor symbol itself reminds us that there is no connection between the gate and the other two terminals of the device. However, the gate of a MOS transistor is capacitively coupled to the source and drain, as the symbol might suggest. In high-speed circuits, the power needed to charge and discharge this capacitance on each input-signal transition accounts for a nontrivial portion of a circuits power consumption. 3.3.3 Basic CMOS Inverter Circuit NMOS and PMOS transistors are used together in a complementary way to form CMOS logic. The simplest CMOS circuit, a logic inverter, requires only one of each type of transistor, connected as shown in Figure 3-10(a). The power supply voltage, VDD , typically may be in the range 26 V, and is most often set at 5.0 V for compatibility with TTL circuits. Ideally, the functional behavior of the CMOS inverter circuit can be characterized by just two cases tabulated in Figure 3-10(b): 1. VIN is 0.0 V. In this case, the bottom, n-channel transistor Q1 is off, since its Vgs is 0, but the top, p-channel transistor Q2 is on, since its Vgs is a large negative value (5.0 V). Therefore, Q2 presents only a small resistance between the power supply terminal (VDD, +5.0 V) and the output terminal (VOUT), and the output voltage is 5.0 V.
VOUT
0.0 (L) 5.0 (H)
off on
on off
5.0 (H) 0.0 (L)
Q1
VIN
(n-channel)
(c)
IN
OUT
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2. VIN is 5.0 V. Here, Q1 is on, since its Vgs is a large positive value (+5.0 V), but Q2 is off, since its Vgs is 0. Thus, Q1 presents a small resistance between the output terminal and ground, and the output voltage is 0 V. With the foregoing functional behavior, the circuit clearly behaves as a logical inverter, since a 0-volt input produces a 5-volt output, and vice versa Another way to visualize CMOS operation uses switches. As shown in Figure 3-11(a), the n-channel (bottom) transistor is modeled by a normally-open switch, and the p-channel (top) transistor by a normally-closed switch. Applying a HIGH voltage changes each switch to the opposite of its normal state, as shown in (b).
(a) VDD = +5.0 V (b) VDD = +5.0 V
The switch model gives rise to a way of drawing CMOS circuits that makes their logical behavior more readily apparent. As shown in Figure 3-12, different symbols are used for the p- and n-channel transistors to reflect their logical behavior. The n-channel transistor (Q1) is switched on, and current flows between source and drain, when a HIGH voltage is applied to its gate; this seems natural enough. The p-channel transistor (Q2) has the opposite behavior. It is
VDD = +5.0 V
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VIN = L VOUT = H VIN = H VOUT = L
Figure 3-11 Switch model for CMOS inverter: (a) LOW input; (b) HIGH input.
Figure 3-12 CMOS inverter logical operation.
Q2
(p-channel)
on when VIN is low
VOUT
Q1
VIN
(n-channel)
on when VIN is high
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Figure 3-13 CMOS 2-input NAND g ate: (a) circuit diagram; (b) function table; (c) logic symbol.
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WHATS IN A NAME?
(a) VDD (b) AB Q1 Q2 Q3 Q4 Z Q2 Q4 Z L L H H L H L H off off on on on on off off off on off on on off on off H H H L A Q1 B Q3 (c) A B Z
The DD in the name VDD refers to the drain terminal of an MOS transistor. This may seem strange, since in the CMOS inverter VDD is actually connected to the source terminal of a PMOS transistor. However, CMOS logic circuits evolved from NMOS logic circuits, where the supply was connected to the drain of an NMOS transistor through a load resistor, and the name VDD stuck. Also note that ground is sometimes referred to as VSS in CMOS and NMOS circuits. Some authors and most circuit manufacturers use VCC as the symbol for the CMOS supply voltage, since this name is used in TTL circuits, which historically preceded CMOS. To get you used to both, well start using VCC in Section 3.4.
on when a LOW voltage is applied; the inversion bubble on its gate indicates this inverting behavior.
3.3.4 CMOS NAND and NOR Gates Both NAND and NOR gates can be constructed using CMOS. A k-input gate uses k p-channel and k n-channel transistors. Figure 3-13 shows a 2-input CMOS NAND gate. If either input is LOW, the output Z has a low-impedance connection to VDD through the corresponding on p-channel transistor, and the path to ground is blocked by the corresponding off n-channel transistor. If both inputs are HIGH, the path to VDD is blocked, and Z has a low-impedance connection to ground. Figure 3-14 shows the switch model for the NAND gates operation. Figure 3-15 shows a CMOS NOR gate. If both inputs are LOW, the output Z has a low-impedance connection to VDD through the on p-channel transistors, and the path to ground is blocked by the off n-channel transistors. If either input is HIGH, the path to VDD is blocked, and Z has a low-impedance connection to ground.
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(a)
A=L
B=L
Figure 3-14 Switch model for CMOS 2-input NAND gate: (a) both inputs LOW; (b) one input HIGH ; (c) both inputs HIGH.
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NAND VS. NOR
CMOS NAND and NOR gates do not have identical performance. For a given silicon area, an n-channel transistor has lower on resistance than a p-channel transistor. Therefore, when transistors are put in series, k n-channel transistors have lower on resistance than do k p-channel ones. As a result, a k-input NAND gate is generally faster than and preferred over a k-input NOR gate.
VDD
(b)
VDD
(c)
VDD
Z=H
Z=H
Z=L
A=H
A=H
B=L
B=H
(a)
VDD
A
Q2
(b)
AB
Q1
Q2
Q3
Q4
Z
B
Q4
L L H H
L H L H
off off on on
on on off off
off on off on
on off on off
H L L L
Z
Figure 3-15 CMOS 2-input NOR gate: (a) circuit diagram; (b) function table; (c) logic symbol.
Q1
Q3
(c)
A B
Z
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VDD
(a)
fan-in
Figure 3-17 Logic diagram equivalent to the internal structure of an 8-input CMOS NAND g ate.
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(b) ABC L L H H L L H H L H L H L H L H Q1 Q2 Q3 Q4 Q5 Q6 Z Q2 Q4 Q6 Z A Q1 L L L L H H H H off off off off on on on on on on on on off off off off off off on on off off on on on on off off on on off off off on off on off on off on on off on off on off on off H H H H H H H L B Q3 (c) C Q5 A B C Z
Figure 3-16 CMOS 3-input NAND gate: (a) circuit diagram; (b) function table; (c) logic symbol.
3.3.5 Fan-In The number of inputs that a gate can have in a particular logic family is called the logic familys fan-in. CMOS gates with more than two inputs can be obtained by extending series-parallel designs on Figures 3-13 and 3-15 in the obvious manner. For example, Figure 3-16 shows a 3-input CMOS NAND gate. In principle, you could design a CMOS NAND or NOR gate with a very large number of inputs. In practice, however, the additive on resistance of series transistors limits the fan-in of CMOS gates, typically to 4 for NOR gates and 6 for NAND gates. As the number of inputs is increased, CMOS gate designers may compensate by increasing the size of the series transistors to reduce their resistance and the corresponding switching delay. However, at some point this becomes inefficient or impractical. Gates with a large number of inputs can be made faster and smaller by cascading gates with fewer inputs. For example, Figure 3-17 shows
I1 I2 I3 I4 I5 I6 I7 I8
I1 I2 I3 I4 I5 I6 I7 I8
OUT
OUT
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the logical structure of an 8-input CMOS NAND gate. The total delay through a 4-input NAND, a 2-input NOR, and an inverter is typically less than the delay of a one-level 8-input NAND circuit.
3.3.6 Noninverting Gates In CMOS, and in most other logic families, the simplest gates are inverters, and the next simplest are NAND gates and NOR gates. A logical inversion comes for free, and it typically is not possible to design a noninverting gate with a smaller number of transistors than an inverting one. CMOS noninverting buffers and AND and OR gates are obtained by connecting an inverter to the output of the corresponding inverting gate. Combining Figure 3-15(a) with an inverter yields an OR gate. Thus, Figure 3-18 shows a noninverting buffer and Figure 3-19 shows an AND gate.
Figure 3-19 CMOS 2-input AND gate: (a) circuit diagram; (b) function table; (c) logic symbol.
(a) VDD
A
B
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(a) (b) A Q1 Q2 Q3 Q4 on off on off off on Z Q2 Q4 A Z L H off on L H Q1 Q3 (c) A Z
(b) AB Q1 Q2 Q3 Q4 Q5 Q6 Z Q2 Q4 Q6 Z L L H H L H L H off off on on on on off off off on off on on off on off on on on off off off off on L L L H Q1 Q3 Q5 (c) A B Z
Figure 3-18 CMOS noninverting buffer: (a) circuit diagram; (b) function table; (c) logic symbol.
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VDD
AND-OR-INVERT (AOI) gate
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(a) (b) ABCD L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 A B Q2 Q4 Q6 Q8 Z C Q5 Q3 D Q7 Q1 L L L L L L L L H H H H H H H H off off off off off off off off on on on on on on on on on on on on on on on on off off off off off off off off off off off off on on on on off off off off on on on on on on on on off off off off on on on on off off off off off off on on off off on on off off on on off off on on on on off off on on off off on on off off on on off off off on off on off on off on off on off on off on off on on off on off on off on off on off on off on off on off
Z
H H H L H H H L H H H L L L L L
Figure 3-20 CMOS AND-OR-INVERT gate: (a) circuit diagram; (b) function tab
3.3.7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates CMOS circuits can perform two levels of logic with just a single level of transistors. For example, the circuit in Figure 3-20(a) is a two-wide, two-input CMOS AND-OR-INVERT (AOI) gate. The function table for this circuit is shown in (b) and a logic diagram for this function using AND and NOR gates is shown in Figure 3-21. Transistors can be added to or removed from this circuit to obtain an AOI function with a different number of AND s or a different number of inputs per AND. The contents of each of the Q1Q8 columns in Figure 3-20(b) depends only on the input signal connected to the corresponding transistors gate. The last column is constructed by examining each input combination and determining whether Z is connected to VDD or ground by on transistors for that input combination. Note that Z is never connected to both VDD and ground for any input combination; in such a case the output would be a non-logic value some-
Figure 3-21 Logic diagram for CMOS AND-OR-INVERT gate.
A B
Z
C D
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(a)
Figure 3-22 CMOS OR-AND-INVERT gate: (a) circuit diagram; (b) function table.
where between LOW and HIGH, and the output structure would consume excessive power due to the low-impedance connection between VDD and ground. A circuit can also be designed to perform an OR-AND-INVERT function. For example, Figure 3-22(a) is a two-wide, two-input CMOS OR-AND-INVERT (OAI ) gate. The function table for this circuit is shown in (b); the values in each column are determined just as we did for the CMOS AOI gate. A logic diagram for the OAI function using OR and NAND gates is shown in Figure 3-23. The speed and other electrical characteristics of a CMOS AOI or OAI gate are quite comparable to those of a single CMOS NAND or NOR gate. As a result, these gates are very appealing because they can perform two levels of logic (AND-OR or OR-AND) with just one level of delay. Most digital designers dont bother to use AOI gates in their discrete designs. However, CMOS VLSI devices often use these gates internally, since many HDL synthesis tools can automatically convert AND /OR logic into AOI gates when appropriate.
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(b) ABCD L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H Q1 Q2 Q3 Q4 Q5 off off on on off off on on off off on on off off on on Q6 Q7 Q8 on off on off on off on off on off on off on off on off Z A Q2 Q6 B Q4 Q8 Z C Q5 Q7 D Q1 Q3 L L L L L L L L H H H H H H H H off off off off off off off off on on on on on on on on on on on on on on on on off off off off off off off off off off off off on on on on off off off off on on on on on on on on off off off off on on on on off off off off on on off off on on off off on on off off on on off off off on off on off on off on off on off on off on off on H H H H H L L L H L L L H L L L
OR-AND-INVERT (AOI) gate
A
B
Z
Figure 3-23 Logic diagram for CMOS O R-AND-INVERT gate.
C
D
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3.4 Electrical Behavior of CMOS Circuits
3.4.1 Overview The topics that we discuss in Sections 3.53.7 include the following:
Copyright 1999 by John F. Wakerly
The next three sections discuss electrical, not logical, aspects of CMOS circuit operation. Its important to understand this material when you design real circuits using CMOS or other logic families. Most of this material is aimed at providing a framework for ensuring that the digital abstraction is really valid for a given circuit. In particular, a circuit or system designer must provide in a number of areas adequate engineering design marginsinsurance that the circuit will work properly even under the worst of conditions.
Logic voltage levels. CMOS devices operating under normal conditions are guaranteed to produce output voltage levels within well-defined LOW and HIGH ranges. And they recognize LOW and HIGH input voltage levels over somewhat wider ranges. CMOS manufacturers specify these ranges and operating conditions very carefully to ensure compatibility among different devices in the same family, and to provide a degree of interoperability (if youre careful) among devices in different families. DC noise margins. Nonnegative DC noise margins ensure that the highest LOW voltage produced by an output is always lower than the highest voltage that an input can reliably interpret as LOW, and that the lowest HIGH voltage produced by an output is always higher than the lowest voltage that an input can reliably interpret as HIGH. A good understanding of noise margins is especially important in circuits that use devices from a number of different families. Fanout. This refers to the number and type of inputs that are connected to a given output. If too many inputs are connected to an output, the DC noise margins of the circuit may be inadequate. Fanout may also affect the speed at which the output changes from one state to another. Speed. The time that it takes a CMOS output to change from the LOW state to the HIGH state, or vice versa, depends on both the internal structure of the device and the characteristics of the other devices that it drives, even to the extent of being affected by the wire or printed-circuit-board traces connected to the output. Well look at two separate components of speed transition time and propagation delay. Power consumption. The power consumed by a CMOS device depends on a number of factors, including not only its internal structure, but also the input signals that it receives, the other devices that it drives, and how often its output changes between LOW and HIGH.
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Noise. The main reason for providing engineering design margins is to ensure proper circuit operation in the presence of noise. Noise can be generated by a number of sources; several of them are listed below, from the least likely to the (perhaps surprisingly) most likely: Cosmic rays. Magnetic fields from nearby machinery. Power-supply disturbances. The switching action of the logic circuits themselves.
Electrostatic discharge. Would you believe that you can destroy a CMOS device just by touching it? Open-drain outputs. Some CMOS outputs omit the usual p-channel pullup transistors. In the HIGH state, such outputs are effectively a no-connection, which is useful in some applications. Three-state outputs. Some CMOS devices have an extra output enable control input that can be used to disable both the p-channel pull-up transistors and the n-channel pull-down transistors. Many such device outputs can be tied together to create a multisource bus, as long as the control logic is arranged so that at most one output is enabled at a time.
3.4.2 Data Sheets and Specifications The manufacturers of real-world devices provide data sheets that specify the devices logical and electrical characteristics. The electrical specifications portion of a minimal data sheet for a simple CMOS device, the 54/74HC00 quadruple NAND gate, is shown in Table 3-3. Different manufacturers typically specify additional parameters, and they may vary in how they specify even the standard parameters shown in the table. Thus, they usually also show the test circuits and waveforms that they use to define various parameters, for example as shown in Figure 3-24. Note that this figure contains information for some parameters in addition to those used with the 54/74HC00. Most of the terms in the data sheet and the waveforms in the figure are probably meaningless to you at this point. However, after reading the next three sections you should know enough about the electrical characteristics of CMOS circuits that youll be able to understand the salient points of this or any other data sheet. As a logic designer, youll need this knowledge to create reliable and robust real-world circuits and systems.
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data sheet Computer science students and other non-EE readers should not have undue fear of the material in the next three sections. Only a basic understanding of electronics, at about the level of Ohms law, is required. Copying Prohibited
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DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE The following conditions apply unless otherwise specified: Commercial: TA = 40C to +85C, VCC = 5.0V5%; Military: TA = 55C to +125C, VCC = 5.0V10%
Sym. Parameter Test Conditions (1) Min. Typ.(2) Max.
VOH
VOL ICC
SWITCHING CHARACTERISTICS OVER OPERATING RANGE, CL = 50 pF
Sym. Parameter (4) Test Conditions
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics. 2. Typical values are at VCC = 5.0 V, +25C ambient. 3. Not more than one output should be shorted at a time. Duration of short-circuit test should not exceed one second. 4. This parameter is guaranteed but not tested.
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Ta b l e 3 - 3 Manufacturers data sheet for a typical CMOS device, the 54/74HC00 quad NAND gate. VIH VIL IIH IIL Input HIGH level Input LOW level Guaranteed logic HIGH level Guaranteed logic LOW level VCC = Max., VI = VCC VCC = Max., VI = 0 V M ax.,(3) 3.15 V V 1.35 1 1 Input HIGH current Input LOW current VIK Clamp diode voltage VCC = M in., IN = 18 mA Short-circuit current VCC = Output HIGH voltage 0.7 1.2 35 V IIOS VO = GND VCC = M in., VIN = VIL VCC = M in. VIN = VIH IOH = 20 A IOH = 4 mA IOL = 20 A IOL = 4 mA 4.4 4.499 4.3 V V V 3.84 Output LOW voltage Quiescent power supply current .001 0.17 2 0.1 0.33 10 VCC = M ax. VIN = GND or VCC, IO = 0
Min. Typ. Max.
Unit
A A
mA
A
Unit
tPD CI
Propagation delay Input capacitance
A or B to Y VIN = 0 V
9 3
19 10
ns
pF pF
Cpd
Power dissipation capacitance per gate
No load
22
WHATS IN A NUMBER?
Two different prefixes, 74 and 54, are used in the part numbers of CMOS and TTL devices. These prefixes simply distinguish between commercial and military versions. A 74HC00 is the commercial part and the 54HC00 is the military version.
Copyright 1999 by John F. Wakerly
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TEST CIRCUIT FOR ALL OUTPUTS
VCC
CMOS Steady-State Electrical Behavior
95
Pulse Generator
SETUP, HOLD, AND RELEASE TIMES
Data Input
Asyncronous Control Input (PR, CLR, etc.) Syncronous Control Input (CLKEN, etc.)
PROPAGATION DELAY
Same-Phase Input Transition Output Transition
3.5 CMOS Steady-State Electrical Behavior
This section discusses the steady-state behavior of CMOS circuits, that is, the circuits behavior when inputs and outputs are not changing. The next section discusses dynamic behavior, including speed and power dissipation.
3.5.1 Logic Levels and Noise Margins The table in Figure 3-10(b) on page 84 defined the CMOS inverters behavior only at two discrete input voltages; other input voltages may yield different output voltages. The complete input-output transfer characteristic can be described
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LOADING
VCC Parameter
t en
RL
CL
S1
S2
tpZH tpZL
1 KW
VIN
Device Under Test
VOUT
S1
50 pF or 150 pF
Open
Closed Open
Closed Open
RL
t dis
tpHZ tpLZ
1 KW
Closed Open
Closed Open
RT
CL
S2
t pd
50 pF or 150 pF
Open
DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should equal ZOUT of the Pulse Generator.
tSU
tH
VCC 50% 0.0 V
Clock Input
tREM
VCC 50% 0.0 V VCC 50% 0.0 V VCC 50% 0.0 V
PULSE WIDTH
LOW-HIGH-LOW
Pulse
tW
VOH 50% VOL VOH 50% VOL
HIGH-LOW-HIGH
Pulse
tSU
tH
THREE-STATE ENABLE AND DISABLE TIMES
Enable Disable Control Input
tPLH
tPHL
VCC 50% 0.0 V VOH 50% VOL
tPZL
tPLZ
VCC 50% 0.0 V
Output Normally LOW
50%
tPLH
tPHL
Opposite-Phase Input Transition
VCC 50% 0.0 V
tPZH
tPHZ
VCC 10% VOL
Output Normally HIGH
50%
VOH 90% 0.0 V
Figure 3-24 Test circuits and waveforms for HC-series logic.
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Figure 3-25 Typical input-output transfer characteristic of a CMOS inverter.
VOUT 5.0 HIGH 3.5 undefined 1.5 LOW 0 0 1.5 3.5 5.0 LOW undefined HIGH
VIN
by a graph such as Figure 3-25. In this graph, the input voltage is varied from 0 to 5 V, as shown on the X axis; the Y axis plots the output voltage. If we believed the curve in Figure 3-25, we could define a CMOS LOW input level as any voltage under 2.4 V, and a HIGH input level as anything over 2.6 V. Only when the input is between 2.4 and 2.6 V does the inverter produce a nonlogic output voltage under this definition. Unfortunately, the typical transfer characteristic shown in Figure 3-25 is just thattypical, but not guaranteed. It varies greatly under different conditions of power supply voltage, temperature, and output loading. The transfer characteristic may even vary depending on when the device was fabricated. For example, after months of trying to figure out why gates made on some days were good and on other days were bad, one manufacturer discovered that the bad gates were victims of airborne contamination by a particularly noxious perfume worn by one of its production-line workers! Sound engineering practice dictates that we use more conservative specifications for LOW and HIGH. The conservative specs for a typical CMOS logic family (HC-series) are depicted in Figure 3-26. These parameters are specified by CMOS device manufacturers in data sheets like Table 3-3, and are defined as follows: VOHmin VIHmin VILmax VOLmax The minimum output voltage in the HIGH state. The minimum input voltage guaranteed to be recognized as a HIGH. The maximum input voltage guaranteed to be recognized as a LOW. The maximum output voltage in the LOW state.
The input voltages are determined mainly by switching thresholds of the two transistors, while the output voltages are determined mainly by the on resistance of the transistors.
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VCC VOHmin
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0.7 VCC
0.3 VCC
All of the parameters in Figure 3-26 are guaranteed by CMOS manufacturers over a range of temperature and output loading. Parameters are also guaranteed over a range of power-supply voltage VCC, typically 5.0 V 10%. The data sheet in Table 3-3 on page 94 specifies values for each of these parameters for HC-series CMOS. Notice that there are two values specified for VOHmin and VOLmax, depending on whether the output current (IOH or IOL) is large or small. When the device outputs are connected only to other CMOS inputs, the output current is low (e.g, IOL 20 A), so theres very little voltage drop across the output transistors. In the next few subsections, well focus on these pure CMOS applications. The power-supply voltage VCC and ground are often called the powersupply rails. CMOS levels are typically a function of the power-supply rails: VOHmin VIHmin VILmax VOLmax VCC 0.1 V 70% of VCC 30% of VCC ground + 0.1 V
Notice in Table 3-3 that VOHmin is specified as 4.4 V. This is only a 0.1-V drop from VCC, since the worst-case number is specified with VCC at its minimum value of 5.010% = 4.5 V. DC noise margin is a measure of how much noise it takes to corrupt a worst-case output voltage into a value that may not be recognized properly by an input. For HC-series CMOS in the LOW state, VILmax (1.35 V) exceeds VOLmax (0.1 V) by 1.25 V so the LOW-state DC noise margin is 1.25 V. Likewise, there is DC noise margin of 1.25 V in the HIGH state. In general, CMOS outputs have excellent DC noise margins when driving other CMOS inputs. Regardless of the voltage applied to the input of a CMOS inverter, the input consumes very little current, only the leakage current of the two transistors gates. The maximum amount of current that can flow is also specified by the device manufacturer: IIH The maximum current that flows into the input in the LOW state.
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HIGH VIHmin High-state DC noise margin ABNORMAL LOW VILmax 0 VOLmax Low-state DC noise margin
Figure 3-26 Logic levels and noise margins for the HC-series CMOS logic family.
power-supply rails
DC noise margin
IIL The maximum current that flows into the input in the HIGH state.
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VCC = +5.0 V Thevenin equivalent of resistive load
resistive load DC load
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VCC = +5.0 V (a) (b) CMOS inverter CMOS inverter Rp 1 k Rp VIN VOUT VIN VOUT RThev = 667 + Rn 2 k Rn resistive load VThev = 3.33 V
Figure 3-27 Resistive model of a CMOS inverter with a resistive load: (a) showing actual load circuit; (b) using Thvenin equivalent of load.
The input current shown in Table 3-3 for the HC00 is only 1 A. Thus, it takes very little power to maintain a CMOS input in one state or the other. This is in sharp contrast to bipolar logic circuits like TTL and ECL, whose inputs may consume significant current (and power) in one or both states. 3.5.2 Circuit Behavior with Resistive Loads As mentioned previously, CMOS gate inputs have very high impedance and consume very little current from the circuits that drive them. There are other devices, however, which require nontrivial amounts of current to operate. When such a device is connected to a CMOS output, we call it a resistive load or a DC load. Here are some examples of resistive loads: Discrete resistors may be included to provide transmission-line termination, discussed in Section 12.4. Discrete resistors may not really be present in the circuit, but the load presented by one or more TTL or other non-CMOS inputs may be modeled by a simple resistor network. The resistors may be part of or may model a current-consuming device such as a light-emitting diode (LED) or a relay coil.
When the output of a CMOS circuit is connected to a resistive load, the output behavior is not nearly as ideal as we described previously. In either logic state, the CMOS output transistor that is on has a nonzero resistance, and a load connected to the output terminal will cause a voltage drop across this resistance. Thus, in the LOW state, the output voltage may be somewhat higher than 0.1 V, and in the HIGH state it may be lower than 4.4 V. The easiest way to see how this happens is look at a resistive model of the CMOS circuit and load.
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Figure 3-27(a) shows the resistive model. The p-channel and n-channel transistors have resistances Rp and Rn, respectively. In normal operation, one resistance is high (> 1 M) and the other is low (perhaps 100 ), depending on whether the input voltage is HIGH or LOW. The load in this circuit consists of two resistors attached to the supply rails; a real circuit may have any resistor values, or an even more complex resistive network. In any case, a resistive load, consisting only of resistors and voltage sources, can always be modeled by a Thvenin equivalent network, such as the one shown in Figure 3-27(b). When the CMOS inverter has a HIGH input, the output should be LOW; the actual output voltage can be predicted using the resistive model shown in Figure 3-28. The p-channel transistor is off and has a very high resistance, high enough to be negligible in the calculations that follow. The n-channel tran-
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CMOS inverter > 1 M VIN = +5.0 V (HIGH) VOUT = 0.43 V (LOW) RThev = 667 + 100 VThev = 3.33 V
Figure 3-28 Resistive model for CMOS LOW output with resistive load.
REMEMBERING THVENIN
Any two-terminal circuit consisting of only voltage sources and resistors can be modeled by a Thvenin equivalent consisting of a single voltage source in series with a single resistor. The Thvenin voltage is the open-circuit voltage of the original circuit, and the Thvenin resistance is the Thvenin voltage divided by the short-circuit current of the original circuit. In the example of Figure 3-27, the Thvenin voltage of the resistive load, including its connection to VCC, is established by the 1-k and 2-k resistors, which form a voltage divider: 2 k V Thev = ----------------------------- 5.0 V = 3.33 V 2 k + 1k
The short-circuit current is (5.0 V)/(1 k) = 5 mA, so the Thvenin resistance is (3.33 V)/(5 mA) = 667 . Experienced readers may recognize this as the parallel resistance of the 1-k and 2- resistors.
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Figure 3-29 Resistive model for CMOS HIGH output with resistive load.
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V OUT = 3.33 V [ 100 ( 100 + 667 ) ] = 0.43 V VOUT = 3.33 V + ( 5 V 3.33 V ) [ 667/ ( 200 + 667 ) ] = 4.61 V
VCC = +5.0 V Thevenin equivalent of resistive load CMOS inverter 200 VIN = +0.0 V (LOW) VOUT = 4.61 V (HIGH) RThev = 667 + > 1 M VThev = 3.33 V
sistor is on and has a low resistance, which we assume to be 100 . (The actual on resistance depends on the CMOS family and other characteristics such as operating temperature and whether or not the device was manufactured on a good day.) The on transistor and the Thvenin-equivalent resistor RThev in Figure 3-28 form a simple voltage divider. The resulting output voltage can be calculated as follows:
Similarly, when the inverter has a LOW input, the output should be HIGH, and the actual output voltage can be predicted with the model in Figure 3-29. Well assume that the p-channel transistors on resistance is 200 . Once again, the on transistor and the Thvenin-equivalent resistor RThev in the figure form a simple voltage divider, and the resulting output voltage can be calculated as follows:
In practice, its seldom necessary to calculate output voltages as in the preceding examples. In fact, IC manufacturers usually dont specify the equivalent resistances of the on transistors, so you wouldnt have the necessary information to make the calculation anyway. Instead, IC manufacturers specify a maximum load for the output in each state (HIGH or LOW), and guarantee a worst-case output voltage for that load. The load is specified in terms of current: IOLmax The maximum current that the output can sink in the LOW state while still maintaining an output voltage no greater than VOLmax. IOHmax The maximum current that the output can source in the HIGH state while still maintaining an output voltage no less than VOHmin.
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(a) VCC (b)
CMOS Steady-State Electrical Behavior
VCC
101
VIN
"sinking current"
Figure 3-30 Circuit definitions of (a) IOLmax; (b) IOHmax.
These definitions are illustrated in Figure 3-30. A device output is said to sink current when current flows from the power supply, through the load, and through the device output to ground as in (a). The output is said to source current when current flows from the power supply, out of the device output, and through the load to ground as in (b). Most CMOS devices have two sets of loading specifications. One set is for CMOS loads, where the device output is connected to other CMOS inputs, which consume very little current. The other set is for TTL loads, where the output is connected to resistive loads such as TTL inputs or other devices that consume significant current. For example, the specifications for HC-series CMOS outputs were shown in Table 3-3 and are repeated in Table 3-4. Notice in the table that the output current in the HIGH state is shown as a negative number. By convention, the current flow measured at a device terminal is positive if positive current flows into the device; in the HIGH state, current flows out of the output terminal.
T a b l e 3 - 4 Output loading specifications for HC-series CMOS with a 5-volt supply.
CMOS load
Maximum LOW-state output current (mA) Maximum LOW-state output voltage (V)
Maximum HIGH-state output current (mA) Minimum HIGH-state output voltage (V)
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"sourcing current" CMOS inverter CMOS inverter Rp > 1 M Rp resistive load VOLmax IOLmax VIN VOHmin IOHmax Rn resistive load Rn > 1 M
sinking current
sourcing current
current flow
TTL load
Parameter
Name
Value
Name
Value
IOLmaxC
0.02 0.1
IOLmaxT
4.0
VOLmaxC
VOLmaxT IOHmaxT
0.33
IOHmaxC
0.02 4.4
4.0
VOHminC
VOHminT
3.84
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VDD VOHminT R p ( on ) = ----------------------------------I OHmaxT VOLmaxT R n ( on ) = ------------------I OLmaxT
Copyright 1999 by John F. Wakerly
As the table shows, with CMOS loads, the CMOS gates output voltage is maintained within 0.1 V of the power-supply rail.With TTL loads, the output voltage may degrade quite a bit. Also notice that for the same output current (4 mA) the maximum voltage drop with respect to the power-supply rail is twice as much in the HIGH state (0.66 V) as in the LOW state (0.33 V). This suggests that the p-channel transistors in HC-series CMOS have a higher on resistance than the n-channel transistors do. This is natural, since in any CMOS circuit, a p-channel transistor has over twice the on resistance of an n-channel transistor with the same area. Equal voltage drops in both states could be obtained by making the p-channel transistors much larger than the n-channel transistors, but for various reasons this was not done. Ohms law can be used to determine how much current an output sources or sinks in a given situation. In Figure 3-28 on page 99, the on n-channel transistor modeled by a 100- resistor has a 0.43-V drop across it; therefore it sinks (0.43 V)/(100 ) = 4.3 mA of current. Similarly, the on p-channel transistor in Figure 3-29 sources (0.39 V)/(200 ) = 1.95 mA. The actual on resistances of CMOS output transistors usually arent published, so its not always possible to use the exact models of the previous paragraphs. However, you can estimate on resistances using the following equations, which rely on specifications that are always published:
These equations use Ohms law to compute the on resistance as the voltage drop across the on transistor divided by the current through it with a worstcase resistive load. Using the numbers given for HC-series CMOS in Table 3-4, we can calculate Rp(on) = 175 and Rn(on) = 82.5 . Very good worst-case estimates of output current can be made by assuming that there is no voltage drop across the on transistor. This assumption simplifies the analysis, and yields a conservative result that is almost always good enough for practical purposes. For example, Figure 3-31 shows a CMOS inverter driving the same Thvenin-equivalent load that weve used in previous examples. The resistive model of the output structure is not shown, because it is no longer needed; we assume that there is no voltage drop across the on CMOS transistor. In (a), with the output LOW, the entire 3.33-V Thveninequivalent voltage source appears across RThev, and the estimated sink current is (3.33 V)/(667 ) = 5.0 mA. In (b), with the output HIGH and assuming a 5.0-V supply, the voltage drop across RThev is 1.67 V, and the estimated source current is (1.67 V)/(667 ) = 2.5 mA.
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(a)
VIN = HIGH
Figure 3-31 Estimating sink and source current: (a) output LOW; (b) output HIGH.
An important feature of the CMOS inverter (or any CMOS circuit) is that the output structure by itself consumes very little current in either state, HIGH or LOW. In either state, one of the transistors is in the high-impedance off state. All of the current flow that weve been talking about occurs when a resistive load is connected to the CMOS output. If theres no load, then theres no current flow, and the power consumption is zero. With a load, however, current flows through both the load and the on transistor, and power is consumed in both.
3.5.3 Circuit Behavior with Nonideal Inputs So far, we have assumed that the HIGH and LOW inputs to a CMOS circuit are ideal voltages, very close to the power-supply rails. However, the behavior of a real CMOS inverter circuit depends on the input voltage as well as on the characteristics of the load. If the input voltage is not close to the power-supply rail, then the on transistor may not be fully on and its resistance may increase. Likewise, the off transistor may not be fully off and its resistance may be quite a bit less than one megohm. These two effects combine to move the output voltage away from the power-supply rail.
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VCC = +5.0 V CMOS inverter Thevenin equivalent of resistive load (b) VCC = +5.0 V CMOS inverter VOUT = 0 V RThev = 667 + VIN = LOW VOUT = 5.0 V RThev = 667 + IOUT = 5.0 mA |IOUT| = 2.5 mA VThev = 3.33 V VThev = 3.33 V
Thevenin equivalent of resistive load
THE TRUTH ABOUT POWER CONSUMPTION
As weve stated elsewhere, an off transistors resistance is over one megohm, but its not infinite. Therefore, a very tiny leakage current actually does flow in off transistors and the CMOS output structure does have a correspondingly tiny but nonzero power consumption. In most applications, this power consumption is tiny enough to ignore. It is usually significant only in standby mode in battery-powered devices, such as the laptop computer on which this chapter was first prepared.
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VCC = +5.0 V VCC = +5.0 V
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(a) Iwasted (b) Iwasted 400 4 k VIN = 1.5 V VOUT = 4.31 V VIN = 3.5 V 2.5 k 200
VOUT = 0.24 V
Figure 3-32 CMOS inverter with nonideal input voltages: (a) equivalent circuit with 1.5-V input; (b) equivalent circuit with 3.5-V input.
For example, Figure 3-32(a) shows a CMOS inverters possible behavior with a 1.5-V input. The p-channel transistors resistance has doubled at this point, and that the n-channel transistor is beginning to turn on. (These values are simply assumed for the purposes of illustration; the actual values depend on the detailed characteristics of the transistors.) In the figure, the output at 4.31 V is still well within the valid range for a HIGH signal, but not quite the ideal of 5.0 V. Similarly, with a 3.5-V input in (b), the LOW output is 0.24 V, not 0 V. The slight degradation of output voltage is generally tolerable; whats worse is that the output structure is now consuming a nontrivial amount of power. The current flow with the 1.5-V input is I wasted = 5.0 V/400 + 2.5 k = 1.72 mA P wasted = 5.0 V I wasted = 8.62 mW
and the power consumption is
The output voltage of a CMOS inverter deteriorates further with a resistive load. Such a load may exist for any of a variety of reasons discussed previously. Figure 3-33 shows a CMOS inverters possible behavior with a resistive load. With a 1.5-V input, the output at 3.98 V is still within the valid range for a HIGH signal, but it is far from the ideal of 5.0 V. Similarly, with a 3.5-V input as shown in Figure 3-34, the LOW output is 0.93 V, not 0 V. In pure CMOS systems, all of the logic devices in a circuit are CMOS. Since CMOS inputs have a very high impedance, they present very little resistive load to the CMOS outputs that drive them. Therefore, the CMOS output levels all remain very close to the power-supply rails (0 V and 5 V), and none of the devices waste power in their output structures. On the other hand, if TTL outputs or other nonideal logic signals are connected to CMOS inputs, then the CMOS
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outputs use power in the way depicted in this subsection; this is formalized in the box at the top of page 135. In addition, if TTL inputs or other resistive loads are connected to CMOS outputs, then the CMOS outputs use power in the way depicted in the preceding subsection.
3.5.4 Fanout The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible output states, HIGH and LOW. For example, we showed in Table 3-4 on page 101 that the maximum LOW-state output current IOLmaxC for an HC-series CMOS gate driving CMOS inputs is 0.02 mA (20 A). We also stated previously that the maximum input current IImax for an HC-series CMOS input in any state is 1 A. Therefore, the LOW-state fanout for an HC-series output driving HC-series inputs is 20. Table 3-4 also showed that the maximum HIGH -state output current IOHmaxC is
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CMOS inverter 400 VIN = +1.5V (LOW) VOUT = 3.98 V (HIGH) RThev = 667 + 2.5K VThev = 3.33 V
Figure 3-33 CMOS inverter with load and nonideal 1.5-V input.
fanout
LOW-state fanout
VCC = +5.0 V
Thevenin equivalent of resistive load
CMOS inverter
4 K
Figure 3-34 CMOS inverter with load and nonideal 3.5-V input.
VIN = +3.5V (HIGH)
VOUT = 0.93 V (LOW)
RThev = 667 +
200
VThev = 3.33 V
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HIGH -state fanout
overall fanout
DC fanout
AC fanout
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3.5.5 Effects of Loading Loading an output beyond its rated fanout has several effects: In the HIGH state, the output voltage (VOH) may fall below VOHmin. Propagation delay to the output may increase beyond specifications. Output rise and fall times may increase beyond their specifications.
Copyright 1999 by John F. Wakerly
0.02 mA (20 A) Therefore, the HIGH-state fanout for an HC-series output driving HC-series inputs is also 20. Note that the HIGH-state and LOW-state fanouts of a gate are not necessarily equal. In general, the overall fanout of a gate is the minimum of its HIGHstate and LOW-state fanouts, 20 in the foregoing example. In the fanout example that we just completed, we assumed that we needed to maintain the gates output at CMOS levels, that is, within 0.1 V of the powersupply rails. If we were willing to live with somewhat degraded, TTL output levels, then we could use IOLmaxT and IOHmaxT in the fanout calculation. According to Table 3-4, these specifications are 4.0 mA and 4.0 mA, respectively. Therefore, the fanout of an HC-series output driving HC-series inputs at TTL levels is 4000, virtually unlimited, apparently. Well, not quite. The calculations that weve just carried out give the DC fanout, defined as the number of inputs that an output can drive with the output in a constant state (HIGH or LOW). Even if the DC fanout specification is met, a CMOS output driving a large number of inputs may not behave satisfactorily on transitions, LOW-to-HIGH or vice versa. During transitions, the CMOS output must charge or discharge the stray capacitance associated with the inputs that it drives. If this capacitance is too large, the transition from LOW to HIGH (or vice versa) may be too slow, causing improper system operation. The ability of an output to charge and discharge stray capacitance is sometimes called AC fanout, though it is seldom calculated as precisely as DC fanout. As youll see in Section 3.6.1, its more a matter of deciding how much speed degradation youre willing to live with.
In the LOW state, the output voltage (VOL) may increase beyond VOLmax.
The operating temperature of the device may increase, thereby reducing the reliability of the device and eventually causing device failure.
The first four effects reduce the DC noise margins and timing margins of the circuit. Thus, a slightly overloaded circuit may work properly in ideal conditions, but experience says that it will fail once its out of the friendly environment of the engineering lab.
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(a)
Figure 3-35 Unused inputs: (a) tied to another input; (b) NAND pulled up; (c) NOR pulled down.
3.5.6 Unused Inputs Sometimes not all of the inputs of a logic gate are used. In a real design problem, you may need an n-input gate but have only an n+1-input gate available. Tying together two inputs of the n+1-input gate gives it the functionality of an n-input gate. You can convince yourself of this fact intuitively now, or use switching algebra to prove it after youve studied Section 4.1. Figure 3-35(a) shows a NAND gate with its inputs tied together. You can also tie unused inputs to a constant logic value. An unused AND or NAND input should be tied to logic 1, as in (b), and an unused OR or NOR input should be tied to logic 0, as in (c). In high-speed circuit design, its usually better to use method (b) or (c) rather than (a), which increases the capacitive load on the driving signal and may slow things down. In (b) and (c), a resistor value in the range 110 k is typically used, and a single pull-up or pull-down resistor can serve multiple unused inputs. It is also possible to tie unused inputs directly to the appropriate power-supply rail. Unused CMOS inputs should never be left unconnected (or floating. On one hand, such an input will behave as if it had a LOW signal applied to it and will normally show a value of 0 V when probed with an oscilloscope or voltmeter. So you might think that an unused OR or NOR input can be left floating, because it will act as if a logic 0 is applied and not affect the gates output. How-
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(b) (c) X 1 k X Z logic 1 logic 0 1k X Z
Z
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SUBTLE BUGS
Floating CMOS inputs are often the cause of mysterious circuit behavior, as an unused input erratically changes its effective state based on noise and conditions elsewhere in the circuit. When youre trying to debug such a problem, the extra capacitance of an oscilloscope probe touched to the floating input is often enough to damp out the noise and make the problem go away. This can be especially baffling if you dont realize that the input is floating!
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current spikes
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filtering capacitors
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ever, since CMOS inputs have such high impedance, it takes only a small amount of circuit noise to temporarily make a floating input look HIGH, creating some very nasty intermittent circuit failures.
3.5.7 Current Spikes and Decoupling Capacitors When a CMOS output switches between LOW and HIGH, current flows from VCC to ground through the partially-on p- and n-channel transistors. These currents, often called current spikes because of their brief duration, may show up as noise on the power-supply and ground connections in a CMOS circuit, especially when multiple outputs are switched simultaneously. For this reason, systems that use CMOS circuits require decoupling capacitors between VCC and ground. These capacitors must be distributed throughout the circuit, at least one within an inch or so of each chip, to supply current during transitions. The large filtering capacitors typically found in the power supply itself dont satisfy this requirement, because stray wiring inductance prevents them from supplying the current fast enough, hence the need for a physically distributed system of decoupling capacitors. 3.5.8 How to Destroy a CMOS Device Hit it with a sledge hammer. Or simply walk across a carpet and then touch an input pin with your finger. Because CMOS device inputs have such high impedance, they are subject to damage from electrostatic discharge (ESD). ESD occurs when a buildup of charge on one surface arcs through a dielectric to another surface with the opposite charge. In the case of a CMOS input, the dielectric is the insulation between an input transistors gate and its source and drain. ESD may damage this insulation, causing a short-circuit between the devices input and output. The input structures of modern CMOS devices use various measures to reduce their susceptibility to ESD damage, but no device is completely immune. Therefore, to protect CMOS devices from ESD damage during shipment and handling, manufacturers normally package their devices in conductive bags, tubes, or foam. To prevent ESD damage when handling loose CMOS devices, circuit assemblers and technicians usually wear conductive wrist straps that are connected by a coil cord to earth ground; this prevents a static charge from building up on their bodies as they move around the factory or lab. Once a CMOS device is installed in a system, another possible source of damage is latch-up. The physical input structure of just about any CMOS device contains parasitic bipolar transistors between VCC and ground configured as a silicon-controlled rectifier (SCR). In normal operation, this parasitic SCR has no effect on device operation. However, an input voltage that is less than ground or more than VCC can trigger the SCR, creating a virtual short-circuit between VCC and ground. Once the SCR is triggered, the only way to turn it off
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ELIMINATE RUDE, SHOCKING BEHAVIOR!
is to turn off the power supply. Before you have a chance to do this, enough power may be dissipated to destroy the device (i.e., you may see smoke). One possible trigger for latch-up is undershoot on high-speed HIGH-toLOW signal transitions, discussed in Section 12.4. In this situation, the input signal may go several volts below ground for several nanoseconds before settling into the normal LOW range. However, modern CMOS logic circuits are fabricated with special structures that prevent latch-up in this transient case. Latch-up can also occur when CMOS inputs are driven by the outputs of another system or subsystem with a separate power supply. If a HIGH input is applied to a CMOS gate before power is present, the gate may come up in the latched-up state when power is applied. Again, modern CMOS logic circuits are fabricated with special structures that prevent this in most cases. However, if the driving output is capable of sourcing lots of current (e.g., tens of mA), latchup is still possible. One solution to this problem is to apply power before hooking up input cables.
3.6 CMOS Dynamic Electrical Behavior
Both the speed and the power consumption of a CMOS device depend to a large extent on AC or dynamic characteristics of the device and its load, that is, what happens when the output changes between states. As part of the internal design of CMOS ASICs, logic designers must carefully examine the effects of output loading and redesign where the load is too high. Even in board-level design, the effects of loading must be considered for clocks, buses, and other signals that have high fanout or long interconnections. Speed depends on two characteristics, transition time and propagation delay, discussed in the next two subsections. Power dissipation is discussed in the third subsection.
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Some design engineers consider themselves above such inconveniences, but to be safe you should follow several ESD precautions in the lab: in instrument or another source of earth ground.
Before handling a CMOS device, touch the grounded metal case of a plugged Before transporting a CMOS device, insert it in conductive foam. When carrying a circuit board containing CMOS devices, handle the board by
the edges, and touch a ground terminal on the board to earth ground before poking around with it. touch the partner first. He or she will thank you for it.
When handing over a CMOS device to a partner, especially on a dry winter day,
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Figure 3-36 Transition times: (a) ideal case of zero-time switching; (b) a more realistic approximation; (c) actual timing, showing rise and fall times.
transition time
rise time (tr) fall time (tf)
stray capacitance
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(a) (b) tr tf (c)
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VIHmin
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tf
3.6.1 Transition Time The amount of time that the output of a logic circuit takes to change from one state to another is called the transition time. Figure 3-36(a) shows how we might like outputs to change statein zero time. However, real outputs cannot change instantaneously, because they need time to charge the stray capacitance of the wires and other components that they drive. A more realistic view of a circuits output is shown in (b). An output takes a certain time, called the rise time (tr), to change from LOW to HIGH, and a possibly different time, called the fall time (tf), to change from HIGH to LOW. Even Figure 3-36(b) is not quite accurate, because the rate of change of the output voltage does not change instantaneously, either. Instead, the beginning and the end of a transition are smooth, as shown in (c). To avoid difficulties in defining the endpoints, rise and fall times are normally measured at the boundaries of the valid logic levels as indicated in the figure. With the convention in (c), the rise and fall times indicate how long an output voltage takes to pass through the undefined region between LOW and HIGH . The initial part of a transition is not included in the rise- or fall-time number. Instead, the initial part of a transition contributes to the propagation delay number discussed in the next subsection. The rise and fall times of a CMOS output depend mainly on two factors, the on transistor resistance and the load capacitance. A large capacitance increases transition times; since this is undesirable, it is very rare for a logic designer to purposely connect a capacitor to a logic circuits output. However, stray capacitance is present in every circuit; it comes from at least three sources: 1. Output circuits, including a gates output transistors, internal wiring, and packaging, have some capacitance associated with them, on the order of 210 picofarads (pF) in typical logic families, including CMOS.
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2. The wiring that connects an output to other inputs has capacitance, about 1 pF per inch or more, depending on the wiring technology. 3. Input circuits, including transistors, internal wiring, and packaging, have capacitance, from 2 to 15 pF per input in typical logic families.
Stray capacitance is sometimes called a capacitive load or an AC load. A CMOS outputs rise and fall times can be analyzed using the equivalent circuit shown in Figure 3-37. As in the preceding section, the p-channel and nchannel transistors are modeled by resistances Rp and Rn, respectively. In normal operation, one resistance is high and the other is low, depending on the outputs state. The outputs load is modeled by an equivalent load circuit with three components: RL, VL These two components represent the DC load and determine the voltages and currents that are present when the output has settled into a stable HIGH or LOW state. The DC load doesnt have too much effect on transition times when the output changes states. CL This capacitance represents the AC load and determines the voltages and currents that are present while the output is changing, and how long it takes to change from one state to the other
When a CMOS output drives only CMOS inputs, the DC load is negligible. To simplify matters, well analyze only this case, with RL = and VL = 0, in the remainder of this subsection. The presence of a nonnegligible DC load would affect the results, but not dramatically (see Exercise 3.69). We can now analyze the transition times of a CMOS output. For the purposes of this analysis, well assume CL= 100 pF, a moderate capacitive load. Also, well assume that the on resistances of the p-channel and n-channel transistors are 200 and 100 , respectively, as in the preceding subsection. The rise and fall times depend on how long it takes to charge or discharge the capacitive load CL.
VCC = +5.0 V Equivalent load for transition-time analysis
Figure 3-37 Equivalent circuit for analyzing transition times of a CMOS output.
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capacitive load AC load
CMOS inverter Rp VIN VOUT RL Rn + CL VL
equivalent load circuit
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(b) 200 > 1 M AC load AC load VOUT = 5.0 V IOUT = 0 VIN VOUT IOUT > 1 M 100 100 pF
100 pF
Figure 3-38 Model of a CMOS HIGH-to-LOW transition: (a) in the HIGH state; (b) after p-channel transistor turns off and n-channel transistor turns on.
First, well look at fall time. Figure 3-38(a) shows the electrical conditions in the circuit when the output is in a steady H IGH state. (RL and VL are not drawn; they have no effect, since we assume RL = .) For the purposes of our analysis, well assume that when CMOS transistors change between on and off, they do so instantaneously. Well assume that at time t = 0 the CMOS output changes to the LOW state, resulting in the situation depicted in (b). At time t = 0, VOUT is still 5.0 V. (A useful electrical engineering maxim is that the voltage across a capacitor cannot change instantaneously.) At time t = , the capacitor must be fully discharged and VOUT will be 0 V. In between, the value of VOUT is governed by an exponential law: V OUT = V DD e t / R n C L = 5.0 e t ( 100 100 10 = 5.0 e t / ( 10 10
9 12
)
)
V
The factor RnCL has units of seconds, and is called an RC time constant. The preceding calculation shows that the RC time constant for HIGH -to-LOW transitions is 10 nanoseconds (ns). Figure 3-39 plots VOUT as a function of time. To calculate fall time, recall that 1.5 V and 3.5 V are the defined boundaries for LOW and HIGH levels for CMOS inputs being driven by the CMOS output. To obtain the fall time, we must solve the preceding equation for VOUT = 3.5 and VOUT = 1.5, yielding: V OUT V OUT 9 t = R n C L ln ------------ = 10 10 ln -----------V DD 5.0 t 3.5 = 3.57 ns t 1.5 = 12.04 ns
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The fall time tf is the difference between these two numbers, or about 8.5 ns. Rise time can be calculated in a similar manner. Figure 3-40(a) shows the conditions in the circuit when the output is in a steady LOW state. If at time t = 0 the CMOS output changes to the HIGH state, the situation depicted in (b) results. Once again, VOUT cannot change instantly, but at time t = , the capacitor will be fully charged and VOUT will be 5.0 V. Once again, the value of VOUT in between is governed by an exponential law: V OUT = V DD ( 1 e t / Rp C L ) = 5.0 ( 1 e t ( 200 100 10 ) ) 9 = 5.0 ( 1 e t / ( 20 10 ) ) V
12
Figure 3-40 Model of a CMOS LOW-to-HIGH transition: (a) in the LOW state; (b) after n-channel transistor turns off and p-channel transistor turns on.
VCC = +5.0 V VCC = +5.0 V
(a)
VIN
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200 > 1 M 100 > 1 M 5V 3.5 V VOUT 1.5 V 0V 0 time tf
(b) > 1 M 200 AC load AC load VOUT = 0 V IOUT = 0 VIN VOUT IOUT 100 > 1 M 100 pF
Figure 3-39 Fall time for a HIGHto- LOW transition of a CMOS output.
100 pF
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200 > 1 M 100 > 1 M 5V 3.5 V VOUT 1.5 V 0V 0 time tr
Figure 3-41 Rise time for a LOWto- HIGH transition of a CMOS output.
The RC time constant in this case is 20 ns. Figure 3-41 plots VOUT as a function of time. To obtain the rise time, we must solve the preceding equation for VOUT = 1.5 and VOUT = 3.5, yielding V DD V OUT t = RC ln ---------------------------V DD = 20 10
9
5.0 V OUT ln ------------------------5.0
t 1.5 = 7.13 ns
t 3.5 = 24.08 ns
The rise time tr is the difference between these two numbers, or about 17 ns. The foregoing example assumes that the p-channel transistor has twice the resistance of the n-channel one, and as a result the rise time is twice as long as the fall time. It takes longer for the weak p-channel transistor to pull the output up than it does for the strong n-channel transistor to pull it down; the outputs drive capability is asymmetric. High-speed CMOS devices are sometimes fabricated with larger p-channel transistors to make the transition times more nearly equal and output drive more symmetric. Regardless of the transistors characteristics, an increase in the load capacitance cause an increase in the RC time constant, and a corresponding increase in the transition times of the output. Thus, it is a goal of high-speed circuit designers to minimize load capacitance, especially on the most timing-critical signals. This can be done by minimizing the number of inputs driven by the signal, by creating multiple copies of the signal, and by careful physical layout of the circuit.
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When working with real digital circuits, its often useful to estimate transition times, without going through a detailed analysis. A useful rule of thumb is that the transition time approximately equals the RC time constant of the charging or discharging circuit. For example, estimates of 10 and 20 ns for fall and rise time in the preceding example would have been pretty much on target, especially considering that most assumptions about load capacitance and transistor on resistances are approximate to begin with. Manufacturers of commercial CMOS circuits typically do not specify transistor on resistances on their data sheets. If you search carefully, you might find this information published in the manufacturers application notes. In any case, you can estimate an on resistance as the voltage drop across the on transistor divided by the current through it with a worst-case resistive load, as we showed in Section 3.5.2: V DD V OHminT R p(on) = ----------------------------------I OHmaxT V OLmaxT R n(on) = -------------------I OLmaxT
3.6.2 Propagation Delay Rise and fall times only partially describe the dynamic behavior of a logic element; we need additional parameters to relate output timing to input timing. A signal path is the electrical path from a particular input signal to a particular output signal of a logic element. The propagation delay tp of a signal path is the amount of time that it takes for a change in the input signal to produce a change in the output signal. A complex logic element with multiple inputs and outputs may specify a different value of tp for each different signal path. Also, different values may be specified for a particular signal path, depending on the direction of the output change. Ignoring rise and fall times, Figure 3-42(a) shows two different propa-
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THERES A CATCH! Calculated transition times are actually quite sensitive to the choice of logic levels. In the examples in this subsection, if we used 2.0 V and 3.0 V instead of 1.5 V and 3.5 V as the thresholds for LOW and HIGH, we would calculate shorter transition times. On the other hand, if we used 0.0 and 5.0 V, the calculated transition times would be infinity! You should also be aware that in some logic families (most notably TTL), the thresholds are not symmetric around the voltage midpoint. Still, it is the authors experience that the time-constant-equals-transition-time rule of thumb usually works for practical circuits. signal path propagation delay tp Copying Prohibited
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(a)
Figure 3-42 Propagation delays for a CMOS inverter: (a) ignoring rise and fall times; (b) measured at midpoints of transitions.
tpHL
tpLH
Figure 3-43 Worst-case timing specified using logiclevel boundary points.
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VIN VOUT tpHL tpLH (b) VIN VOUT tpHL tpLH
HIGH LOW
gation delays for the input-to-output signal path of a CMOS inverter, depending on the direction of the output change: tpHL The time between an input change and the corresponding output change when the output is changing from HIGH to LOW. tpLH The time between an input change and the corresponding output change when the output is changing from LOW to HIGH.
Several factors lead to nonzero propagation delays. In a CMOS device, the rate at which transistors change state is influenced both by the semiconductor physics of the device and by the circuit environment, including input-signal transition rate, input capacitance, and output loading. Multistage devices such as noninverting gates or more complex logic functions may require several internal transistors to change state before the output can change state. And even when the output begins to change state, with nonzero rise and fall times it takes quite some time to cross the region between states, as we showed in the preceding subsection. All of these factors are included in propagation delay. To factor out the effect of rise and fall times, manufacturers usually specify propagation delays at the midpoints of input and output transitions, as shown in Figure 3-42(b). However, sometimes the delays are specified at the logic-level boundary points, especially if the devices operation may be adversely affected by slow rise and fall times. For example, Figure 3-43 shows how the minimum input pulse width for an SR latch (discussed in Section 7.2.1) might be specified.
S or R
tpw(min)
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In addition, a manufacturer may specify absolute maximum input rise and fall times that must be satisfied to guarantee proper operation. High-speed CMOS circuits may consume excessive current or oscillate if their input transitions are too slow.
3.6.3 Power Consumption The power consumption of a CMOS circuit whose output is not changing is called static power dissipation or quiescent power dissipation. (The words consumption and dissipation are used pretty much interchangeably when discussing how much power a device uses.) Most CMOS circuits have very low static power dissipation. This is what makes them so attractive for laptop computers and other low-power applicationswhen computation pauses, very little power is consumed. A CMOS circuit consumes significant power only during transitions; this is called dynamic power dissipation. One source of dynamic power dissipation is the partial short-circuiting of the CMOS output structure. When the input voltage is not close to one of the power supply rails (0 V or VCC), both the p-channel and n-channel output transistors may be partially on, creating a series resistance of 600 or less. In this case, current flows through the transistors from VCC to ground. The amount of power consumed in this way depends on both the value of VCC and the rate at which output transitions occur, according to the formula P T = C PD V CC f
2
The following variables are used in the formula:
PT The circuits internal power dissipation due to output transitions. VCC The power supply voltage. As all electrical engineers know, power dissipation across a resistive load (the partially-on transistors) is proportional to the square of the voltage. f The transition frequency of the output signal. This specifies the number of power-consuming output transitions per second. (But note that frequency is defined as the number of transitions divided by 2.) CPD The power dissipation capacitance. This constant, normally specified by the device manufacturer, completes the formula. CPD turns out to have units of capacitance, but does not represent an actual output capacitance. Rather, it embodies the dynamics of current flow through the changing output-transistor resistances during a single pair of output transitions, HIGH-to-LOW and LOW-to-HIGH. For example, CPD for HC-series CMOS gates is typically 2024 pF, even though the actual output capacitance is much less. The PT formula is valid only if input transitions are fast enough, leading to fast output transitions. If the input transitions are too slow, then the output
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quiescent power dissipation dynamic power dissipation transition frequency power dissipation capacitance
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2 P L = C L ( V CC /2 ) 2 f 2 = C L V CC f
transistors stay partially on for a longer time, and power consumption increases. Device manufacturers usually recommend a maximum input rise and fall time, below which the value specified for CPD is valid. A second, and often more significant, source of CMOS power consumption is the capacitive load (CL) on the output. During a LOW-to-HIGH transition, current flows through a p-channel transistor to charge CL. Likewise, during a HIGH -to-LOW transition, current flows through an n-channel transistor to discharge CL. In each case, power is dissipated in the on resistance of the transistor. Well use PL to denote the total amount of power dissipated by charging and discharging CL. The units of PL are power, or energy usage per unit time. The energy for one transition could be determined by calculating the current through the charging transistor as a function of time (using the RC time constant as in Section 3.6.1), squaring this function, multiplying by the on resistance of the charging transistor, and integrating over time. An easier way is described below. During a transition, the voltage across the load capacitance CL changes by VCC. According to the definition of capacitance, the total amount of charge that must flow to make a voltage change of VCC across CL is C L V CC . The total amount of energy used in one transition is charge times the average voltage change. The first little bit of charge makes a voltage change of VCC, while the last bit of charge makes a vanishingly small voltage change, hence the average 2 change is VCC/2. The total energy per transition is therefore C L V CC /2 . If there are 2f transitions per second, the total power dissipated due to the capacitive load is
The total dynamic power dissipation of a CMOS circuit is the sum of PT and PL: P D = P T + PL
2 2 = C PD V CC f + C L V CC f
2 = ( C PD + C L ) V CC f
Based on this formula, dynamic power dissipation is often called CV 2f power. In most applications of CMOS circuits, CV2f power is by far the major contributor to total power dissipation. Note that CV2f power is also consumed by bipolar logic circuits like TTL and ECL, but at low to moderate frequencies it is insignificant compared to the static (DC or quiescent) power dissipation of bipolar circuits.
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3.7 Other CMOS Input and Output Structures
Circuit designers have modified the basic CMOS circuit in many ways to produce gates that are tailored for specific applications. This section describes some of the more common variations in CMOS input and output structures.
3.7.1 Transmission Gates A p-channel and n-channel transistor pair can be connected together to form a logic-controlled switch. Shown in Figure 3-44(a), this circuit is called a CMOS transmission gate. A transmission gate is operated so that its input signals EN and /EN are always at opposite levels. When EN is HIGH and /EN is LOW, there is a lowimpedance connection (as low as 25 ) between points A and B. When EN is LOW and /EN is HIGH, points A and B are disconnected. Once a transmission gate is enabled, the propagation delay from A to B (or vice versa) is very short. Because of their short delays and conceptual simplicity, transmission gates are often used internally in larger-scale CMOS devices such as multiplexers and flip-flops. For example, Figure 3-45 shows how transmission gates can be used to create a 2-input multiplexer. When S is LOW, the X input is connected to the Z output; when S is HIGH, Y is connected to Z.
VCC
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Y S
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normally complementary A B
Figure 3-44 CMOS transmission gate.
EN
transmission gate
Figure 3-45 Two-input multiplexer using CMOS transmission gates.
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Schmitt-trigger input
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Figure 3-46 A Schmitt-trigger inverter: (a) inputoutput transfer characteristic; (b) logic symbol.
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VOUT (a) 5.0 VT VT+ (b) 0.0 2.1 2.9 5.0 VIN
At least one commercial manufacturer (Quality Semiconductor) makes a variety of logic functions based on transmission gates. In their multiplexer devices, it takes several nanoseconds for a change in the select inputs (such as in Figure 3-45) to affect the input-output path (X or Y to Z). Once a path is set up, however, the propagation delay from input to output is specified to be at most 0.25 ns; this is the fastest discrete CMOS multiplexer you can buy.
3.7.2 Schmitt-Trigger Inputs The input-output transfer characteristic for a typical CMOS gate was shown in Figure 3-25 on page 96. The corresponding transfer characteristic for a gate with Schmitt-trigger inputs is shown in Figure 3-46(a). A Schmitt trigger is a special circuit that uses feedback internally to shift the switching threshold depending on whether the input is changing from LOW to HIGH or from HIGH to LOW. For example, suppose the input of a Schmitt-trigger inverter is initially at 0 V, a solid LOW. Then the output is HIGH, close to 5.0 V. If the input voltage is increased, the output will not go LOW until the input voltage reaches about 2.9 V. However, once the output is LOW, it will not go HIGH again until the input is decreased to about 2.1 V. Thus, the switching threshold for positive-going input changes, denoted VT+, is about 2.9 V, and for negative-going input changes, denoted VT, is about 2.1 V. The difference between the two thresholds is called hysteresis. The Schmitt-trigger inverter provides about 0.8 V of hysteresis. To demonstrate the usefulness of hysteresis, Figure 3-47(a) shows an input signal with long rise and fall times and about 0.5 V of noise on it. An ordinary inverter, without hysteresis, has the same switching threshold for both positivegoing and negative-going transitions, VT 2.5 V. Thus, the ordinary inverter responds to the noise as shown in (b), producing multiple output changes each time the noisy input voltage crosses the switching threshold. However, as shown in (c), a Schmitt-trigger inverter does not respond to the noise, because its hysteresis is greater than the noise amplitude.
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(a)
(b)
(c)
Figure 3-47 Device operation with slowly changing inputs: (a) a noisy, slowly changing input; (b) output produced by an ordinary inverter; (c) output produced by an inverter with 0.8 V of hysteresis.
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5.0 VT+ = 2.9 VT = 2.5 VT= 2.1 0 t VOUT HIGH LOW t VOUT HIGH LOW t
FIXING YOUR TRANSMISSION
Schmitt-trigger inputs have better noise immunity than ordinary gate inputs for signals that contain transmission-line reflections, discussed in Section 12.4, or that have long rise and fall times. Such signals typically occur in physically long connections, such as input-output buses and computer interface cables. Noise immunity is important in these applications because long signal lines are more likely to have reflections or to pick up noise from adjacent signal lines, circuits, and appliances.
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high impedance state Hi-Z state floating state three-state output tri-state output
three-state bus
three-state buffer
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(a) (b) EN A B C D L L H H L H L H H H L L H H H L L L H L Q1 EN C Q2 OUT off off on off A B D Q1 (c) EN A
Q2 OUT
off Hi-Z off Hi-Z off L on H
OUT
Figure 3-48 CMOS three-state buffer: (a) circuit diagram; (b) function table; (c) logic symbol.
3.7.3 Three-State Outputs Logic outputs have two normal states, LOW and HIGH, corresponding to logic values 0 and 1. However, some outputs have a third electrical state that is not a logic state at all, called the high impedance, Hi-Z, or floating state. In this state, the output behaves as if it isnt even connected to the circuit, except for a small leakage current that may flow into or out of the output pin. Thus, an output can have one of three stateslogic 0, logic 1, and Hi-Z. An output with three possible states is called (surprise!) a three-state output or, sometimes, a tri-state output. Three-state devices have an extra input, usually called output enable or output disable, for placing the devices output(s) in the high-impedance state. A three-state bus is created by wiring several three-state outputs together. Control circuitry for the output enables must ensure that at most one output is enabled (not in its Hi-Z state) at any time. The single enabled device can transmit logic levels (HIGH and LOW) on the bus. Examples of three-state bus design are given in Section 5.6. A circuit diagram for a CMOS three-state buffer is shown in Figure 3-48(a). To simplify the diagram, the internal NAND, NOR, and inverter functions are shown in functional rather than transistor form; they actually use a total of 10 transistors (see Exercise 3.79). As shown in the function table (b), when the enable (EN) input is LOW, both output transistors are off, and the output is in the Hi-Z state. Otherwise, the output is HIGH or LOW as controlled by
LEGAL NOTICE
TRI-STATE is a trademark of National Semiconductor Corporation. Their lawyer thought youd like to know.
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the data input A. Logic symbols for three-state buffers and gates are normally drawn with the enable input coming into the top, as shown in (c). In practice, the three-state control circuit may be different from what we have shown, in order to provide proper dynamic behavior of the output transistors during transitions to and from the Hi-Z state. In particular, devices with three-state outputs are normally designed so that the output-enable delay (Hi-Z to LOW or HIGH) is somewhat longer than the output-disable delay (LOW or HIGH to Hi-Z). Thus, if a control circuit activates one devices output-enable input at the same time that it deactivates a seconds, the second device is guaranteed to enter the Hi-Z state before the first places a HIGH or LOW level on the bus. If two three-state outputs on the same bus are enabled at the same time and try to maintain opposite states, the situation is similar to tying standard activepull-up outputs together as in Figure 3-56 on page 129a nonlogic voltage is produced on the bus. If fighting is only momentary, the devices probably will not be damaged, but the large current drain through the tied outputs can produce noise pulses that affect circuit behavior elsewhere in the system. There is a leakage current of up to 10 A associated with a CMOS threestate output in its Hi-Z state. This current, as well as the input currents of receiving gates, must be taken into account when calculating the maximum number of devices that can be placed on a three-state bus. That is, in the LOW or HIGH state, an enabled three-state output must be capable of sinking or sourcing up to 10 A of leakage current for every other three-state output on the bus, as well as handling the current required by every input on the bus. As with standard CMOS logic, separate LOW-state and HIGH-state calculations must be made to ensure that the fanout requirements of a particular circuit configuration are met.
*3.7.4 Open-Drain Outputs The p-channel transistors in CMOS output structures are said to provide active pull-up, since they actively pull up the output voltage on a LOW-to-HIGH transition. These transistors are omitted in gates with open-drain outputs, such as the NAND gate in Figure 3-49(a). The drain of the topmost n-channel transistor is left unconnected internally, so if the output is not LOW it is open, as indicated in (b). The underscored diamond in the symbol in (c) is sometimes used to indicate an open-drain output. A similar structure, called an open-collector output, is provided in TTL logic families as described in Section 3.10.5. An open-drain output requires an external pull-up resistor to provide passive pull-up to the HIGH level. For example, Figure 3-50 shows an opendrain CMOS NAND gate, with its pull-up resistor, driving a load. For the highest possible speed, an open-drain outputs pull-up resistor should be as small as possible; this minimizes the RC time constant for LOW-to* Throughout this book, optional sections are marked with an asterisk.
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Figure 3-49 Open-drain CMOS NAND g ate: (a) circuit diagram; (b) function table; (c) logic symbol.
ooze
Figure 3-50 Open-drain CMOS NAND g ate driving a load.
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AB Q1 Q2 Z Z A Q1 L L H H L H L H off off on on off on off on open open open L B Q2 (c) A B Z pull-up resistor +5 V R = 1.5 k A B Z C open-drain output D E
HIGH transitions (rise time). However, the pull-up resistance cannot be
arbitrarily small; the minimum resistance is determined by the open-drain outputs maximum sink current, IOLmax. For example, in HC- and HCT-series CMOS, IOLmax is 4 mA, and the pull-up resistor can be no less than 5.0 V/4 mA, or 1.25 k. Since this is an order of magnitude greater than the on resistance of the p-channel transistors in a standard CMOS gate, the LOW-to-HIGH output transitions are much slower for an open-drain gate than for standard gate with active pull-up. As an example, let us assume that the open-drain gate in Figure 3-50 is HC-series CMOS, the pull-up resistance is 1.5 k, and the load capacitance is 100 pF. We showed in Section 3.5.2 that the on resistance of an HC-series CMOS output in the LOW state is about 80 , Thus, the RC time constant for a HIGH -to-LOW transition is about 80 100 pF = 8 ns, and the outputs fall time is about 8 ns. However, the RC time constant for a LOW-to-HIGH transition is about 1.5 k 100 pF = 150 ns, and the rise time is about 150 ns. This relatively slow rise time is contrasted with the much faster fall time in Figure 3-51. A friend of the author calls such slow rising transitions ooze.
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Figure 3-51 Rising and falling transitions of an open-drain CMOS output.
So why use open-drain outputs? Despite slow rise times, they can be useful in at least three applications: driving light-emitting diodes (LEDs) and other devices; performing wired logic; and driving multisource buses.
*3.7.5 Driving LEDs An open-drain output can drive an LED as shown in Figure 3-52. If either input A or B is LOW, the corresponding n-channel transistor is off and the LED is off. When A and B are both HIGH, both transistors are on, the output Z is LOW, and the LED is on. The value of the pull-up resistor R is chosen so that the proper amount of current flows through the LED in the on state. Typical LEDs require 10 mA for normal brightness. HC- and HCT-series CMOS outputs are only specified to sink or source 4 mA and are not normally used to drive LEDs. However, the outputs in advanced CMOS families such as 74AC and 74ACT can sink 24 mA or more, and can be used quite effectively to drive LEDs.
VCC
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5V 3.5 V 1.5 V 0V 0 50 100 150 200 250 300 time tf tr ILED = 10 mA R
Figure 3-52 Driving an LED with an open-drain output.
LED
Z
VOLmax = 0.37 V
A
Q1
B
Q2
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Using the above information, we can write the following equation: V OL + V LED + ( I LED R ) = V CC V CC V OL V LED R = ------------------------------------------I LED = ( 5.0 0.37 1.6 ) V/10 mA = 303
RESISTOR VALUES Copyright 1999 by John F. Wakerly
Three pieces of information are needed to calculate the proper value of the pull-up resistor R: 1. The LED current ILED needed for the desired brightness, 10 mA for typical LEDs. 2. The voltage drop VLED across the LED in the on condition, about 1.6 V for typical LEDs. 3. The output voltage VOL of the open-drain output that sinks the LED current. In the 74AC and 74ACT CMOS families, VOLmax is 0.37 V. If an output can sink ILED and maintain a lower voltage, say 0.2 V, then the calculation below yields a resistor value that is a little too low, but normally with no harm done. A little more current than ILED will flow and the LED will be just a little brighter than expected.
Assuming VCC = 5.0 V and the other typical values above, we can solve for the required value of R:
Note that you dont have to use an open-drain output to drive an LED. Figure 3-53(a) shows an LED driven by ordinary an CMOS NAND-gate output with active pull-up. If both inputs are HIGH, the bottom (n-channel) transistors pull the output LOW as in the open-drain version. If either input is LOW, the output is HIGH; although one or both of the top (p-channel) transistors is on, no current flows through the LED. With some CMOS families, you can turn an LED on when the output is in the HIGH state, as shown in Figure 3-53(b). This is possible if the output can source enough current to satisfy the LEDs requirements. However, method (b) isnt used as often as method (a), because most CMOS and TTL outputs cannot source as much current in the HIGH state as they can sink in the LOW state.
In most applications, the precise value of LED series resistors is unimportant, as long as groups of nearby LEDs have similar drivers and resistors to give equal apparent brightness. In the example in this subsection, one might use an off-the-shelf resistor value of 270, 300, or 330 ohms, whatever is readily available.
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(a)
A
B
Figure 3-53 Driving an LED with an ordinary CMOS output: (a) sinking current, on in the LOW state; (b) sourcing current, on in the HIGH state.
*3.7.6 Multisource Buses Open-drain outputs can be tied together to allow several devices, one at a time, to put information on a common bus. At any time all but one of the outputs on the bus are in their HIGH (open) state. The remaining output either stays in the HIGH state or pulls the bus LOW, depending on whether it wants to transmit a logical 1 or a logical 0 on the bus. Control circuitry selects the particular device that is allowed to drive the bus at any time. For example, in Figure 3-54, eight 2-input open-drain NAND-gate outputs drive a common bus. The top input of each NAND gate is a data bit, and the
Figure 3-54 Eight open-drain outputs driving a bus.
VCC
Data1 Enable1 Data2 Enable2
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(b) R Q2 Q4 Q2 Q4 LED Z Z Q1 A Q1 R Q3 B Q3 LED
open-drain bus
R
DATAOUT
Data3 Enable3 Data4 Enable4
Data5 Enable5 Data6 Enable6
Data7 Enable7 Data8 Enable8
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wired AND
fighting
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VCC VCC A Q1 VCC R B Q2 C Q1 D Q2 E Q1 2-input open-drain NAND gates F Q2
Z
Figure 3-55 Wired-AND function on three open-drain NAND-gate outputs.
bottom input of each is a control bit. At most one control bit is HIGH at any time, enabling the corresponding data bit to be passed through to the bus. (Actually, the complement of the data bit is placed on the bus.) The other gate outputs are HIGH , that is, open, so the data input of the enabled gate determines the value on the bus. *3.7.7 Wired Logic If the outputs of several open-drain gates are tied together with a single pull-up resistor, then wired logic is performed. (Thats wired, not weird!) An AND function is obtained, since the wired output is HIGH if and only if all of the individual gate outputs are HIGH (actually, open); any output going LOW is sufficient to pull the wired output LOW. For example, a three-input wired AND function is shown in Figure 3-55. If any of the individual 2-input NAND gates has both inputs HIGH, it pulls the wired output LOW; otherwise, the pull-up resistor R pulls the wired output HIGH . Note that wired logic cannot be performed using gates with active pull-up. Two such outputs wired together and trying to maintain opposite logic values result in a very high current flow and an abnormal output voltage. Figure 3-56 shows this situation, which is sometimes called fighting. The exact output voltage depends on the relative strengths of the fighting transistors, but with 5-V CMOS devices it is typically about 12 V, almost always a nonlogic voltage. Worse, if outputs are left fighting continuously for more than a few seconds, the chips can get hot enough to sustain internal damage and to burn your fingers!
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*3.7.8 Pull-Up Resistors A proper choice of value for the pull-up resistor R must be made in open-drain applications. Two calculations are made to bracket the allowable values of R:
Minimum The sum of the current through R in the LOW state and the LOWstate input currents of the gates driven by the wired outputs must not exceed the LOW-state driving capability of the active output, 4 mA for HC and HCT, 24 mA for AC and ACT. Maximum The voltage drop across R in the HIGH state must not reduce the output voltage below 2.4 V, which is VIHmin for typical driven gates plus a 400-mV noise margin. This drop is produced by the HIGH-state output leakage current of the wired outputs and the HIGH-state input currents of the driven gates.
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trying to pull HIGH Q2 Q4 Z HIGH Q1 LOW Q3 VCC I 5V 20 mA Rp(on) + Rn(on) (HC or HCT) Q2 Q4 HIGH Q1 HIGH Q3 trying to pull LOW
Figure 3-56 Two CMOS outputs trying to maintain opposite logic values on the same line.
pull-up resistor calculation
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HCT open-drain NAND gates VCC = +5 V
Figure 3-57 Four open-drain outputs driving two inputs in the LOW state.
Figure 3-58 Four open-drain outputs driving two inputs in the HIGH state.
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LOW LOW 3.2 mA LOW LOW R 0.4 mA 0.4 V LOW LOW LS-TTL gates 0.4 mA 4 mA HIGH HIGH
For example, suppose that four HCT open-drain outputs are wired together and drive two LS-TTL inputs (Section 3.11) as shown in Figure 3-57. A LOW output must sink 0.4 mA from each LS-TTL input as well as sink the current through the pull-up resistor R. For the total current to stay within the HCT IOLmax spec of 4 mA, the current through R may be no more than I R(max) = 4 ( 2 0.4 ) = 3.2 mA
HCT open-drain NAND gates VCC = +5 V
HIGH HIGH
5 A
60 A
HIGH HIGH
R
20 A
5 A
2.4 V
HIGH HIGH
LS-TTL gates
20 A
5 A
HIGH HIGH
5 A
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Assuming that VOL of the open-drain output is 0.0 V, the minimum value of R is R min = ( 5.0 0.0 ) / I R(max) = 1562.5
In the HIGH state, typical open-drain outputs have a maximum leakage current of 5 A, and typical LS-TTL inputs require 20 A of source current. Hence, the H IGH-state current requirement as shown in Figure 3-58 is I R(leak) = ( 4 5 ) + ( 2 20 ) = 60 A
This current produces a voltage drop across R, and must not lower the output voltage below VOHmin = 2.4 V; thus the maximum value of R is R max = ( 5.0 2.4 ) / I R(leak) = 43.3 Hence, any value of R between 1562.5 and 43.3 k may be used. Higher values reduce power consumption and improve the LOW-state noise margin, while lower values increase power consumption but improve both the HIGH-state noise margin and the speed of LOW-to-HIGH output transitions.
3.8 CMOS Logic Families
The first commercially successful CMOS family was 4000-series CMOS. Although 4000-series circuits offered the benefit of low power dissipation, they were fairly slow and were not easy to interface with the most popular logic family of the time, bipolar TTL. Thus, the 4000 series was supplanted in most applications by the more capable CMOS families discussed in this section. All of the CMOS devices that we discuss have part numbers of the form 74FAMnn, where FAM is an alphabetic family mnemonic and nn is a numeric function designator. Devices in different families with the same value of nn perform the same function. For example, the 74HC30, 74HCT30, 74AC30, 74ACT30, and 74AHC30 are all 8-input NAND gates. The prefix 74 is simply a number that was used by an early, popular supplier of TTL devices, Texas Instruments. The prefix 54 is used for identical parts that are specified for operation over a wider range of temperature and power-supply voltage, for use in military applications. Such parts are usually
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OPEN-DRAIN ASSUMPTION In our open-drain resistor calculations, we assume that the output voltage can be as low as 0.0 V rather than 0.4 V (VOLmax) in order to obtain a worst-case result. That is, even if the open-drain output is so strong that it can pull the output voltage all the way down to 0.0 V (its only required to pull down to 0.4 V), well never allow it to sink more than 4 mA, so it doesnt get overstressed. Some designers prefer to use 0.4 V in this calculation, figuring that if the output is so good that it can pull low er than 0.4 V, a little bit of excess sink current beyond 4 mA wont hurt it. 4000-series CMOS
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HC (High-speed CMOS)
HCT (High-speed CMOS, TTL compatible)
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HC Logic Levels HIGH VCC = 5.0 V VOHminT = 3.84V VIHmin = 3.5 V VILmax = 1.5 V HIGH ABNORMAL LOW (a) ABNORMAL LOW (b) VIHmin = 2.0 V 0.0 V VOLmaxT = 0.33 V 0.0 V VOUT 5.0
VOHminT = 3.84V
VILmax = 0.8 V VOLmaxT = 0.33 V
Figure 3-59 Input and output levels for CMOS devices using a 5-V supply: (a) HC; (b) HCT.
fabricated in the same way as their 74-series counterparts, except that they are tested, screened, and marked differently, a lot of extra paperwork is generated, and a higher price is charged, of course.
3.8.1 HC and HCT The first two 74-series CMOS families are HC (High-speed CMOS) and HCT (High-speed CMOS, TTL compatible). Compared with the original 4000 family, HC and HCT both have higher speed and better current sinking and sourcing capability. The HCT family uses a power supply voltage VCC of 5 V and can be intermixed with TTL devices, which also use a 5-V supply. The HC family is optimized for use in systems that use CMOS logic exclusively, and can use any power supply voltage between 2 and 6 V. A higher voltage is used for higher speed, and a lower voltage for lower power dissipation. Lowering the supply voltage is especially effective, since most CMOS power dissipation is proportional to the square of the voltage (CV2f power). Even when used with a 5-V supply, HC devices are not quite compatible with TTL. In particular, HC circuits are designed to recognize CMOS input levels. Assuming a supply voltage of 5.0 V, Figure 3-59(a) shows the input and output levels of HC devices. The output levels produced by TTL devices do not quite match this range, so HCT devices use the different input levels shown in (b). These levels are established in the fabrication process by making transistors with different switching thresholds, producing the different transfer characteristics shown in Figure 3-60.
Figure 3-60 Transfer characteristics of HC and HCT circuits under typical conditions.
HCT HC
0
0
1.4
2.5
5.0
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Well have more to say about CMOS/TTL interfacing in Section 3.12. For now, it is useful simply to note that HC and HCT are essentially identical in their output specifications; only their input levels differ.
3.8.2 VHC and VHCT Several new CMOS families were introduced in the 1980s and the 1990s. Two of the most recent and probably the most versatile are VHC (Very High-Speed CMOS) and VHCT (Very High-Speed CMOS, TTL compatible). These families are about twice as fast as HC/HCT while maintaining backwards compatibility with their predecessors. Like HC and HCT, the VHC and VHCT families differ from each other only in the input levels that they recognize; their output characteristics are the same. Also like HC/HCT, VHC/VHCT outputs have symmetric output drive. That is, an output can sink or source equal amounts of current; the output is just as strong in both states. Other logic families, including the FCT and TTL families introduced later, have asymmetric output drive; they can sink much more current in the LOW state than they can source in the HIGH state.
3.8.3 HC, HCT, VHC, and VHCT Electrical Characteristics Electrical characteristics of the HC, HCT, VHC, and VHCT families are summarized in this subsection. The specifications assume that the devices are used with a nominal 5-V power supply, although (derated) operation is possible with any supply voltage in the range 25.5 V (up to 6 V for HC/HCT). Well take a closer look at low-voltage and mixed-voltage operation in Section 3.13. Commercial (74-series) parts are intended to be operated at temperatures between 0C and 70C, while military (54-series) parts are characterized for operation between 55C and 125C. The specs in Table 3-5 assume an operating temperature of 25 C. A full manufacturers data sheet provides additional specifications for device operation over the entire temperature range. Most devices within a given logic family have the same electrical specifications for inputs and outputs, typically differing only in power consumption and propagation delay. Table 3-5 includes specifications for a 74x00 two-input NAND gate and a 74x138 3-to-8 decoder in the HC, HCT, VHC, and VHCT families. The 00 NAND gate is included as the smallest logic-design building block in each family, while the 138 is a medium-scale part containing the equivalent of about 15 NAND gates. (The 138 spec is included to allow comparison with
VERY=ADVANCED, SORT OF
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VHCT (Very Highspeed CMOS, TTL compatible) The VHC and VHCT logic families are manufactured by several companies, including Motorola, Fairchild, and Toshiba. Compatible families with similar but not identical specifications are manufactured by Texas Instruments and Philips; they are called AHC and AHCT, where the A stands for Advanced. Copying Prohibited
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Ta b l e 3 - 5 Speed and power characteristics of CMOS families operating at 5 V
Family Description Part Symbol Condition HC HCT VHC
VHCT
Typical propagation delay (ns) Quiescent power-supply current (A)
00 138 00 138
tPD
9 18
10 20
5.2 7.2
5.5 8.1
ICC
Vin = 0 or VCC Vin = 0 or VCC
2.5 40
2.5 40
5.0 40
5.0 402
Quiescent power dissipation (mW)
00 138
Vin = 0 or VCC Vin = 0 or VCC
0.0125 0.2 22 55
0.0125 0.2 15 51
0.025 0.2 19 34
0.025 0.2 17 49
Power dissipation capacitance (pF)
00 138
CPD CPD
Dynamic power dissipation (mW/MHz)
00 138
0.55 1.38
0.38 1.28
0.48 0.85
0.43 1.23
Total power dissipation (mW)
00 00 00 138 138 138
f = 100 kHz f = 1 MHz f = 10 MHz f = 100 kHz f = 1 MHz f = 10 MHz
0.068 0.56 5.5 0.338 1.58 14.0
0.050 0.39 3.8 0.328 1.48 13.0 0.50 3.9 38 6.55 29.5 259
0.073 0.50 4.8 0.285 1.05 8.7
0.068 0.45 4.3 0.323 1.43 12.5 0.37 2.5 24 2.61 11.5 101
Speed-power product (pJ)
00 00 00 138 138 138
f = 100 kHz f = 1 MHz f = 10 MHz f = 100 kHz f = 1 MHz f = 10 MHz
0.61 5.1 50 6.08 28.4 251
0.38 2.6 25 2.05 7.56 63
the faster FCT family in Section 3.8.4; 00 gates are not manufactured in the FCT family.) The first row of Table 3-5 specifies propagation delay. As discussed in Section 3.6.2, two numbers, tpHL and tpLH may be used to specify delay; the number in the table is the worst-case of the two. Skipping ahead to Table 3-11 on page 163, you can see that HC and HCT are about the same speed as LS TTL, and that VHC and VHCT are almost as fast as ALS TTL. The propagation delay
NOTE ON NOTATION
The x in the notation74x00 takes the place of a family designator such as HC, HCT, VHC, VHCT, FCT, LS, ALS, AS, or F. We may also refer to such a generic part simply as a 00 and leave off the 74x.
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QUIETLY GETTING MORE DISSED
for the 138 is somewhat longer than for the 00, since signals must travel through three or four levels of gates internally. The second and third rows of the table show that the quiescent power dissipation of these CMOS devices is practically nil, well under a milliwatt (mW) if the inputs have CMOS levels0 V for LOW and VCC for HIGH. (Note that in the table, the quiescent power dissipation numbers given for the 00 are per gate, while for the 138 they apply to the entire MSI device.) As we discussed in Section 3.6.3, the dynamic power dissipation of a CMOS gate depends on the voltage swing of the output (usually VCC), the output transition frequency (f ), and the capacitance that is being charged and discharged on transitions, according to the formula P D = ( C L + C PD ) V2 f DD
Here, CPD is the power dissipation capacitance of the device and CL is the capacitance of the load attached to the CMOS output in a given application. The table lists both CPD and an equivalent dynamic power dissipation factor in units of milliwatts per megahertz, assuming that CL = 0. Using this factor, the total power dissipation is computed at various frequencies as the sum of the dynamic power dissipation at that frequency and the quiescent power dissipation. Shown next in the table, the speed-power product is simply the product of the propagation delay and power consumption of a typical gate; the result is measured in picojoules (pJ). Recall from physics that the joule is a unit of energy, so the speed-power product measures a sort of efficiencyhow much energy a logic gate uses to switch its output. In this day and age, its obvious that the lower the energy usage, the better.
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HCT and VHCT circuits can also be driven by TTL devices, which may produce HIGH output levels as low as 2.4 V. As we explained in Section 3.5.3, a CMOS output may draw additional current from the power supply if any of the inputs are nonideal. In the case of an HCT or VHCT inverter with a HIGH input of 2.4 V, the bottom, n-channel output transistor is fully on. However, the top, p-channel transistor is also partially on. This allows the additional quiescent current flow, specified as ICC or ICCT in the data sheet, which can be as much as 23 mA per nonideal input in HCT and VHCT devices. speed-power product SAVING ENERGY There are practical as well as geopolitical reasons for saving energy in digital systems. Lower energy consumption means lower cost of power supplies and cooling systems. Also, a digital systems reliability is improved more by running it cooler than by any other single reliability improvement strategy. Copying Prohibited
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Ta b l e 3 - 6 Input specifications for CMOS families with VCC between 4.5 and 5.5 V.
Family Description Symbol Condition HC HCT VHC
VHCT
Input leakage current (A)
IImax
Vin = any
1
1 10
1
1 10
Maximum input capacitance (pF) CINmax VILmax
10
10
LOW-level input voltage (V)
1.35 3.85
0.8 2.0
1.35 3.85
0.8 2.0
HIGH-level input voltage (V)
VIHmin
Table 3-6 gives the input specs of typical CMOS devices in each of the families. Some of the specs assume that the 5-V supply has a 10% margin; that is, VCC can be anywhere between 4.5 and 5.5 V. These parameters were discussed in previous sections, but for reference purposes their meanings are summarized here: IImax The maximum input current for any value of input voltage. This spec states that the current flowing into or out of a CMOS input is 1 A or less for any value of input voltage. In other words, CMOS inputs create almost no DC load on the circuits that drive them. CINmax The maximum capacitance of an input. This number can be used when figuring the AC load on an output that drives this and other inputs. Most manufacturers also specify a lower, typical input capacitance of about 5 pF, which gives a good estimate of AC load if youre not unlucky. VILmax The maximum voltage that an input is guaranteed to recognize as LOW. Note that the values are different for HC/VHC versus HCT/VHCT. The CMOS value, 1.35 V, is 30% of the minimum power-supply voltage, while the TTL value is 0.8 V for compatibility with TTL families.
CMOS VS. TTL POWER DISSIPATION
At high transition frequencies (f ), CMOS families actually use more power than TTL. For example, compare HCT CMOS in Table 3-5 at f = 10 MHz with LS TTL in Table 3-11; a CMOS gate uses three times as much power as a TTL gate at this frequency. Both HCT and LS may be used in systems with maximum clock frequencies of up to about 20 MHz, so you might think that CMOS is not so good for high-speed systems. However, the transition frequencies of most outputs in typical systems are much less than the maximum frequency present in the system (e.g., see Exercise 3.76). Thus, typical CMOS systems have a lower total power dissipation than they would have if they were built with TTL.
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LOW-level output current (mA) LOW-level output voltage (V)
HIGH-level output current (mA) HIGH-level output voltage (V)
VIHmin The minimum voltage that an input is guaranteed to recognize as HIGH. The CMOS value, 3.85 V, is 70% of the maximum power-supply voltage, while the TTL value is 2.0 V for compatibility with TTL families. (Unlike CMOS levels, TTL input levels are not symmetric with respect to the power-supply rails.)
The specifications for TTL-compatible CMOS outputs usually have two sets of output parameters; one set or the other is used depending on how an output is loaded. A CMOS load is one that requires the output to sink and source very little DC current, 20 A for HC/HCT and 50 A for VHC/VHCT. This is, of course, the case when the CMOS outputs drive only CMOS inputs. With CMOS loads, CMOS outputs maintain an output voltage within 0.1 V of the supply rails, 0 and VCC. (A worst-case VCC = 4.5 V is used for the table entries; hence, VOHminC = 4.4 V.) A TTL load can consume much more sink and source current, up to 4 mA from and HC/HCT output and 8 mA from a VHC/VHCT output. In this case, a higher voltage drop occurs across the on transistors in the output circuit, but the output voltage is still guaranteed to be within the normal range of TTL output levels. Table 3-7 lists CMOS output specifications for both CMOS and TTL loads. These parameters have the following meanings: IOLmaxC The maximum current that an output can supply in the LOW state while driving a CMOS load. Since this is a positive value, current flows into the output pin. IOLmaxT The maximum current that an output can supply in the LOW state while driving a TTL load.
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Ta b l e 3 - 7 Output specifications for CMOS families operating with VCC between 4.5 and 5.5 V.
Family Description Symbol Condition HC HCT VHC VHCT
IOLmaxC IOLmaxT
CMOS load TTL load
0.02 4.0
0.02 4.0
0.05 8.0
0.05 8.0
VOLmaxC VOLmaxT IOHmaxC IOHmaxT
Iout IOLmaxC Iout IOLmaxT CMOS load TTL load
0.1 0.33
0.1 0.33
0.1 0.44
0.1 0.44
0.02 4.0 4.4 3.84
0.02 4.0 4.4 3.84
0.05 8.0 4.4 3.80
0.05 8.0 4.4 3.80
VOHminC VOHminT
|Iout ||IOHmaxC| |Iout ||IOHmaxT|
CMOS load
TTL load
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FCT (Fast CMOS, TTL compatible)
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VOLmaxC The maximum voltage that a LOW output is guaranteed to produce while driving a CMOS load, that is, as long as IOLmaxC is not exceeded. VOLmaxT The maximum voltage that a LOW output is guaranteed to produce while driving a TTL load, that is, as long as IOLmaxT is not exceeded. IOHmaxC The maximum current that an output can supply in the HIGH state while driving a CMOS load. Since this is a negative value, positive current flows out of the output pin. IOHmaxT The maximum current that an output can supply in the HIGH state while driving a TTL load. VOHminC The minimum voltage that a HIGH output is guaranteed to produce while driving a CMOS load, that is, as long as IOHmaxC is not exceeded. VOHminT The minimum voltage that a HIGH output is guaranteed to produce while driving a TTL load, that is, as long as IOHmaxT is not exceeded.
The voltage parameters above determine DC noise margins. The LOWstate DC noise margin is the difference between VOLmax and VILmax. This depends on the characteristics of both the driving output and the driven inputs. For example, the LOW-state DC noise margin of a HCT driving a few HCT inputs (a CMOS load) is 0.8 0.1 = 0.7 V. With a TTL load, the noise margin for the HCT inputs drops to 0.8 0.33 = 0.47 V. Similarly, the HIGH -state DC noise margin is the difference between VOHmin and VIHmin. In general, when different families are interconnected, you have to compare the appropriate VOLmax and VOHmin of the driving gate with VILmax and VIHmin of all the driven gates to determine the worst-case noise margins. The IOLmax and IOHmax parameters in the table determine fanout capability, and are especially important when an output drives inputs in one or more different families. Two calculations must be performed to determine whether an output is operating within its rated fanout capability:
HIGH -state fanout The IIHmax values for all of the driven inputs are added. The
sum must be less than IOHmax of the driving output. LOW-state fanout The IILmax values for all of the driven inputs are added. The sum must be less than IOLmax of the driving output
Note that the input and output characteristics of specific components may vary from the representative values given in Table 3-7, so you must always consult the manufacturers data sheets when analyzing a real design. *3.8.4 FCT and FCT-T In the early 1990s, yet another CMOS family was launched. The key benefit of the FCT (Fast CMOS, TTL compatible) family was its ability to meet or exceed the speed and the output drive capability of the best TTL families while reducing power consumption and maintaining full compatibility with TTL.
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The original FCT family had the drawback of producing a full 5-V CMOS VOH, creating enormous CV2f power dissipation and circuit noise as its outputs swung from 0 V to almost 5 V in high-speed (25 MHz+) applications. A variation of the family, FCT-T (Fast CMOS, TTL compatible with TTL VOH), was quickly introduced with circuit innovations to reduce the HIGH-level output voltage, thereby reducing both power consumption and switching noise while maintaining the same high operating speed as the original FCT. A suffix of T is used on part numbers to denote the FCT-T output structure, for example, 74FCT138T versus 74FCT138. The FCT-T family remains very popular today. A key application of FCT-T is driving buses and other heavy loads. Compared with other CMOS families, it can source or sink gobs of current, up to 64 mA in the LOW state.
*3.8.5 FCT-T Electrical Characteristics Electrical characteristics of the 5-V FCT-T family are summarized in Table 3-8. The family is specifically designed to be intermixed with TTL devices, so its operation is only specified with a nominal 5-V supply and TTL logic levels. Some manufacturers are beginning to sell parts with similar capabilities using a 3.3-V supply, and using the FCT designation. However, they are different devices with different part numbers. Individual logic gates are not manufactured in the FCT family. Perhaps the simplest FCT logic element is a 74FCT138T decoder, which has six inputs, eight outputs, and contains the equivalent of about a dozen 4-input gates internally. (This function is described later, in Section 5.4.4.) Comparing its propagation delay and power consumption in Table 3-8 with the corresponding HCT and VHCT numbers in Table 3-5 on page 134, you can see that the FCT-T family is superior in both speed and power dissipation. When comparing, note that FCT-T manufacturers specify only maximum, not typical propagation delays. Unlike other CMOS families, FCT-T does not have a CPD specification. Instead, it has an ICCD specification: ICCD Dynamic power supply current, in units of mA/MHz. This is the amount of additional power supply current that flows when one input is changing at the rate of 1 MHz.
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EXTREME SWITCHING Device outputs in the FCT and FCT-T families have very low impedance and as a consequence extremely fast rise and fall times. In fact, they are so fast that they are often a major source of analog problems, including switching noise and ground bounce, so extra care must be taken in the analog and physical design of printedcircuit boards using these and other extremely high-speed parts. To reduce the effects of transmission-line reflections (Section 12.4.3), another high-speed design worry, some FCT-T outputs have built-in 25- series resistors. Copying Prohibited
FCT-T (Fast CMOS, TTL compatible with TTL VOH
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Description Symbol Condition Value
Ta b l e 3 - 8 Specifications for a 74FCT138T decoder in the FCT-T logic family.
Maximum propagation delay (ns)
tPD
5.8
Quiescent power-supply current (A)
ICC
Vin = 0 or VCC
200 1.0
Quiescent power dissipation (mW)
Vin = 0 or VCC
Dynamic power supply current (mA/MHz)
ICCD
Outputs open, one input changing
0.12 2.0
Quiescent power supply current per TTL input (mA) Total power dissipation (mW)
ICC
Vin = 3.4 V
f = 100 kHz f = 1 MHz f = 10 MHz
0.60 1.06 1.6
Speed-power product (pJ)
f = 100 kHz f = 1 MHz f = 10 MHz
6.15 9.3 41
Input leakage current (A)
IImax
Vin = any
5
Typical input capacitance (pF)
LOW-level input voltage (V)
CINtyp
5
VILmax VIHmin
0.8 2.0
HIGH-level input voltage (V)
LOW-level output current (mA) LOW-level output voltage (V)
IOLmax
64
VOLmax IOHmax
Iout IOLmax
0.55
HIGH-level output current (mA) HIGH-level output voltage (V)
15 2.4 3.3
VOHmin VOHtyp
| Iout | | IOHmax | | Iout | | IOHmax |
The ICCD specification gives the same information as CPD, but in a different way. The circuits internal power dissipation due to transitions at a given frequency f can be calculated by the formula P T = V CC I CCD f
Thus, ICCD/VCC is algebraically equivalent to the CPD specification of other CMOS families (see Exercise 3.83). FCT-T also has a ICC specification for the extra quiescent current that is consumed with nonideal HIGH inputs (see box at the top of page 135).
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3.9 Bipolar Logic
Bipolar logic families use semiconductor diodes and bipolar junction transistors as the basic building blocks of logic circuits. The simplest bipolar logic elements use diodes and resistors to perform logic operations; this is called diode logic. Most TTL logic gates use diode logic internally and boost their output drive capability using transistor circuits. Some TTL gates use parallel configurations of transistors to perform logic functions. ECL gates, described in Section 3.14, use transistors as current switches to achieve very high speed. This section covers the basic operation of bipolar logic circuits made from diodes and transistors, and the next section covers TTL circuits in detail. Although TTL is the most commonly used bipolar logic family, it has been largely supplanted by the CMOS families that we studied in previous sections. Still, it is useful to study basic TTL operation for the occasional application that requires TTL/CMOS interfacing, discussed in Section 3.12. Also, an understanding of TTL may give you insight into the fortuitous similarity of logic levels that allowed the industry to migrate smoothly from TTL to 5-V CMOS logic, and now to lower-voltage, higher-performance 3.3-V CMOS logic, as described in Section 3.13. If youre not interested in all the gory details of TTL, you can skip to Section 3.11 for an overview of TTL families. 3.9.1 Diodes A semiconductor diode is fabricated from two types of semiconductor material, called p-type and n-type, that are brought into contact with each other as shown in Figure 3-61(a). This is basically the same material that is used in p-channel and n-channel MOS transistors. The point of contact between the p and n materials is called a pn junction. (Actually, a diode is normally fabricated from a single monolithic crystal of semiconductor material in which the two halves are doped with different impurities to give them p-type and n-type properties.) The physical properties of a pn junction are such that positive current can easily flow from the p-type material to the n-type. Thus, if we build the circuit shown in Figure 3-61(b), the pn junction acts almost like a short circuit. However, the physical properties also make it very difficult for positive current to
Figure 3-61 Semiconductor diodes: (a) the pn junction; (b) forward-biased junction allowing current flow; (c) reverse-biased junction blocking current flow.
R R
(a)
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diode logic semiconductor diode p-type material n-type material pn junction
(b) (c) pn I V I V/R p n I V I 0 n p
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diode action
diode
anode cathode
reverse-biased diode forward-biased diode
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I I (a) pn (b) (c) I anode + cathode V V
V
Figure 3-62 Diodes: (a) symbol; (b) transfer characteristic of an ideal diode; (c) transfer characteristic of a real diode.
flow in the opposite direction, from n to p. Thus, in the circuit of Figure 3-61(c), the pn junction behaves almost like an open circuit. This is called diode action. Although its possible to build vacuum tubes and other devices that exhibit diode action, modern systems use pn junctionssemiconductor diodeswhich well henceforth call simply diodes. Figure 3-62(a) shows the schematic symbol for a diode. As weve shown, in normal operation significant amounts of current can flow only in the direction indicated by the two arrows, from anode to cathode. In effect, the diode acts like a short circuit as long as the voltage across the anode-to-cathode junction is nonnegative. If the anode-to-cathode voltage is negative, the diode acts like an open circuit and no current flows. The transfer characteristic of an ideal diode shown in Figure 3-62(b) further illustrates this principle. If the anode-to-cathode voltage, V, is negative, the diode is said to be reverse biased and the current I through the diode is zero. If V is nonnegative, the diode is said to be forward biased and I can be an arbitrarily large positive value. In fact, V can never get larger than zero, because an ideal diode acts like a zero-resistance short circuit when forward biased. A nonideal, real diode has a resistance that is less than infinity when reverse biased, and greater than zero when forward biased, so the transfer characteristic looks like Figure 3-62(c). When forward biased, the diode acts like a
YES, THERE ARE TWO ARROWS
. . . in Figure 3-62(a). The second arrow is built into the diode symbol to help you remember the direction of current flow. Once you know this, there are many ways to remember which end is called the anode and which is the cathode. Aficionados of vacuum-tube hi-fi amplifiers may remember that electrons travel from the hot cathode to the anode, and therefore positive current flow is from anode to cathode. Those of us who were still watching Sesame Street when most vacuum tubes went out of style might like to think in terms of the alphabetcurrent flows alphabetically from A to C.
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Figure 3-63 Model of a real diode: (a) reverse biased; (b) forward biased; (c) transfer characteristic of forward-biased diode.
small nonlinear resistance; its voltage drop increases as current increases, but not strictly proportionally. When the diode is reverse biased, a small amount of negative leakage current flows. If the voltage is made too negative, the diode breaks down, and large amounts of negative current can flow; in most applications, this type of operation is avoided. A real diode can be modeled very simply as shown in Figure 3-63(a) and (b). When the diode is reverse biased, it acts like an open circuit; we ignore leakage current. When the diode is forward biased, it acts like a small resistance, Rf, in series with Vd, a small voltage source. Rf is called the forward resistance of the diode, and Vd is called a diode-drop. Careful choice of values for Rf and Vd yields a reasonable piecewise-linear approximation to the real diode transfer characteristic, as in Figure 3-63(c). In a typical small-signal diode such as a 1N914, the forward resistance Rf is about 25 and the diode-drop Vd is about 0.6 V. In order to get a feel for diodes, you should remember that a real diode does not actually contain the 0.6-V source that appears in the model. Its just that, due to the nonlinearity of the real diodes transfer characteristic, significant amounts of current do not begin to flow until the diodes forward voltage V has reached about 0.6 V. Also note that in typical applications, the 25- forward resistance of the diode is small compared to other resistances in the circuit, so that very little additional voltage drop occurs across the forward-biased diode once V has reached 0.6 V. Thus, for practical purposes, a forward-biased diode may be considered to have a fixed drop of 0.6 V or so .
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anode cathode anode cathode + V < 0.6 V + V 0.6 V Slope = 1/Rf Rf V Vd Vd = 0.6 V
leakage current diode breakdown
forward resistance diode-drop
ZENER DIODES
Zener diodes take advantage of diode breakdown, in particular the steepness of the VI slope in the breakdown region. A Zener diode can function as a voltage regulator when used with a resistor to limit the breakdown current. A wide variety of Zeners with different breakdown voltages are produced for voltage-regulator applications.
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LOW HIGH
diode AND gate
Figure 3-64 Diode AND gate: (a) electrical circuit; (b) both inputs HIGH ; (c) one input HIGH, one LOW; (d) function table; (e) truth table.
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Ta b l e 3 - 9 Logic levels in a simple diode logic system.
Signal Level Designation
LOW
Binary Logic Value
02 volts
0 1
23 volts 35 volts
noise margin
HIGH
undefined
3.9.2 Diode Logic Diode action can be exploited to perform logical operations. Consider a logic system with a 5-V power supply and the characteristics shown in Table 3-9. Within the 5-volt range, signal voltages are partitioned into two ranges, LOW and H IGH, with a 1-volt noise margin between. A voltage in the LOW range is considered to be a logic 0, and a voltage in the HIGH range is a logic 1. With these definitions, a diode AND gate can be constructed as shown in Figure 3-64(a). In this circuit, suppose that both inputs X and Y are connected to HIGH voltage sources, say 4 V, so that VX and VY are both 4 V as in (b). Then both diodes are forward biased, and the output voltage VZ is one diode-drop above 4 V, or about 4.6 V. A small amount of current, determined by the value of R, flows from the 5-V supply through the two diodes and into the 4-V sources. The colored arrows in the figure show the path of this current flow.
+5 V +5 V
(a)
(b)
R
R
X
VX
D1
VZ
Z
VX
D1
4V
ID1
VZ = 4.6 V
Y
VY
D2
4V
VY
D2
ID2
+5 V
(c)
(d)
(e)
R
VX
VY
VZ
XYZ 0 0 1 1 0 1 0 1 0 0 0 1
VX
D1
VZ = 1.6V
1V
ID1
4V
VY
D2
low low high high
low high low high
low low low high
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Now suppose that VX drops to 1 V as in Figure 3-64(c). In the diode AND gate, the output voltage equals the lower of the two input voltages plus a diodedrop. Thus, VZ drops to 1.6 V, and diode D2 is reverse biased (the anode is at 1.6 V and the cathode is still at 4 V). The single LOW input pulls down the output of the diode AND gate to a LOW value. Obviously, two LOW inputs create a LOW output as well. This functional operation is summarized in (d) and is repeated in terms of binary logic values in (e); clearly, this is an AND gate. Figure 3-65(a) shows a logic circuit with two AND gates connected together; Figure 3-65(b) shows the equivalent electrical circuit with a particular set of input values. This example shows the necessity of diodes in the AND circuit: D3 allows the output Z of the first AND gate to remain H IGH while the output C of the second AND gate is being pulled LOW by input B through D4. When diode logic gates are cascaded as in Figure 3-65, the voltage levels of the logic signals move away from the power-supply rails and towards the undefined region. Thus, in practice, a diode AND gate normally must be followed by a transistor amplifier to restore the logic levels; this is the scheme used in TTL NAND gates, described in Section 3.10.1. However, logic designers are occasionally tempted to use discrete diodes to perform logic under special circumstances; for example, see Exercise 3.94. 3.9.3 Bipolar Junction Transistors A bipolar junction transistor is a three-terminal device that, in most logic circuits, acts like a current-controlled switch. If we put a small current into one of the terminals, called the base, then the switch is oncurrent may flow between the other two terminals, called the emitter and the collector. If no current is put into the base, then the switch is offno current flows between the emitter and the collector.
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Z (a) C 0 +5 V +5 V (b) R1 R2 VX D1 VZ = 4.6V Ileak D3 VC = 1.6 V C 4V 4V VY D2 D4 1V VB
Figure 3-65 Two AND gates: (a) logic diagram; (b) electrical circuit.
bipolar junction transistor base emitter collector
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(b) C (c) C (d) C
npn transistor
pnp transistor
amplifier active region
common-emitter configuration
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n p Ic B B B n p n B base collector emitter p n Ib E E E E
Ie = Ib + Ic
Figure 3-66 Development of an npn transistor: (a) back-to-back diodes; (b) equivalent pn junctions; (c) structure of an npn transistor; (d) npn transistor symbol.
To study the operation of a transistor, we first consider the operation of a pair of diodes connected as shown in Figure 3-66(a). In this circuit, current can flow from node B to node C or node E, when the appropriate diode is forward biased. However, no current can flow from C to E, or vice versa, since for any choice of voltages on nodes B, C , and E, one or both diodes will be reverse biased. The pn junctions of the two diodes in this circuit are shown in (b). Now suppose that we fabricate the back-to-back diodes so that they share a common p-type region, as shown in Figure 3-66(c). The resulting structure is called an npn transistor and has an amazing property. (At least, the physicists working on transistors back in the 1950s thought it was amazing!) If we put current across the base-to-emitter pn junction, then current is also enabled to flow across the collector-to-base np junction (which is normally impossible) and from there to the emitter. The circuit symbol for the npn transistor is shown in Figure 3-66(d). Notice that the symbol contains a subtle arrow in the direction of positive current flow. This also reminds us that the base-to-emitter junction is a pn junction, the same as a diode whose symbol has an arrow pointing in the same direction. It is also possible to fabricate a pnp transistor, as shown in Figure 3-67. However, pnp transistors are seldom used in digital circuits, so we wont discuss them any further. The current Ie flowing out of the emitter of an npn transistor is the sum of the currents Ib and Ic flowing into the base and the collector. A transistor is often used as a signal amplifier, because over a certain operating range (the active region) the collector current is equal to a fixed constant times the base current (Ic = Ib). However, in digital circuits, we normally use a transistor as a simple switch thats always fully on or fully off, as explained next. Figure 3-68 shows the common-emitter configuration of an npn transistor, which is most often used in digital switching applications. This configuration
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(a)
B
uses two discrete resistors, R1 and R2, in addition to a single npn transistor. In this circuit, if VIN is 0 or negative, then the base-to-emitter diode junction is reverse biased, and no base current (Ib) can flow. If no base current flows, then no collector current (Ic) can flow, and the transistor is said to be cut off (OFF). Since the base-to-emitter junction is a real diode, as opposed to an ideal one, VIN must reach at least +0.6 V (one diode-drop) before any base current can flow. Once this happens, Ohms law tells us that I b = ( V IN 0.6 ) / R1
(We ignore the forward resistance Rf of the forward-biased base-to-emitter junction, which is usually small compared to the base resistor R1.) When base current flows, then collector current can flow in an amount proportional to Ib, that is, Ic = Ib The constant of proportionality, , is called the gain of the transistor, and is in the range of 10 to 100 for typical transistors.
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(b) Ie p n p B base emitter Ib collector Ic = Ib + Ie
Figure 3-67 A pnp transistor: (a) structure; (b) symbol.
C
C
cut off (OFF)
gain
VCC
R2
Ic
Figure 3-68 Common-emitter configuration of an npn transistor.
R1
+
VIN
Ib
+
VCE
VBE
Ie = Ib + Ic
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saturated ON ) saturation(region
saturation resistance transistor simulation
Figure 3-69 Transistor inverter: (a) logic symbol; (b) circuit diagram; (c) transfer characteristic.
IN
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V CE = V CC I c R 2 = V CC I b R 2 = V CC ( V IN 0.6 ) R2 / R1 I c = ( V CC V CE(sat) ) / ( R2 + R CE(sat) )
VCC VOUT R2 VCC VOUT R1 VIN Q1 OUT VCE(sat) LOW undefined HIGH (c) (a) (b)
Although the base current Ib controls the collector current flow Ic , it also indirectly controls the voltage VCE across the collector-to-emitter junction, since VCE is just the supply voltage VCC minus the voltage drop across resistor R2:
However, in an ideal transistor VCE can never be less than zero (the transistor cannot just create a negative potential), and in a real transistor VCE can never be less than VCE(sat), a transistor parameter that is typically about 0.2 V. If the values of VIN, , R1, and R2 are such that the above equation predicts a value of VCE that is less than VCE(sat), then the transistor cannot be operating in the active region and the equation does not apply. Instead, the transistor is operating in the saturation region, and is said to be saturated (ON ). No matter how much current Ib we put into the base, VCE cannot drop below VCE(sat), and the collector current Ic is determined mainly by the load resistor R2:
Here, RCE(sat) is the saturation resistance of the transistor. Typically, RCE(sat) is 50 or less and is insignificant compared with R2 . Computer scientists might like to imagine an npn transistor as a device that continuously looks at its environment and executes the program in Table 3-10.
3.9.4 Transistor Logic Inverter Figure 3-69 shows that we can make a logic inverter from an npn transistor in the common-emitter configuration. When the input voltage is LOW, the output voltage is HIGH, and vice versa. In digital switching applications, bipolar transistors are often operated so they are always either cut off or saturated. That is, digital circuits such as the
VIN
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/* Transistor parameters #define DIODEDROP 0.6 /* #define BETA 10; #define VCE_SAT 0.2 /* #define RCE_SAT 50 /*
main() { float Vcc, Vin, R1, R2; float Ib, Ic, Vce;
}
Figure 3-70 Normal states of an npn transistor in a digital switching circuit: (a) transistor symbol and currents; (b) equivalent circuit for a cut-off (OFF) transistor; (c) equivalent circuit for a saturated (ON) transistor.
(a) C (b) C (c) C
B
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Ta b l e 3 - 1 0 A C program that simulates the function of an npn transistor in the common-emitter configuration.
*/ volts */ volts */ ohms */ /* circuit parameters */ /* circuit conditions */ if (Vin < DIODEDROP) { /* cut off */ Ib = 0.0; Ic = 0.0; Vce = Vcc; } else { /* active or saturated */ Ib = (Vin - DIODEDROP) / R1; if ((Vcc - ((BETA * Ib) * R2)) >= VCE_SAT) { /* active */ Ic = BETA * Ib; Vce = Vcc - (Ic * R2); } else { /* saturated */ Vce = VCE_SAT; Ic = (Vcc - Vce) / (R2 + RCE_SAT); } }
Ic Ic = 0 Ic > 0 B B RCE(sat) Ib + Ib = 0 + Ib > 0 VCE(sat) = 0.2 V Ie = Ib + Ic VBE < 0.6 V Ie = 0 E VBE = 0.6 V Ie = Ib + Ic E E
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VCC = +5 V
storage time
Schottky diode Schottky-clamped transistor
Schottky transistor
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R VOUT VIN
Figure 3-71 Switch model for a transistor inverter.
RCEsat < 50
Switch is closed when VIN is HIGH.
VCEsat 0.2 V
inverter in Figure 3-69 are designed so that their transistors are always (well, almost always) in one of the states depicted in Figure 3-70. When the input voltage VIN is LOW, it is low enough that Ib is zero and the transistor is cut off; the collector-emitter junction looks like an open circuit. When VIN is HIGH, it is high enough (and R1 is low enough and is high enough) that the transistor will be saturated for any reasonable value of R2; the collector-emitter junction looks almost like a short circuit. Input voltages in the undefined region between LOW and HIGH are not allowed, except during transitions. This undefined region corresponds to the noise margin that we discussed in conjunction with Table 3-1. Another way to visualize the operation of a transistor inverter is shown in Figure 3-71. When VIN is HIGH, the transistor switch is closed, and the output terminal is connected to ground, definitely a LOW voltage. When VIN is LOW, the transistor switch is open and the output terminal is pulled to +5 V through a resistor; the output voltage is HIGH unless the output terminal is too heavily loaded (i.e., improperly connected through a low impedance to ground). 3.9.5 Schottky Transistors When the input of a saturated transistor is changed, the output does not change immediately; it takes extra time, called storage time, to come out of saturation. In fact, storage time accounts for a significant portion of the propagation delay in the original TTL logic family. Storage time can be eliminated and propagation delay can be reduced by ensuring that transistors do not saturate in normal operation. Contemporary TTL logic families do this by placing a Schottky diode between the base and collector of each transistor that might saturate, as shown in Figure 3-72. The resulting transistors, which do not saturate, are called Schottky-clamped transistors or Schottky transistors for short.
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When forward biased, a Schottky diodes voltage drop is much less than a standard diodes, 0.25 V vs. 0.6 V. In a standard saturated transistor, the base-tocollector voltage is 0.4 V, as shown in Figure 3-73(a). In a Schottky transistor, the Schottky diode shunts current from the base into the collector before the transistor goes into saturation, as shown in (b). Figure 3-74 is the circuit diagram of a simple inverter using a Schottky transistor.
+ 0.25 V
)
VBC = 0.4 V + +
VBE = 0.6 V
Figure 3-73 Operation of a transistor with large base current: (a) standard saturated transistor; (b) transistor with Schottky diode to prevent saturation.
VCC
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collector collector base base emitter emitter (a) (b)
Figure 3-72 Schottky-clamped transistor: (a) circuit; (b) symbol.
(b)
Ic
+
VBC = 0.25 V + Ib +
Ic
+
VCE = 0.2 V
VCE = 0.35 V
Ib
VBE = 0.6 V
Figure 3-74 Inverter using Schottky transistor.
R2
VOUT
R1
VIN
Q1
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diode AND gate clamp diode
phase splitter
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3.10 Transistor-Transistor Logic
LOW 00.8 volts. HIGH 2.05.0 volts.
The most commonly used bipolar logic family is transistor-transistor logic. Actually, there are many different TTL families, with a range of speed, power consumption, and other characteristics. The circuit examples in this section are based on a representative TTL family, Low-power Schottky (LS or LS-TTL). TTL families use basically the same logic levels as the TTL-compatible CMOS families in previous sections. Well use the following definitions of LOW and HIGH in our discussions of TTL circuit behavior:
3.10.1 Basic TTL NAND Gate The circuit diagram for a two-input LS-TTL NAND gate, part number 74LS00, is shown in Figure 3-75. The NAND function is obtained by combining a diode AND gate with an inverting buffer amplifier. The circuits operation is best understood by dividing it into the three parts that are shown in the figure and discussed in the next three paragraphs: Diode AND gate and input protection. Phase splitter. Output stage.
Diodes D1X and D1Y and resistor R1 in Figure 3-75 form a diode AND gate, as in Section 3.9.2. Clamp diodes D2X and D2Y do nothing in normal operation, but limit undesirable negative excursions on the inputs to a single diode drop. Such negative excursions may occur on HIGH-to-LOW input transitions as a result of transmission-line effects, discussed in Section 12.4. Transistor Q2 and the surrounding resistors form a phase splitter that controls the output stage. Depending on whether the diode AND gate produces a low or a high voltage at VA, Q2 is either cut off or turned on.
WHERE IN THE WORLD IS Q1?
Notice that there is no transistor Q1 in Figure 3-75, but the other transistors are named in a way thats traditional; some TTL devices do in fact have a transistor named Q 1. Instead of diodes like D1X and D1Y, these devices use a multiple-emitter transistor Q1 to perform logic. This transistor has one emitter per logic input, as shown in the figure to the right. Pulling any one of the emitters LOW is sufficient to turn the transistor ON and thus pull VA LOW.
VCC
R1 2.8 k
X Y
VA
Q1
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The output stage has two transistors, Q4 and Q5, only one of which is on at any time. The TTL output stage is sometimes called a totem-pole or push-pull output. Similar to the p-channel and n-channel transistors in CMOS, Q 4 and Q5 provide active pull-up and pull-down to the HIGH and LOW states, respectively. The functional operation of the TTL NAND gate is summarized in Figure 3-76(a). The gate does indeed perform the NAND function, with the truth table and logic symbol shown in (b) and (c). TTL NAND gates can be designed with any desired number of inputs simply by changing the number of diodes in
(a) X Y VA Q2 Q3 Q4 Q5 Q6 VZ Z
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R1 20 k R2 8 k R5 120 D1X X Q3 Q4 D1Y Y VA Q2 D3 D4 R6 4 k Z D2X D2Y R3 12 k Q5 R4 1.5 k R7 3 k Q6
Figure 3-75 Circuit diagram of two-input LS-TTL NAND g ate.
Diode AND gate and input protection
Phase splitter
Output stage
output stage totem-pole output push-pull output
L L H H
L H L H
1.05 1.05 1.05
1.2
off off off on
on on on off
on on on off
off off off on
off off off on
2.7 2.7 2.7 0.35
H H H L
Figure 3-76 Functional operation of a TTL two-input NAND g ate: (a) function table; (b) truth table; (c) logic symbol.
(b)
X 0 0 1 1
Y 0 1 0 1
Z 1 1 1 0
(c)
X Y
Z
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sinking current
sourcing current
CURRENT SPIKES AGAIN
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the diode AND gate in the figure. Commercially available TTL NAND gates have as many as 13 inputs. A TTL inverter is designed as a 1-input NAND gate, omitting diodes D1Y and D2Y in Figure 3-75. Since the output transistors Q4 and Q5 are normally complementaryone ON and the other OFFyou might question the purpose of the 120 resistor R5 in the output stage. A value of 0 would give even better driving capability in the HIGH state. This is certainly true from a DC point of view. However, when the TTL output is changing from HIGH to LOW or vice versa, there is a short time when both transistors may be on. The purpose of R5 is to limit the amount of current that flows from VCC to ground during this time. Even with a 120 resistor in the TTL output stage, higher-than-normal currents called current spikes flow when TTL outputs are switched. These are similar to the current spikes that occur when high-speed CMOS outputs switch. So far we have shown the input signals to a TTL gate as ideal voltage sources. Figure 3-77 shows the situation when a TTL input is driven LOW by the output of another TTL gate. Transistor Q5A in the driving gate is ON, and thereby provides a path to ground for the current flowing out of the diode D1XB in the driven gate. When current flows into a TTL output in the LOW state, as in this case, the output is said to be sinking current. Figure 3-78 shows the same circuit with a HIGH output. In this case, Q4A in the driving gate is turned on enough to supply the small amount of leakage current flowing through reverse-biased diodes D1XB and D2XB in the driven gate. When current flows out of a TTL output in the HIGH state, the output is said to be sourcing current.
3.10.2 Logic Levels and Noise Margins At the beginning of this section, we indicated that we would consider TTL signals between 0 and 0.8 V to be LOW, and signals between 2.0 and 5.0 V to be HIGH . Actually, we can be more precise by defining TTL input and output levels in the same way as we did for CMOS: VOHmin The minimum output voltage in the HIGH state, 2.7 V for most TTL families. VIHmin The minimum input voltage guaranteed to be recognized as a HIGH, 2.0 V for all TTL families.
Current spikes can show up as noise on the power-supply and ground connections in TTL and CMOS circuits, especially when multiple outputs are switched simultaneously. For this reason, reliable circuits require decoupling capacitors between VCC and ground, distributed throughout the circuit so that there is a capacitor within an inch or so of each chip. Decoupling capacitors supply the instantaneous current needed during transitions.
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R2A 8 k R5A 120 R1B 20 k R2B 8 k Q3A (OFF) 0.35 V D1XB Q4A (OFF) D1YB Q2A (ON) D3A D4A R6A 4 k Q2B (OFF) 2V D2XB D2YB Q5A (ON) R3B 12 k R4A 1.5 k R7A 3 k R4B 1.5 k Q6A (ON)
Figure 3-77 A TTL output driving a TTL input LOW.
VCC = +5 V
R2A 8 k
R5A 120
R1B 20 k
R2B 8 k
Q3A (ON)
2.7 V
D1XB
Q4A (ON)
D1YB
Q2A (OFF)
D3A D4A
R6A 4 k
Q2B (ON)
2V
D2XB
D2YB
Q5A (OFF)
R3B 12 k
R4A 1.5 k
R7A 3 k
Ileak
R4B 1.5 k
Q6A (OFF)
Figure 3-78 A TTL output driving a TTL input HIGH.
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Figure 3-79 Noise margins for popular TTL logic families (74LS, 74S, 74ALS, 74AS, 74F).
DC noise margin
fanout
current flow
LOW-state unit load
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HIGH VOHmin = 2.7 V VIHmin = 2.0 V High-state DC noise margin Low-state DC noise margin ABNORMAL LOW 0 VILmax = 0.8 V VOLmax = 0.5 V
VILmax The maximum input voltage guaranteed to be recognized as a LOW, 0.8 V for most TTL families. VOLmax The maximum output voltage in the LOW state, 0.5 V for most families.
These noise margins are illustrated in Figure 3-79. In the HIGH state, the VOHmin specification of most TTL families exceeds VIHmin by 0.7 V, so TTL has a DC noise margin of 0.7 V in the HIGH state. That is, it takes at least 0.7 V of noise to corrupt a worst-case HIGH output into a voltage that is not guaranteed to be recognizable as a HIGH input. In the LOW state, however, VILmax exceeds VOLmax by only 0.3 V, so the DC noise margin in the LOW state is only 0.3 V. In general, TTL and TTL-compatible circuits tend to be more sensitive to noise in the LOW state than in the HIGH state.
3.10.3 Fanout As we defined it previously in Section 3.5.4, fanout is a measure of the number of gate inputs that are connected to (and driven by) a single gate output. As we showed in that section, the DC fanout of CMOS outputs driving CMOS inputs is virtually unlimited, because CMOS inputs require almost no current in either state, HIGH or LOW. This is not the case with TTL inputs. As a result, there are very definite limits on the fanout of TTL or CMOS outputs driving TTL inputs, as youll learn in the paragraphs that follow. As in CMOS, the current flow in a TTL input or output lead is defined to be positive if the current actually flows into the lead, and negative if current flows out of the lead. As a result, when an output is connected to one or more inputs, the algebraic sum of all the input and output currents is 0. The amount of current required by a TTL input depends on whether the input is HIGH or LOW, and is specified by two parameters: IILmax The maximum current that an input requires to pull it LOW. Recall from the discussion of Figure 3-77 that positive current is actually flowing from VCC, through R1B, through diode D1XB , out of the input lead, through the driving output transistor Q5A, and into ground. Since current flows out of a TTL input in the LOW state, IILmax has a negative value. Most LS-TTL inputs have IILmax = 0.4 mA, which is sometimes called a LOW-state unit load for LS-TTL.
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IIHmax The maximum current that an input requires to pull it HIGH. As shown in Figure 3-78 on page 155, positive current flows from VCC, through R5A and Q4A of the driving gate, and into the driven input, where it leaks to ground through reversed-biased diodes D1XB and D2XB. Since current flows into a TTL input in the HIGH state, IIHmax has a positive value. Most LS-TTL inputs have IIHmax = 20 A, which is sometimes called a HIGH-state unit load for LS-TTL. Like CMOS outputs, TTL outputs can source or sink a certain amount of current depending on the state, HIGH or LOW: IOLmax The maximum current an output can sink in the LOW state while maintaining an output voltage no more than VOLmax. Since current flows into the output, IOLmax has a positive value, 8 mA for most LS-TTL outputs. IOHmax The maximum current an output can source in the HIGH state while maintaining an output voltage no less than VOHmin. Since current flows out of the output, IOHmax has a negative value, 400 A for most LSTTL outputs.
Notice that the value of IOLmax for typical LS-TTL outputs is exactly 20 times the absolute value of IILmax. As a result, LS-TTL is said to have a LOWstate fanout of 20, because an output can drive up to 20 inputs in the LOW state. Similarly, the absolute value of IOHmax is exactly 20 times IIHmax, so LS-TTL is said to have a HIGH -state fanout of 20 also. The overall fanout is the lesser of the LOW- and HIGH-state fanouts. Loading a TTL output with more than its rated fanout has the same deleterious effects that were described for CMOS devices in Section 3.5.5 on page 106. That is, DC noise margins may be reduced or eliminated, transition times and delays may increase, and the device may overheat.
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HIGH-state unit load LOW-state fanout HIGH-state fanout overall fanout
TTL OUTPUT ASYMMETRY
Although LS-TTLs numerical fanouts for HIGH and LOW states are equal, LS-TTL and other TTL families have a definite asymmetry in current driving capabilityan LS-TTL output can sink 8 mA in the LOW state, but can source only 400 A in the HIGH state. This asymmetry is no problem when TTL outputs drive other TTL inputs, because it is matched by a corresponding asymmetry in TTL input current requirements (IILmax is large, while IIHmax is small). However, it is a limitation when TTL is used to drive LEDs, relays, solenoids, or other devices requiring large amounts of current, often tens of milliamperes. Circuits using these devices must be designed so that current flows (and the driven device is on) when the TTL output is in the LOW state, and so little or no current flows in the HIGH state. Special TTL buffer/driver gates are made that can sink up to 60 mA in the LOW state, but that still have a rather puny current sourcing capability in the HIGH state (2.4 mA).
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n 0.4 mA R pd < 0.5 V
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If a TTL or CMOS output is forced to sink a lot more than IOLmax, the device may be damaged, especially if high current is allowed to flow for more than a second or so. For example, suppose that a TTL output in the LOW state is short-circuited directly to the 5 V supply. The ON resistance, RCE(sat), of the saturated Q5 transistor in a typical TTL output stage is less than 10 . Thus, Q5 must dissipate about 52/10 or 2.5 watts. Dont try this yourself unless youre prepared to deal with the consequences! Thats enough heat to destroy the device (and burn your finger) in a very short time.
In general, two calculations must be carried out to confirm that an output is not being overloaded: HIGH state The IIHmax values for all of the driven inputs are added. This sum must be less than or equal to the absolute value of IOHmax for the driving output. LOW state The IILmax values for all of the driven inputs are added. The absolute value of this sum must be less than or equal to IOLmax for the driving output.
For example, suppose you designed a system in which a certain LS-TTL output drives ten LS-TTL and three S-TTL gate inputs. In the HIGH state, a total of 10 20 + 3 50 A = 350 A is required. This is within an LS-TTL outputs HIGH -state current-sourcing capability of 400 A. But in the LOW state, a total of 10 0.4 + 3 2.0 mA = 10.0 mA is required. This is more than an LS-TTL outputs LOW-state current-sinking capability of 8 mA, so the output is overloaded. 3.10.4 Unused Inputs Unused inputs of TTL gates can be handled in the same way as we described for CMOS gates in Section 3.5.6 on page 107. That is, unused inputs may be tied to used ones, or unused inputs may be pulled HIGH or LOW as is appropriate for the logic function. The resistance value of a pull-up or pull-down resistor is more critical with TTL gates than CMOS gates, because TTL inputs draw significantly more current, especially in the LOW state. If the resistance is too large, the voltage drop across the resistor may result in a gate input voltage beyond the normal LOW or HIGH range. For example, consider the pull-down resistor shown in Figure 3-80. The pull-down resistor must sink 0.4 mA of current from each of the unused LS-TTL inputs that it drives. Yet the voltage drop across the resistor must be no more than 0.5 V in order to have a LOW input voltage no worse than that produced by a normal gate output. If the resistor drives n LS-TTL inputs, then we must have
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Thus, if the resistor must pull 10 LS-TTL inputs LOW, then we must have Rpd < 0.5 / (10 4 103), or Rpd < 125 . Similarly, consider the pull-up resistor shown in Figure 3-81. It must source 20 A of current to each unused input while producing a HIGH voltage no worse than that produced by a normal gate output, 2.7 V. Therefore, the voltage drop across the resistor must be no more than 2.3 V; if n LS-TTL input are driven, we must have n 20 A R pu < 2.3 V
Thus, if 10 LS-TTL inputs are pulled up, then Rpu < 2.3 / (10 20 10-6), or Rpu < 11.5 K.
+5 V
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FLOATING TTL INPUTS Analysis of the TTL input structure shows that unused inputs left unconnected (or floating) behave as if they have a HIGH voltage appliedthey are pulled HIGH by base resistor R1 in Figure 3-75 on page 153. However, R1s pull-up is much weaker than that of a TTL output driving the input. As a result, a small amount of circuit noise, such as that produced by other gates when they switch, can make a floating input spuriously behave like its LOW. Therefore, for the sake of reliability, unused TTL inputs should be tied to a stable HIGH or LOW voltage source.
Vin 0.5 V IILmax sink current from LOW inputs Rpd source current to HIGH inputs Rpu
Figure 3-80 Pull-down resistor for TTL inputs.
Figure 3-81 Pull-up resistor for TTL inputs.
Vin 2.7 V
IIHmax
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WHY USE A RESISTOR? Copyright 1999 by John F. Wakerly
You might be asking yourself, Why use a pull-up or pull-down resistor, when a direct connection to ground or the 5-V power supply should be a perfectly good source of LOW or H IGH? Well, for a HIGH source, a direct connection to the 5 V power supply is not recommended, since an input transient of over 5.5 V can damage some TTL devices, ones that use a multi-emitter transistor in the input stage. The pull-up resistor limits current and prevents damage in this case. For a LOW source, a direct connection to ground without the pull-down resistor is actually OK in most cases. Youll see many examples of this sort of connection throughout this book. However, as explained in Section 12.2.2 on page 803, the pull-down resistor is still desirable in some cases so that the constant LOW signal it produces can be overridden and driven HIGH for system-testing purposes.
3.10.5 Additional TTL Gate Types Although the NAND gate is the workhorse of the TTL family, other types of gates can be built with the same general circuit structure. The circuit diagram for an LS-TTL NOR gate is shown in Figure 3-82. If either input X or Y is HIGH, the corresponding phase-splitter transistor Q2X or Q2Y is turned on, which turns off Q3 and Q4 while turning on Q5 and Q6, and the output is LOW. If both inputs are LOW, then both phase-splitter transistors are off, and the output is forced HIGH. This functional operation is summarized in Figure 3-83. The LS-TTL NOR gates input circuits, phase splitter, and output stage are almost identical to those of an LS-TTL NAND gate. The difference is that an LSTTL NAND gate uses diodes to perform the AND function, while an LS-TTL NOR gate uses parallel transistors in the phase splitter to perform the OR function. The speed, input, and output characteristics of a TTL N OR gate are comparable to those of a TTL NAND. However, an n-input NOR gate uses more transistors and resistors and is thus more expensive in silicon area than an ninput NAND. Also, internal leakage current limits the number of Q2 transistors that can be placed in parallel, so NOR gates have poor fan-in. (The largest discrete TTL NOR gate has only 5 inputs, compared with a 13-input NAND.) As a result, NOR gates are less commonly used than NAND gates in TTL designs. The most natural TTL gates are inverting gates like NAND and NOR. Noninverting TTL gates include an extra inverting stage, typically between the input stage and the phase splitter. As a result, noninverting TTL gates are typically larger and slower than the inverting gates on which they are based. Like CMOS, TTL gates can be designed with three-state outputs. Such gates have an output-enable or output-disable input that allows the output to be placed in a high-impedance state where neither output transistor is turned on.
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X
Y
Some TTL gates are also available with open-collector outputs. Such gates omit the entire upper half of the output stage in Figure 3-75, so that only passive pull-up to the HIGH state is provided by an external resistor. The applications and required calculations for TTL open-collector gates are similar to those for CMOS gates with open-drain outputs.
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R1X 20 k R2 8 k R5 120 D1X VAX Q2X Q3 D1Y R1Y 20 k Q4 R3X 10 k VAY Q2Y D3 D4 R6 4 k Z D2X D2Y R3Y 10 k Q5 R4 1.5 k R7 3 k Q6 Diode inputs and input protection OR function and phase splitter Output stage
Figure 3-82 Circuit diagram of a two-input LS-TTL NOR gate.
(a)
X
Y
VAX
Q2X off off on on
VAY
Q2Y off on off on
Q3
Q4
Q5
Q6
VZ
Z
L L H H
L H L H
1.05 1.05 1.2 1.2
1.05 1.2 1.05 1.2
on off off off
on off off off
off on on on
off on on on
2.7 0.35 0.35 0.35
H L L L
Figure 3-83 Two-input LS-TTL NOR gate: (a) function table; (b) truth table; (c) logic symbol.
(b)
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 0
(c)
X Y
Z
open-collector output
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74-series TTL
74H (High-speed TTL) 74L (Low-power TTL)
74S (Schottky TTL)
74LS (Low-power Schottky TTL)
74AS (Advanced Schottky TTL)
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3.11 TTL Families
Copyright 1999 by John F. Wakerly
TTL families have evolved over the years in response to the demands of digital designers for better performance. As a result, three TTL families have come and gone, and todays designers have five surviving families from which to choose. All of the TTL families are compatible in that they use the same power supply voltage and logic levels, but each family has its own advantages in terms of speed, power consumption, and cost.
3.11.1 Early TTL Families The original TTL family of logic gates was introduced by Sylvania in 1963. It was popularized by Texas Instruments, whose 7400-series part numbers for gates and other TTL components quickly became an industry standard. As in 7400-series CMOS, devices in a given TTL family have part numbers of the form 74FAMnn, where FAM is an alphabetic family mnemonic and nn is a numeric function designator. Devices in different families with the same value of nn perform the same function. In the original TTL family, FAM is null and the family is called 74-series TTL. Resistor values in the original TTL circuit were changed to obtain two more TTL families with different performance characteristics. The 74H (Highspeed TTL) family used lower resistor values to reduce propagation delay at the expense of increased power consumption. The 74L (Low-power TTL) family used higher resistor values to reduce power consumption at the expense of propagation delay. The availability of three TTL families allowed digital designers in the 1970s to make a choice between high speed and low power consumption for their circuits. However, like many people in the 1970s, they wanted to have it all, now. The development of Schottky transistors provided this opportunity, and made 74, 74H, and 74L TTL obsolete. The characteristics of betterperforming, contemporary TTL families are discussed in the rest of this section.
3.11.2 Schottky TTL Families Historically, the first family to make use of Schottky transistors was 74S (Schottky TTL). With Schottky transistors and low resistor values, this family has much higher speed, but higher power consumption, than the original 74-series TTL. Perhaps the most widely used and certainly the least expensive TTL family is 74LS (Low-power Schottky TTL), introduced shortly after 74S. By combining Schottky transistors with higher resistor values, 74LS TTL matches the speed of 74-series TTL but has about one-fifth of its power consumption. Thus, 74LS is a preferred logic family for new TTL designs. Subsequent IC processing and circuit innovations gave rise to two more Schottky logic families. The 74AS (Advanced Schottky TTL) family offers speeds approximately twice as fast as 74S with approximately the same power
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Maximum propagation delay (ns)
Power consumption per gate (mW) Speed-power product (pJ)
LOW-level input voltage (V)
LOW-level output voltage (V) HIGH -level input voltage (V)
HIGH -level output voltage (V) LOW-level input current (mA)
LOW-level output current (mA) HIGH -level input current (A)
HIGH -level output current (A)
consumption. The 74ALS (Advanced Low-power Schottky TTL) family offers both lower power and higher speeds than 74LS, and rivals 74LS in popularity for general-purpose requirements in new TTL designs. The 74F (Fast TTL) family is positioned between 74AS and 74ALS in the speed/power tradeoff, and is probably the most popular choice for high-speed requirements in new TTL designs.
3.11.3 Characteristics of TTL Families The important characteristics of contemporary TTL families are summarized in Table 3-11. The first two rows of the table list the propagation delay (in nanoseconds) and the power consumption (in milliwatts) of a typical 2-input NAND gate in each family. One figure of merit of a logic family is its speed-power product listed in the third row of the table. As discussed previously, this is simply the product of the propagation delay and power consumption of a typical gate. The speed-power product measures a sort of efficiencyhow much energy a logic gate uses to switch its output. The remaining rows in Table 3-11 describe the input and output parameters of typical TTL gates in each of the families. Using this information, you can
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Ta b l e 3 - 1 1 Characteristics of gates in TTL families.
Family Description Symbol 74S 74LS 74AS 74ALS 74F
3
9
1.7
4
3
19
2
8
1.2
4
57
18
13.6 0.8 0.5 2.0 2.7
4.8
12
VILmax
0.8 0.5 2.0 2.7
0.8 0.5 2.0 2.7
0.8 0.5 2.0 2.7
0.8 0.5 2.0 2.7
VOLmax
VIHmin
VOHmin IILmax
2.0 20 50
0.4 8
0.5 20 20
0.2 8
0.6 20
IOLmax IIHmax
20
20
20
IOHmax
1000
400
2000
400
1000
74ALS (Advanced Lowpower Schottky TTL) 74F (Fast TTL)
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recommended operating conditions electrical characteristics
switching characteristics
absolute maximum ratings
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A fourth section is also included in the manufacturers data book:
Copyright 1999 by John F. Wakerly
analyze the external behavior of TTL gates without knowing the details of the internal TTL circuit design. These parameters were defined and discussed in Sections 3.10.2 and 3.10.3. As always, the input and output characteristics of specific components may vary from the representative values given in Table 3-11, so you must always consult the manufacturers data book when analyzing a real design. 3.11.4 A TTL Data Sheet Table 3-12 shows the part of a typical manufacturers data sheet for the 74LS00. The 54LS00 listed in the data sheet is identical to the 74LS00, except that it is specified to operate over the full military temperature and voltage range, and it costs more. Most TTL parts have corresponding 54-series (military) versions. Three sections of the data sheet are shown in the table: Recommended operating conditions specify power-supply voltage, inputvoltage ranges, DC output loading, and temperature values under which the device is normally operated. Electrical characteristics specify additional DC voltages and currents that are observed at the device inputs and output when it is operated under the recommended conditions: II Maximum input current for a very high HIGH input voltage. IOS Output current with HIGH output shorted to ground. ICCH Power-supply current when all outputs (on four NAND gates) are HIGH . (The number given is for the entire package, which contains four NAND gates, so the current per gate is one-fourth of the specified amount.) ICCL Power-supply current when all outputs (on four NAND gates) are LOW.
Switching characteristics give maximum and typical propagation delays under typical operating conditions of VCC = 5 V and TA = 25C. A conservative designer must increase these delays by 5%10% to account for different power-supply voltages and temperatures, and even more under heavy loading conditions.
Absolute maximum ratings indicate the worst-case conditions for operating or storing the device without damage.
A complete data book also shows test circuits that are used to measure the parameters when the device is manufactured, and graphs that show how the typical parameters vary with operating conditions such as power-supply voltage (VCC), ambient temperature (TA), and load (RL, CL).
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RECOMMENDED OPERATING CONDITIONS
Parameter
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED FREE-AIR TEMPERATURE RANGE SN54LS00
Typ.(2)
Parameter
IIOS
SWITCHING CHARACTERISTICS, VCC = 5.0 V, TA = 25C
Parameter From (Input)
A or B
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Recommended Operating Conditions. 2. All typical values are at VCC = 5.0 V, TA = 25C. 3. Not more than one output should be shorted at a time; duration of short-circuit should not exceed one second.
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Ta b l e 3 - 1 2 Typical manufacturers data sheet for the 74LS00.
SN54LS00 Nom. SN74LS00 Nom. Description Min. Max. Min. Max.
Unit
VCC VIH VIL
Supply voltage
4.5
5.0
5.5
4.75 2.0
5.0
5.25
V V V
High-level input voltage Low-level input voltage
2.0
0.7
0.8
IOH IOL TA
High-level output current Low-level output current
0.4 4
0.4 4
mA mA C
Operating free-air temperature
55
125
0
70
SN74LS00
Typ.(2)
Test Conditions(1)
Min.
Max.
Min.
Max.
Unit
VIK
VCC = Min., IN = 18 mA
1.5
1.5
V
VOH VOL II
VCC = Min., VIL = Max., IOH = 0.4 mA VCC = Min., VIH = 2.0 V, IOL = 4 mA VCC = Min., VIH = 2.0 V, IOL = 8 mA VCC = Max., VI = 7.0 V VCC = Max. VI = 2.7 V VCC = Max. VI = 0.4 V VCC = Max. VCC = Max., VI = 0 V
2.5
3.4
2.7
3.4
V V
0.25
0.4
0.25
0.4
0.35
0.1 20
0.1 20
mA
IIH IIL
A
0.4
0.4
mA
(3)
20
100 1.6
20
100 1.6
mA
ICCH ICCL
0.8
0.8
mA
VCC = Max., VI = 4.5 V
2.4
4.4
2.4
4.4
mA
To (Output)
Y
Test Conditions
Min.
Typ.
Max.
Unit
tPLH
tPHL
RL = 2 k, CL = 15 pF
9
15
ns
10
15
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Figure 3-84 Output and input levels for interfacing TTL and CMOS families. (Note that HC and VHC inputs are not TTL compatible.)
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*3.12 CMOS/TTL Interfacing
OUTPUTS 5.0 INPUTS VOHmin , VOLmax HIGH VIHmin , VOLmax (HC, VHC) HC, HCT VHC, VHCT 3.84 3.80 3.85 High-state DC noise margin LS, S, ALS, AS, F 2.7 2.0 LS, S, ALS, AS, F, HCT, VHCT, FCT (HC, VHC)
(not drawn to scale)
A digital designer selects a default logic family to use in a system, based on general requirements of speed, power, cost, and so on. However, the designer may select devices from other families in some cases because of availability or other special requirements. (For example, not all 74LS part numbers are available in 74HCT, and vice versa.) Thus, its important for a designer to understand the implications of connecting TTL outputs to CMOS inputs, and vice versa. There are several factors to consider in TTL/CMOS interfacing, and the first is noise margin. The LOW-state DC noise margin depends on VOLmax of the driving output and VILmax of the driven input, and equals VILmax VOLmax. Similarly, the HIGH-state DC noise margin equals VOHmin VIHmin. Figure 3-84 shows the relevant numbers for TTL and CMOS families. For example, the LOW-state DC noise margin of HC or HCT driving TTL is 0.8 0.33 = 0.47 V, and the HIGH-state is 3.84 2.0 =1.84 V. On the other hand, the HIGH-state margin of TTL driving HC or VHC is 2.7 3.85 = 1.15 V. In other words, TTL driving HC or AC doesnt work, unless the TTL HIGH output happens to be higher and the CMOS HIGH input threshold happens to be lower by a total of 1.15 V compared to their worst-case specs. To drive CMOS inputs properly from TTL outputs, the CMOS devices should be HCT, VHCT. or FCT rather than HC or VHC. The next factor to consider is fanout. As with pure TTL (Section 3.10.3), a designer must sum the input current requirements of devices driven by an output and compare with the outputs capabilities in both states. Fanout is not a problem when TTL drives CMOS, since CMOS inputs require almost no current in either state. On the other hand, TTL inputs, especially in the LOW state, require sub-
ABNORMAL
1.35
FCT LS, S, ALS, AS, F VHC, VHCT HC, HCT
0.55 0.5 0.44 0.33
0.8
LS, S, ALS, AS, F, HCT, VHCT, FCT
LOW
Low-state DC noise margin
0
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stantial current, especially compared to HC and HCT output capabilities. For example, an HC or HCT output can drive 10 LS or only two S-TTL inputs. The last factor is capacitive loading. Weve seen that load capacitance increases both the delay and the power dissipation of logic circuits. Increases in delay are especially noticeable with HC and HCT outputs, whose transition times increase about 1 ns for each 5 pF of load capacitance. The transistors in FCT outputs have very low on resistances, so their transition times increase only about 0.1 ns for each 5 pF of load capacitance. For a given load capacitance, power-supply voltage, and application, all of the CMOS families have similar dynamic power dissipation, since each variable in the CV 2f equation is the same. On the other hand, TTL outputs have somewhat lower dynamic power dissipation, since the voltage swing between TTL HIGH and LOW levels is smaller.
*3.13 Low-Voltage CMOS Logic and Interfacing
Two important factors have led the IC industry to move towards lower powersupply voltages in CMOS devices:
In most applications, CMOS output voltages swing from rail to rail, so the V in the CV2f equation is the power-supply voltage. Cutting power-supply voltage reduces dynamic power dissipation more than proportionally. As the industry moves towards ever-smaller transistor geometries, the oxide insulation between a CMOS transistors gate and its source and drain is getting ever thinner, and thus incapable of insulating voltage potentials as high as 5 V. As a result, JEDEC, an IC industry standards group, selected 3.3V 0.3V, 2.5V 0.2V, and 1.8V 0.15V as the next standard logic power-supply voltages. JEDEC standards specify the input and output logic voltage levels for devices operating with these power-supply voltages. The migration to lower voltages has occurred in stages, and will continue to do so. For discrete logic families, the trend has been to produce parts that operate and produce outputs at the lower voltage, but that can also tolerate inputs at the higher voltage. This approach has allowed 3.3-V CMOS families to operate with 5-V CMOS and TTL families, as well see in the next section. Many ASICs and microprocessors have followed a similar approach, but another approach is often used as well. These devices are large enough that it can make sense to provide them with two power-supply voltages. A low voltage, such as 2.5 V, is supplied to operate the chips internal gates, or core logic. A higher voltage, such as 3.3 V, is supplied to operate the external input and output circuits, or pad ring, for compatibility with older-generation devices in the system. Special buffer circuits are used internally to translate safely and quickly between the core-logic and the pad-ring logic voltages.
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core logic pad ring
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LVCMOS (low-voltage CMOS) LVTTL (low-voltage TTL)
(a)
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Figure 3-85 Comparison of logic levels: (a) 5-V CMOS; (b) 5-V TTL, including 5-V TTL-compatible CMOS; (c) 3.3-V LVTTL; (d) 2.5-V CMOS; (e) 1.8-V CMOS.
VCC (b) 5.0 V VCC 5.0 V 4.44 V VOH 3.5 V VIH (c) 3.3 V VCC (d) 2.5 V VT 2.4 V 2.0 V 1.5 V VOH VIH VT 2.4 V 2.0 V 1.5 V VOH VIH VT 2.5 V 2.0 V 1.7 V 1.2 V 0.7 V 0.4 V 5.0 V VCC 1.5 V VIL VOH VIH VT (e) 1.8 V VCC 0.8 V 0.4 V 5.0 V VIL 0.8 V 0.4 V 5.0 V VIL 0.5 V 5.0 V VOL VIL VOL VOL VOL 1.45 V 1.2 V 0.9 V 0.65 V 0.45 V 5.0 V VOH VIH VT VIL VOL GND GND GND GND 5-V CMOS Families 5-V TTL Families 3.3-V LVTTL Families 2.5-V CMOS Families
*3.13.1 3.3-V LVTTL and LVCMOS Logic The relationships among signal levels for standard TTL and low-voltage CMOS devices operating at their nominal power-supply voltages are illustrated nicely in Figure 3-85, adapted from a Texas Instruments application note. The original, symmetric signal levels for pure 5-V CMOS families such as HC and VHC are shown in (a). TTL-compatible CMOS families such as HCT, VHCT, and FCT shift the voltage levels downwards for compatibility with TTL as shown in (b). The first step in the progression of lower CMOS power-supply voltages was 3.3 V. The JEDEC standard for 3.3-V logic actually defines two sets of levels. LVCMOS (low-voltage CMOS) levels are used in pure CMOS applications where outputs have light DC loads (less than 100 A), so VOL and VOH are maintained within 0.2 V of the power-supply rails. LVTTL (low-voltage TTL) levels, shown in (c), are used in applications where outputs have significant DC loads, so VOL can be as high as 0.4 V and VOH can be as low as 2.4 V. The positioning of TTLs logic levels at the low end of the 5-V range was really quite fortuitous. As shown in Figure 3-85(b) and (c), it was possible to define the LVTTL levels to match up with TTL levels exactly. Thus, an LVTTL output can drive a TTL input with no problem, as long as its output current specifications (IOLmax , IOHmax) are respected. Similarly, a TTL output can drive an LVTTL input, except for the problem of driving it beyond LVTTLs 3.3-V VCC , as discussed next.
GND
1.8-V CMOS Families
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*3.13.2 5-V Tolerant Inputs The inputs of a gate wont necessarily tolerate voltages greater than VCC. This can easily occur when 5-V and 3.3-V logic families in a system. For example, 5-V CMOS devices easily produce 4.9-V outputs when lightly loaded, and both CMOS and TTL devices routinely produce 4.0-V outputs even when moderately loaded. The maximum voltage VImax that can be tolerated by an input is listed in the absolute maximum ratings section of the manufacturers data sheet. For HC devices, VImax equals VCC. Thus, if an HC device is powered by a 3.3-V supply, its cannot be driven by any 5-V CMOS or TTL outputs. For VHC devices, on the other hand, VImax is 7 V; thus, VHC devices with a 3.3-V power supply may be used to convert 5-V outputs to 3.3-V levels for use with 3.3-V microprocessors, memories, and other devices in a pure 3.3-V subsystem. Figure 3-86 explains why some inputs are 5-V tolerant and others are not. As shown in (a), the HC and HCT input structure actually contains two reversebiased clamp diodes, which we havent shown before, between each input signal and VCC and ground. The purpose of these diodes is specifically to shunt any transient input signal value less than 0 through D1 or greater than VCC through D2 to the corresponding power-supply rail. Such transients can occur as a result of transmission-line reflections, as described in Section 12.4. Shunting the socalled undershoot or overshoot to ground or VCC reduces the magnitude and duration of reflections. Of course, diode D2 cant distinguish between transient overshoot and a persistent input voltage greater than VCC. Hence, if a 5-V output is connected to one of these inputs, it will not see the very high impedance normally associated with a CMOS input. Instead, it will see a relatively low impedance path to VCC through the now forward-biased diode D2, and excessive current will flow. Figure 3-86(b) shows a 5-V tolerant CMOS input. This input structure simply omits D2; diode D1 is still provided to clamp undershoot. The VHC and AHC families use this input structure.
(a) VCC (b) VCC
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clamp diode
D2 Q2 Q2 VI Q1 VI Q1 D1 D1
Figure 3-86 CMOS input structures: (a) non-5-V tolerant HC; (b) 5-V tolerant VHC.
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Figure 3-87 CMOS three-state output structures: (a) non-5-V tolerant HC and VHC; b) 5-V tolerant LVC.
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(a) VCC (b) VCC V2 VCC Q2 V2 VOUT Q2 VOUT Y VCC Q3 VOUT Y 0V Q1 0V Q1
The kind of input structure shown in Figure 3-86(b) is necessary but not sufficient to create 5-V tolerant inputs. The transistors in a devices particular fabrication process must also be able to withstand voltage potentials higher than VCC . On this basis, VImax in the VHC family is limited to 7.0 V. In many 3.3-V ASIC processes, its not possible to get 5-V tolerant inputs, even if youre willing to give up the transmission-line benefits of diode D2.
*3.13.3 5-V Tolerant Outputs Five-volt tolerance must also be considered for outputs, in particular, when both 3.3-V and 5-V three-state outputs are connected to a bus. When the 3.3-V output is in the disabled, Hi-Z state, a 5-V device may be driving the bus, and a 5-V signal may appear on the 3.3-V devices output. In this situation, Figure 3-87 explains why some outputs are 5-V tolerant and others are not. As shown in (a), the standard CMOS three-state output has an n-channel transistor Q1 to ground and a p-channel transistor Q2 to VCC . When the output is disabled, circuitry (not shown) holds the gate of Q1 near 0 V, and the gate of Q2 near VCC, so both transistors are off and Y is Hi-Z. Now consider what happens if VCC is 3.3 V and a different device applies a 5-V signal to the output pin Y in (a). Then the drain of Q2 (Y) is at 5 V while the gate (V2) is still at only 3.3 V. With the gate at a lower potential than the drain, Q2 will begin to conduct and provide a relatively low-impedance path from Y to VCC , and excessive current will flow. Both HC and VHC three-state outputs have this structure and therefore are not 5-V tolerant. Figure 3-87(b) shows a 5-V tolerant output structure. An extra p-channel transistor Q3 is used to prevent Q2 from turning on when it shouldnt. When VOUT is greater than VCC, Q3 turns on. This forms a relatively low impedance path from Y to the gate of Q2, which now stays off because its gate voltage V2 can no longer be below the drain voltage. This output structure is used in Texas Instruments LVC (Low-Voltage CMOS) family.
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*3.13.4 TTL/LVTTL Interfacing Summary Based on the information in the preceding subsections, TTL (5-V) and LVTTL (3.3-V) devices can be mixed in the same system subject to just three rules:
1. LVTTL outputs can drive TTL inputs directly, subject to the usual constraints on output current (IOLmax, IOHmax) of the driving devices. 2. TTL outputs can drive LVTTL inputs if the inputs are 5-V tolerant. 3. TTL and LVTTL three-state outputs can drive the same bus if the LVTTL outputs are 5-V tolerant.
*3.13.5 2.5-V and 1.8-V Logic The transition from 3.3-V to 2.5-V logic will not be so easy. It is true that 3.3-V outputs can drive 2.5-V inputs as long as the inputs are 3.3-V tolerant. However, a quick look at Figure 3-85(c) and (d) on page 168 shows that VOH of a 2.5-V output equals VIH of a 3.3-V input. In other words, there is zero HIGH-state DC noise margin when a 2.5-V output drives a 3.3-V input, not a good situation. The solution to this problem is to use a level translator or level shifter, a device which is powered by both supply voltages and which internally boosts the lower logic levels (2.5 V) to the higher ones (3.3 V). Many of todays ASICs and microprocessors contain level translators internally, allowing them to operate with a 2.5-V or 2.7-V core and a 3.3-V pad ring, as we discussed at the beginning of this section. If and when 2.5-V discrete devices become popular, we can expect the major semiconductor vendors produce level translators as stand-alone components as well. The next step will be a transition from 2.5-V to 1.8-V logic. Referring to Figure 3-85(d) and (e), you can see that the HIGH-state DC noise margin is actually negative when a 1.8-V output drives a 2.5-V input, so level translators will be needed in this case also.
*3.14 Emitter-Coupled Logic
The key to reducing propagation delay in a bipolar logic family is to prevent a gates transistors from saturating. In Section 3.9.5, we learned how Schottky diodes prevent saturation in TTL gates. However, it is also possible to prevent saturation by using a radically different circuit structure, called current-mode logic (CML) or emitter-coupled logic (ECL). Unlike the other logic families in this chapter, CML does not produce a large voltage swing between the LOW and HIGH levels. Instead, it has a small voltage swing, less than a volt, and it internally switches current between two possible paths, depending on the output state. The first CML logic family was introduced by General Electric in 1961. The concept was soon refined by Motorola and others to produce the still popular 10K and 100K emitter-coupled logic (ECL) families. These families are
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level translator level shifter current-mode logic (CML)
emitter-coupled logic (ECL)
emitter-coupled logic (ECL)
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differential amplifier
Figure 3-88 Basic CML inverter/buffer circuit with input HIGH .
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VCC = 5.0 V R1 300 R2 330 VOUT1 4.2 V (LOW) VOUT2 5.0 V (HIGH)
extremely fast, offering propagation delays as short as 1 ns. The newest ECL family, ECLinPS (literally, ECL in picoseconds), offers maximum delays under 0.5 ns (500 ps), including the signal delay getting on and off of the IC package. Throughout the evolution of digital circuit technology, some type of ECL has always been the fastest technology for discrete, packaged logic components. Still, commercial ECL families arent nearly as popular as CMOS and TTL, mainly because they consume much more power. In fact, high power consumption made the design of ECL supercomputers, such as the Cray-1 and Cray-2, as much of a challenge in cooling technology as in digital design. Also, ECL has a poor speed-power product, does not provide a high level of integration, has fast edge rates requiring design for transmission-line effects in most applications, and is not directly compatible with TTL and CMOS. Nevertheless, ECL still finds its place as a logic and interface technology in very high-speed communications gear, including fiber-optic transceiver interfaces for gigabit Ethernet and Asynchronous Transfer Mode (ATM) networks.
*3.14.1 Basic CML Circuit The basic idea of current-mode logic is illustrated by the inverter/buffer circuit in Figure 3-88. This circuit has both an inverting output (OUT1) and a noninverting output (OUT2). Two transistors are connected as a differential amplifier with a common emitter resistor. The supply voltages for this example are VCC = 5.0, VBB = 4.0, and VEE = 0 V, and the input LOW and HIGH levels are defined to be 3.6 and 4.4 V. This circuit actually produces output LOW and HIGH levels that are 0.6 V higher (4.2 and 5.0 V), but this is corrected in real ECL circuits.
OUT1
OUT2
VIN 4.4 V (HIGH)
IN
Q2 Q1 on OFF VE 3.8 V
VBB = 4.0 V
R3 1.3 k
VEE = 0.0 V
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When VIN is HIGH, as shown in the figure, transistor Q1 is on, but not saturated, and transistor Q2 is OFF. This is true because of a careful choice of resistor values and voltage levels. Thus, VOUT2 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW). When VIN is LOW, as shown in Figure 3-89, transistor Q2 is on, but not saturated, and transistor Q1 is OFF. Thus, VOUT1 is pulled to 5.0 V through R1, and it can be shown that VOUT2 is about 4.2 V. The outputs of this inverter are called differential outputs because they are always complementary, and it is possible to determine the output state by looking at the difference between the output voltages (VOUT1 VOUT2) rather than their absolute values. That is, the output is 1 if (VOUT1 VOUT2) > 0, and it is 0 if (VOUT1 VOUT2) > 0. It is possible to build input circuits with two wires per logical input that define the logical signal value in this way; these are called differential inputs Differential signals are used in most ECL interfacing and clock distribution applications because of their low skew and high noise immunity. They are low skew because the timing of a 0-to-1 or 1-to-0 transition does not depend critically on voltage thresholds, which may change with temperature or between devices. Instead, the timing depends only on when the voltages cross over relative to each other. Similarly, the relative definition of 0 and 1 provides outstanding noise immunity, since noise created by variations in the power supply or coupled from external sources tend to be common-mode signals that affect both differential signals similarly, leaving the difference value unchanged.
VCC = 5.0 V
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differential outputs differential inputs
R1 300 R2 330 VOUT1 5.0 V (HIGH) VOUT2 4.2 V (LOW)
common-mode signals
Figure 3-89 Basic CML inverter/buffer circuit with input LOW.
OUT1
OUT2
VIN 3.6 V (LOW)
IN
Q2 Q1 OFF on VE 3.4 V
VBB = 4.0 V
R3 1.3 k
VEE = 0.0 V
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single-ended input
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(a) VCC = 5.0 V X VX R1 300 R2 330 VOUT1 VOUT2 (c) OUT1 OUT2 X Y Y VY Q1 Q2 Q3 VBB = 4.0 V VE R3 1.3 k VEE = 0.0 V (b) (d) XY VX VY Q1 Q2 Q3 VE VOUT1 VOUT2 OUT1 OUT2 5.0 4.2 4.2 4.2 4.2 5.0 5.0 5.0 H L L L L H H H XY 0 0 1 1 0 1 0 1 OUT1 OUT2 1 0 0 0 0 1 1 1 L L H H L H L H 3.6 3.6 4.4 4.4 3.6 4.4 3.6 4.4 OFF OFF on on OFF on OFF on on OFF OFF OFF 3.4 3.8 3.8 3.8
It is also possible, of course, to determine the logic value by sensing the absolute voltage level of one input signal, called a single-ended input. Singleended signals are used in most ECL logic applications to avoid the obvious expense of doubling the number of signal lines. The basic CML inverter in Figure 3-89 has a single-ended input. It always has both outputs available internally; the circuit is actually either an inverter or a non-inverting buffer depending on whether we use OUT1 or OUT2. To perform logic with the basic circuit of Figure 3-89, we simply place additional transistors in parallel with Q1, similar to the approach in a TTL NOR gate. For example, Figure 3-90 shows a 2-input CML OR/NOR gate. If any input is HIGH, the corresponding input transistor is active, and VOUT1 is LOW (NOR output). At the same time, Q3 is OFF, and VOUT2 is HIGH (OR output). Recall that the input levels for the inverter/buffer are defined to be 3.6 and 4.4 V, while the output levels that it produces are 4.2 and 5.0 V. This is obviously
Figure 3-90 CML 2-input OR/NOR gate: (a) circuit diagram; (b) function table; (c) logic symbol; (d) truth table.
OUT1 OUT2
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a problem. We could put a diode in series with each output to lower it by 0.6 V to match the input levels, but that still leaves another problemthe outputs have poor fanout. A HIGH output must supply base current to the inputs that it drives, and this current creates an additional voltage drop across R1 or R2, reducing the output voltage (and we dont have much margin to work with). These problems are solved in commercial ECL families, such as the 10K family described next.
*3.14.2 ECL 10K/10H Families The packaged components in todays most popular ECL family have 5-digit part numbers of the form 10xxx (e.g., 10102, 10181, 10209), so the family is generically called ECL 10K. This family has several improvements over the basic CML circuit described previously:
An emitter-follower output stage shifts the output levels to match the input levels and provides very high current-driving capability, up to 50 mA per output. It is also responsible for the familys name, emitter-coupled logic. An internal bias network provides VBB without the need for a separate, external power supply. The family is designed to operate with VCC = 0 (ground) and VEE = 5.2 V. In most applications, ground signals are more noise-free than the powersupply signals. In ECL, the logic signals are referenced to the algebraically higher power-supply voltage rail, so the familys designers decided to make that 0 V (the clean ground) and use a negative voltage for VEE. The power-supply noise that does appear on VEE is a common-mod signal that is rejected by the input structures differential amplifier. Parts with a 10H prefix (the ECL 10H family) are fully voltage compensated, so they will work properly with power-supply voltages other than VEE = 5.2 V, as well discuss in Section 3.14.4. Logic LOW and HIGH levels are defined in the ECL 10K family as shown in Figure 3-91. Note that even though the power supply is negative, ECL assigns the names LOW and HIGH to the algebraically lower and higher voltages, respectively. DC noise margins in ECL 10K are much less than in CMOS and TTL, only 0.155 V in the LOW state and 0.125 V in the HIGH state. However, ECL gates do not need as much noise margin as these families. Unlike CMOS and TTL, an ECL gate generates very little power-supply and ground noise when it changes state; its current requirement remains constant as it merely steers current from one path to another. Also, ECLs emitter-follower outputs have very low impedance in either state, and it is difficult to couple noise from an external source into a signal line driven by such a low-impedance output.
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0 0
Figure 3-91 ECL 10K logic levels.
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ABNORMAL VIHmax VIHmin 0.810 HIGH 0.810 VOHmax 0.980 VOHmin 1.105 High-state DC noise margin Low-state DC noise margin ABNORMAL VILmax 1.475 1.630 VOLmax 1.850 VOLmin LOW VILmin 1.850 ABNORMAL
Figure 3-92(a) is the circuit for an ECL OR/NOR gate, one section of a quad OR/NOR gate with part number 10102. A pull-down resistor on each input ensures that if the input is left unconnected, it is treated as LOW. The bias network has component values selected to generate VBB = 1.29 V for proper operation of the differential amplifier. Each output transistor, using the emitterfollower configuration, maintains its emitter voltage at one diode-drop below its base voltage, thereby achieving the required output level shift. Figure 3-92(b) summarizes the electrical operation of the gate. The emitter-follower outputs used in ECL 10K require external pull-down resistors, as shown in the figure. The 10K family is designed to use external rather than internal pull-down resistors for good reason. The rise and fall times of ECL output transitions are so fast (typically 2 ns) that any connection longer than a few inches must be treated as a transmission line, and must be terminated as discussed in Section 12.4. Rather than waste power with an internal pulldown resistor, ECL 10K allows the designer to select an external resistor that satisfies both pull-down and transmission-line termination requirements. The simplest termination, sufficient for short connections, is to connect a resistor in the range of 270 to 2 k from each output to VEE. A typical ECL 10K gate has a propagation delay of 2 ns, comparable to 74AS TTL. With its outputs left unconnected, a 10K gate consumes about 26 mW of power, also comparable to a 74AS TTL gate, which consumes about 20 mW. However, the termination required by ECL 10K also consumes power, from 10 to 150 mW per output depending on the termination circuit configuration. A 74AS TTL output may or may not require a power-consuming termination circuit, depending on the physical characteristics of the application.
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(a)
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differential amplifier multiple inputs bias network complementary emitter-follower outputs VCC2 = 0 V VCC1 = 0 V X VX R3 220 R4 245 VC2 VC3 R7 907 Q5 VOUT1 OUT1 (NOR) Y VY Q1 Q2 Q3 Q4 VBB = 1.29 V Q6 VOUT2 OUT2 (OR) VE R1 50 k R2 50 k R5 779 R6 6.1 k R8 4.98 k RL1 VEE = 5.2 V (b) XY VX VY Q1 Q2 Q3 VE VC2 VC3 VOUT1 VOUT2 OUT1 OUT2 0.9 1.8 1.8 1.8 1.8 0.9 0.9 0.9 H L L L L H H H L L H H L H L H 1.8 1.8 0.9 0.9 1.8 0.9 1.8 0.9 OFF OFF on on OFF on OFF on on OFF OFF OFF 1.9 1.5 1.5 1.5 0.2 1.2 1.2 1.2 1.2 0.2 0.2 0.2 (c) XY 0 0 1 1 0 1 0 1 OUT1 OUT2 1 0 0 0 0 1 1 1 (d) X Y OUT1 OUT2
RL2
Figure 3-92 Two-input 10K ECL OR/NOR gate: (a) circuit diagram; (b) function table; (c) truth table; (d) logic symbol.
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positive ECL (PECL)
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*3.14.3 ECL 100K Family Members of the ECL 100K family have 6-digit part numbers of the form 100xxx (e.g., 100101, 100117, 100170), but in general have functions different than 10K parts with similar numbers. The 100K family has the following major differences from the 10K family: Reduced power-supply voltage, VEE = 4.5 V. Different logic levels, as a consequence of the different supply voltage. Shorter propagation delays, typically 0.75 ns. Shorter transition times, typically 0.70 ns. Higher power consumption, typically 40 mW per gate.
*3.14.4 Positive ECL (PECL) We described the advantage of noise immunity provided by ECLs negative power supply (VEE = 5.2 V or 4.5 V), but theres also a big disadvantage todays most popular CMOS and TTL logic families, ASICs, and microprocessors all use a positive power-supply voltage, typically +5.0 V but trending to +3.3 V. Systems incorporating both ECL and CMOS/TTL devices therefore require two power supplies. In addition, interfacing between standard, negative ECL 10K or 100K logic levels and positive CMOS/TTL levels requires special level-translation components that connect to both supplies. Positive ECL (PECL, pronounced peckle) uses a standard +5.0-V power supply. Note that theres nothing in the ECL 10K circuit design of Figure 3-92 that requires VCC to be grounded and VEE to be connected to a 5.2-V supply. The circuit will function exactly the same with VEE connected to ground, and VCC to a +5.2-V supply. Thus, PECL components are nothing more than standard ECL components with VEE connected to ground and VCC to a +5.0-V supply. The voltage between VEE and VCC is a little less than with standard 10K ECL and more than with standard 100K ECL, but the 10H-series and 100K parts are voltage compensated, designed to still work well with the supply voltage being a little high or low. Like ECL logic levels, PECL levels are referenced to VCC, so the PECL HIGH level is about VCC 0.9 V, and LOW is about VCC 1.7 V, or about 4.1 V and 3.3 V with a nominal 5-V VCC. Since these levels are referenced to VCC, they move up and down with any variations in VCC. Thus, PECL designs require particularly close attention to power distribution issues, to prevent noise on VCC from corrupting the logic levels transmitted and received by PECL devices. Recall that CML/ECL devices produce differential outputs and can have differential inputs. A differential input is relatively insensitive to the absolute voltage levels of an input-signal pair, and only to their difference. Therefore, differential signals can be used quite effectively in PECL applications to ease the noise concerns raised in the preceding paragraph.
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It is also quite common to provide differential PECL-compatible inputs and outputs on CMOS devices, allowing a direct interface between the CMOS device and a device such as a fiber-optic transceiver that expects ECL or PECL levels. In fact, as CMOS circuits have migrated to 3.3-V power supplies, it has even been possible to build PECL-like differential inputs and outputs that are simple referenced to the 3.3-V supply instead of a 5-V supply.
References
Students who need to study the basics may wish to consult Electrical Circuits Review by Bruce M. Fleischer. This 20-page tutorial covers all of the basic circuit concepts that are used in this chapter. It appears both as an appendix in this books first edition and as a PDF file on its web page, www.ddpp.com. If youre interested in history, a nice introduction to all of the early bipolar logic families can be found in Logic Design with Integrated Circuits by William E. Wickes (Wiley-Interscience, 1968). The classic introduction to TTL electrical characteristics appeared in The TTL Applications Handbook, edited by Peter Alfke and Ib Larsen (Fairchild Semiconductor, 1973). Early logic designers also enjoyed The TTL Cookbook by Don Lancaster. For another perspective on the electronics material in this chapter, you can consult almost any modern electronics text. Many contain a much more analytical discussion of digital circuit operation; for example, see Microelectronics by J. Millman and A. Grabel (McGraw-Hill, 1987, 2nd ed.). Another good introduction to ICs and important logic families can be found in VLSI System Design by Saburo Muroga (Wiley, 1982). For NMOS and CMOS circuits in particular, two good books are Introduction to VLSI Systems by Carver Mead and Lynn Conway (Addison-Wesley, 1980) and Principles of CMOS VLSI Design by Neil H. E. Weste and Kamran Eshraghian (Addison-Wesley, 1993). Characteristics of todays logic families can be found in the data books published by the device manufacturers. Both Texas Instruments and Motorola publish comprehensive data books for TTL and CMOS devices, as listed in Table 3-13. Both manufacturers keep up-to-date versions of their data books on the web, at www.ti.com and www.mot.com. Motorola also provides a nice introduction to ECL design in their MECL System Design Handbook (publ. HB205, rev. 1, 1988). Howie Johnson? BeeBop? The JEDEC standards for digital logic levels can be found on JEDECs web site, www.jedec.org. (Joint Electron Device Engineering Council). The JEDEC standards for 3.3-V, 2.5-V, and 1.8-V logic were published in 1994, 1995, and 1997, respectively.
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T a b l e 3 - 1 3 Manufacturers logic data books.
Order number Manufacturer Topics Title
Year
Texas Instrument Texas Instrument Texas Instrument Texas Instrument Texas Instrument Motorola Motorola Motorola
SDLD001
74, 74S, 74LS TTL 74AS, 74ALS TTL
TTL Logic Data Book F Logic Data Book
1988 1995 1994 1997 1997 1997 1989 1988 1988 1989
SDAD001C SDFD001B
ALS/AS Logic Data Book
74F TTL
SCLD001D
74HC, 74HCT CMOS 74AC, 74ACT CMOS
HC/HCT Logic Data Book AC/ACT Logic Data Book Fast and LSTTL Data FACT Data
SCAD001D SCLD003A
Texas Instrument
74AHC, 74AHCT CMOS
AHC/AHCT Logic Data Book High-Speed CMOS Data MECL Device Data
DL121/D DL129/D DL122/D
74F, 74LSTTL 74HC, 74HCT 74AC, 74ACT 10K ECL
Motorola
DL138/D
After seeing the results of last few decades amazing pace of development in digital electronics, its easy to forget that logic circuits had an important place in technologies that came before the transistor. In Chapter 5 of Introduction to the Methodology of Switching Circuits (Van Nostrand, 1972), George J. Klir shows how logic can be (and has been) performed by a variety of physical devices, including relays, vacuum tubes, and pneumatic systems.
Drill Problems
3.1
A particular logic family defines a LOW signal to be in the range 0.00.8 V, and a HIGH signal to be in the range 2.03.3 V. Under a positive-logic convention, indicate the logic value associated with each of the following signal levels: (a) (e) 0.0 V (b) 3.0 V (c) 0.8 V (d) 1.9 V 0.7 V 3.0 V
2.0 V
(f)
5.0 V
(g)
(h)
3.2 3.3 3.4 3.5
3.6 3.7 3.8 3.9
Repeat Drill 3.1 using a negative-logic convention. Discuss how a logic buffer amplifier is different from an audio amplifier. Is a buffer amplifier equivalent to a 1-input AND gate or a 1-input OR gate? True or false: For a given set of input values, a N AND gate produces the opposite output as a NOR gate. True or false: The Simpsons are a bipolar logic family. Write two completely different definitions of gate used in this chapter. What kind of transistors are used in CMOS gates? (Electrical engineers only.) Draw an equivalent circuit for a CMOS inverter using a single-pole, double-throw relay. Copying Prohibited
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A
B
C
D
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3.10 For a given silicon area, which is likely to be faster, a CMOS NAND gate or a CMOS NOR ? 3.11 Define fan-in and fanout. Which one are you likely to have to calculate? 3.12 Draw the circuit diagram, function table, and logic symbol for a 3-input CMOS NOR gate in the style of Figure 3-16. 3.13 Draw switch models in the style of Figure 3-14 for a 2-input CMOS N OR gate for all four input combinations. 3.14 Draw a circuit diagram, function table, and logic symbol for a CMOS OR gate in the style of Figure 3-19. 3.15 Which has fewer transistors, a CMOS inverting gate or a noninverting gate? 3.16 Name and draw the logic symbols of four different 4-input CMOS gates that each use 8 transistors. 3.17 The circuit in Figure X3.18(a) is a type of CMOS AND-OR-INVERT gate. Write a function table for this circuit in the style of Figure 3-15(b), and a corresponding logic diagram using AND and OR gates and inverters. 3.18 The circuit in Figure X3.18(b) is a type of CMOS OR-AND-INVERT gate. Write function table for this circuit in the style of Figure 3-15(b), and a corresponding logic diagram using AND and OR gates and inverters. 3.19 How is it that perfume can be bad for digital designers? 3.20 How much high-state DC noise margin is available in a CMOS inverter whose transfer characteristic under worst-case conditions looks like Figure 3-25? How much low-state DC noise margin is available? (Assume standard 1.5-V and 3.5-V thresholds for LOW and H IGH.) 3.21 Using the data sheet in Table 3-3, determine the worst-case LOW-state and HIGH state DC noise margins of the 74HC00. State any assumptions required by your answer. Copyright 1999 by John F. Wakerly
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Q8 A Q2 Q6 Q6 B Q4 Q8 Z Q4 Q2 Q3 Q1 Z Q1 C Q5 Q5 Q7 Q3 D Q7
Figure X3.18
(b)
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(a) 120 to VCC (b) (f) 270 to VCC and 330 to GND 75 to VCC and 150 to GND (c) (e) 1 K to GND 100 to VCC 75 to VCC (d) 150 to VCC and 150 to GND 270 to VCC and 150 to GND (g) (h) (a) R = 100 , C = 50 pF R = 1 K, C = 30 pF (b) R = 330 , C = 150 pF (c) (d) R = 4.7 K, C = 100 pF Copyright 1999 by John F. Wakerly
3.22 Section 3.5 defines seven different electrical parameters for CMOS circuits. Using the data sheet in Table 3-3, determine the worst-case value of each of these for the 74HC00. State any assumptions required by your answer. 3.23 Based on the conventions and definitions in Section 3.4, if the current at a device output is specified as a negative number, is the output sourcing current or sinking current? 3.24 For each of the following resistive loads, determine whether the output drive specifications of the 74HC00 over the commercial operating range are exceeded. (Refer to Table 3-3, and use VOHmin = 2.4 V and VCC = 5.0 V.)
3.25 Across the range of valid HIGH input levels, 2.05.0 V, at what input level would you expect the 74FCT257T (Table 3-3) to consume the most power? 3.26 Determine the LOW-state and HIGH-state DC fanout of the 74FCT257T when it drives 74LS00-like inputs. (Refer to Tables 3-3 and 3-12.) 3.27 Estimate the on resistances of the p-channel and n-channel output transistors of the 74FCT257T using information in Table 3-3. 3.28 Under what circumstances is it safe to allow an unused CMOS input to float? 3.29 Explain latch up and the circumstances under which it occurs. 3.30 Explain why putting all the decoupling capacitors in one corner of a printed-circuit board is not a good idea. 3.31 When is it important to hold hands with a friend? 3.32 Name the two components of CMOS logic gates delay. Which one is most affected by load capacitance? 3.33 Determine the RC time constant for each of the following resistor-capacitor combinations:
3.34 Besides delay, what other characteristic(s) of a CMOS circuit are affected by load capacitance? 3.35 Explain the IC formula in footnote 5 in Table 3-3 in terms of concepts presented in Sections 3.5 and 3.6. 3.36 It is possible to operate 74AC CMOS devices with a 3.3-volt power supply. How much power does this typically save, compared to 5-volt operation? 3.37 A particular Schmitt-trigger inverter has VILmax = 0.8 V, VIHmin = 2.0 V, VT+ = 1.6 V, and VT = 1.3 V. How much hysteresis does it have? 3.38 Why are three-state outputs usually designed to turn off faster than they turn on? Copying Prohibited
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3.39 Discuss the pros and cons of larger versus smaller pull-up resistors for open-drain CMOS outputs or open-collector TTL outputs. 3.40 A particular LED has a voltage drop of about 2.0 V in the on state, and requires about 5 mA of current for normal brightness. Determine an appropriate value for the pull-up resistor when the LED is connected as shown in Figure 3-52. 3.41 How does the answer for Drill 3.39 change if the LED is connected as shown in Figure 3-53(a)? 3.42 A wired-AND function is obtained simply by tying two open-drain or open-collector outputs together, without going through another level of transistor circuitry. How is it, then, that a wired-AND function can actually be slower than a discrete AND gate? (Hint: Recall the title of a Teenage Mutant Ninja Turtles movie.) 3.43 Which CMOS or TTL logic family in this chapter has the strongest output driving capability? 3.44 Concisely summarize the difference between HC and HCT logic families. The same concise statement should apply to AC versus ACT. 3.45 Why dont the specifications for FCT devices include parameters like VOLmaxC that apply to CMOS loads, as HCT and ACT specifications do? 3.46 How does FCT-T devices reduce power consumption compared to FCT devices? 3.47 How many diodes are required for an n-input diode AND gate? 3.48 True or false: A TTL NOR gate uses diode logic. 3.49 Are TTL outputs more capable of sinking current or sourcing current? 3.50 Compute the maximum fanout for each of the following cases of a TTL output driving multiple TTL inputs. Also indicate how much excess driving capability is available in the LOW or HIGH state for each case. (a) 74LS driving 74LS 74S driving 74AS (b) (f) 74LS driving 74S 74F driving 74S
3.51 Which resistor dissipates more power, the pull-down for an unused LS-TTL NOR-gate input, or the pull-up for an unused LS-TTL N AND-gate input? Use the minimum allowable resistor value in each case. 3.52 Which would you expect to be faster, a TTL AND gate or a TTL AND-OR-INVERT gate? Why? 3.53 Describe the main benefit and the main drawback of TTL gates that use Schottky transistors. 3.54 Using the data sheet in Table 3-12, determine the worst-case LOW-state and HIGH -state DC noise margins of the 74LS00. 3.55 Section 3.10 defines eight different electrical parameters for TTL circuits. Using the data sheet in Table 3-12, determine the worst-case value of each of these for the 74LS00.
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(c) (e) (d) 74AS driving 74AS 74AS driving 74F (g) 74ALS driving 74F (h) 74AS driving 74ALS Copying Prohibited
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(a) 470 to VCC 600 to VCC (b) (f) 330 to VCC and 470 to GND 510 to VCC and 510 to GND (c) (e) 10 K to GND (d) 390 to VCC and 390 to GND 220 to VCC and 330 to GND (g) 4.7 K to GND (h) (a) (c) 74HCT driving 74LS (b) 74VHCT driving 74AS 74S driving 74VHCT 74LS driving 74HCT (d) (a) 74HCT driving 74LS (b) 74HCT driving 74S (c) 74VHCT driving 74AS (d) 74VHCT driving 74LS
3.56 For each of the following resistive loads, determine whether the output drive specifications of the 74LS00 over the commercial operating range are exceeded. (Refer to Table 3-12, and use VOLmax = 0.5 V and VCC = 5.0 V.)
3.57 Compute the LOW-state and HIGH -state DC noise margins for each of the following cases of a TTL output driving a TTL-compatible CMOS input, or vice versa.
3.58 Compute the maximum fanout for each of the following cases of a TTL-compatible CMOS output driving multiple inputs in a TTL logic family. Also indicate how much excess driving capability is available in the LOW or HIGH state for each case.
3.59 For a given load capacitance and transition rate, which logic family in this chapter has the lowest dynamic power dissipation?
Exercises
3.60 Design a CMOS circuit that has the functional behavior shown in Figure X3.60. (Hint: Only six transistors are required.)
Figure X3.60
A Z
B C
3.61 Design a CMOS circuit that has the functional behavior shown in Figure X3.61. (Hint: Only six transistors are required.)
Figure X3.61
A Z
B C
3.62 Draw a circuit diagram, function table, and logic symbol in the style of Figure 3-19 for a CMOS gate with two inputs A and B and an output Z, where Z = 1 if A = 0 and B = 1, and Z = 0 otherwise. (Hint: O nly six transistors are required.) 3.63 Draw a circuit diagram, function table, and logic symbol in the style of Figure 3-19 for a CMOS gate with two inputs A and B and an output Z, where Copyright 1999 by John F. Wakerly Copying Prohibited
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3.65
3.66 3.67
3.68
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Z = 0 if A = 1 and B = 0, and Z = 1 otherwise. ( Hint: Only six transistors are needed.) Draw a figure showing the logical structure of an 8-input CMOS NOR gate, assuming that at most 4-input gate circuits are practical. Using your general knowledge of CMOS electrical characteristics, select a circuit structure that minimizes the NOR gates propagation delay for a given area of silicon, and explain why this is so. The circuit designers of TTL-compatible CMOS families presumably could have made the voltage drop across the on transistor under load in the H IGH state as little as it is in the LOW state, simply by making the p-channel transistors bigger. Why do you suppose they didnt bother to do this? How much current and power are wasted in Figure 3-32(b)? Perform a detailed calculation of VOUT in Figures 3-34 and 3-33. (Hint: Create a Thvenin equivalent for the CMOS inverter in each figure.) Consider the dynamic behavior of a CMOS output driving a given capacitive load. If the resistance of the charging path is double the resistance of the discharging path, is the rise time exactly twice the fall time? If not, what other factors affect the transition times? Analyze the fall time of the CMOS inverter output of Figure 3-37, assuming that RL = 1 k and VL = 2.5 V. Compare your answer with the results of Section 3.6.1 and explain. Repeat Exercise 3.68 for rise time. Assuming that the transistors in an FCT CMOS three-state buffer are perfect, zero-delay on-off devices that switch at an input threshold of 1.5 V, determine the value of tPLZ for the test circuit and waveforms in Figure 3-24. (Hint: You have to determine the time using an RC time constant.) Explain the difference between your result and the specifications in Table 3-3. Repeat Exercise 3.70 for tPHZ. Using the specifications in Table 3-6, estimate the on resistances of the p-channel and n-channel transistors in 74AC-series CMOS logic. Create a 4422 matrix of worst-case DC noise margins for the following CMOS interfacing situations: an (HC, HCT, VHC, or VHCT) output driving an (HC, HCT, VHC, or VHCT) input with a (CMOS, TTL) load in the (LOW, HIGH ) state; Figure X3.74 illustrates. (Hints: There are 64 different combinations to examine, but many give identical results. Some combinations yield negative margins.) In the LED example in Section 3.7.5, a designer chose a resistor value of 300 , and found that the open-drain gate was able to maintain its output at 0.1 V while driving the LED. How much current flows through the LED, and how much power is dissipated by the pull-up resistor in this case? Consider a CMOS 8-bit binary counter (Section 8.4) clocked at 16 MHz. For the purposes of computing dynamic power dissipation, what is the transition frequency of least significant bit? Of the most significant bit? For the purposes of Copying Prohibited
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Output HC HCT VHC VHCT HC
CL TL CL TL CL TL CL TL CH CL TH TL CH CL TH TL CH CL TH TL CH CL TH TL
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TH TL
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Key: CL = CMOS load, LOW CH = CMOS load, HIGH TL = TTL load, LOW TH = TTL load, HIGH
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determining the dynamic power dissipation of the eight output bits, what frequency should be used? Using only AND and N OR gates, draw a logic diagram for the logic function performed by the circuit in Figure 3-55. Calculate the approximate output voltage at Z in Figure 3-56, assuming that the gates are HCT-series CMOS. Redraw the circuit diagram of a CMOS 3-state buffer in Figure 3-48 using actual transistors instead of NAND , NOR, and inverter symbols. Can you find a circuit for the same function that requires a smaller total number of transistors? If so, draw it. Modify the CMOS 3-state buffer circuit in Figure 3-48 so that the output is in the High-Z state when the enable input is HIGH . The modified circuit should require no more transistors than the original. Using information in Table 3-3, estimate how much current can flow through each output pin when the outputs of two different 74FCT257Ts are fighting. A computer system made by the Green PC Company had ten LED status OK indicators, each of which was turned on by an open-collector output in the style of Figure 3-52. However, in order to save a few cents, the logic designer connected the anodes of all ten LEDs together and replaced the ten, now parallel, 300- pull-up resistors with a single 30- resistor. This worked fine in the lab, but a big problem was found after volume shipments began. Explain. Show that at a given power-supply voltage, an FCT-type ICCD specification can be derived from an HCT/ACT-type CPD specification, and vice versa. If both VZ and V_B in Figure 3-65(b) are 4.6 V, can we get VC = 5.2 V? Explain. Modify the program in Table 3-10 to account for leakage current in the OFF state. Assuming ideal conditions, what is the minimum voltage that will be recognized as a HIGH in the TTL NAND gate in Figure 3-75 with one input LOW and the other HIGH? Assuming ideal conditions, what is the maximum voltage that will be recognized as a LOW in the TTL NAND gate in Figure 3-75 with both inputs HIGH ? Find a commercial TTL part that can source 40 mA in the HIGH state. What is its application?
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3.89 What happens if you try to drive an LED with its cathode grounded and its anode connected to a TTL totem-pole output, analogous to Figure 3-53 for CMOS? 3.90 What happens if you try to drive a 12-volt relay with a TTL totem-pole output? 3.91 Suppose that a single pull-up resistor to +5 V is used to provide a constant-1 logic source to 15 different 74LS00 inputs. What is the maximum value of this resistor? How much HIGH-state DC noise margin are you providing in this case? 3.92 The circuit in Figure X3.92 uses open-collector NAND gates to perform wired logic. Write a truth table for output signal F and, if youve read Section 4.2, a logic expression for F as a function of the circuit inputs. 3.93 What is the maximum allowable value for R1 in Figure X3.92? Assume that a 0.7 V HIGH-state noise margin is required. The 74LS01 has the specs shown in the 74LS column of Table 3-11, except that IOHmax is 100 A, a leakage current that flows into the output in the HIGH state. 3.94 A logic designer found a problem in a certain circuits function after the circuit had been released to production and 1000 copies of it built. A portion of the circuit is shown in Figure X3.94 in black; all of the gates are 74LS00 NAND gates. The logic designer fixed the problem by adding the two diodes shown in color. What do the diodes do? Describe both the logical effects of this change on the circuits function and the electrical effects on the circuits noise margins.
+5V
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R1 R2 74LS01 W X G 74LS01 F
Figure X3.92
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Y Z
Figure X3.94
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+5V Thevenin equivalent of termination
Figure X3.95
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Thevenin termination R1 R bus R2 bus (a) (b)
V
3.95 A Thvenin termination for an open-collector or three-state bus has the structure shown in Figure X3.95(a). The idea is that, by selecting appropriate values of R1 and R2, a designer can obtain a circuit equivalent to the termination in (b) for any desired values of V and R. The value of V determines the voltage on the bus when no device is driving it, and the value of R is selected to match the characteristic impedance of the bus for transmission-line purposes (Section 12.4). For each of the following pairs of V and R, determine the required values of R1 and R2. (a) V = 2.75, R = 148.5 V = 3.0, R = 130 (b) V = 2.7, R = 180 V = 2.5, R = 75
(c)
(d)
3.96 For each of the R1 and R2 pairs in Exercise 3.95, determine whether the termination can be properly driven by a three-state output in each of the following logic families: 74LS, 74S, 74ACT. For proper operation, the familys IOL and IOH specs must not be exceeded when VOL = VOLmax and VOH = VOHmin, respectively. 3.97 Suppose that the output signal F in Figure 3.92 drives the inputs of two 74S04 inverters. Compute the minimum and maximum allowable values of R2, assuming that a 0.7 V HIGH-state noise margin is required. 3.98 A 74LS125 is a buffer with a three-state output. When enabled, the output can sink 24 mA in the LOW state and source 2.6 mA in the HIGH state. When disabled, the output has a leakage current of 20 A (the sign depends on the output voltageplus if the output is pulled HIGH by other devices, minus if its LOW). Suppose a system is designed with multiple modules connected to a bus, where each module has a single 74LS125 to drive the bus, and one 74LS04 to receive information on the bus. What is the maximum number of modules that can be connected to the bus without exceeding the 74LS125s specs? 3.99 Repeat Exercise 3.97, this time assuming that a single pull-up resistor is connected from the bus to +5 V to guarantee that the bus is HIGH when no device is driving it. Calculate the maximum possible value of the pull-up resistor, and the number of modules that can be connected to the bus. 3.100 Find the circuit design in a TTL data book for an actual three-state gate, and explain how it works. 3.101 Using the graphs in a TTL data book, develop some rules of thumb for derating the maximum propagation delay specification of LS-TTL under nonoptimal conditions of power-supply voltage, temperature, and loading. Copyright 1999 by John F. Wakerly Copying Prohibited
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3.102 Determine the total power dissipation of the circuit in Figure 3.102 as function of transition frequency f for two realizations: (a) using 74LS gates; (b) using 74HC gates. Assume that input capacitance is 3 pF for a TTL gate and 7 pF for a CMOS gate, that a 74LS gate has an internal power dissipation capacitance of 20 pF, and that there is an additional 20 pF of stray wiring capacitance in the circuit. Also assume that the X , Y, and Z inputs are always HIGH , and that input C is driven with a CMOS-level square wave with frequency f. Other information that you need for this problem can be found in Tables 3-5 and 3-11. State any other assumptions that you make. At what frequency does the TTL circuit dissipate less power than the CMOS circuit? 3.103 It is possible to drive one or more 74AC or 74HC inputs reliably with a 74LS TTL output by providing an external resistor to pull the TTL output all the way up to VCC in the HIGH state. What are the design issues in choosing a value for this pullup resistor?
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C X Y
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Combinational Logic Design Principles
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4
ogic circuits are classified into two types, combinational and sequential. A combinational logic circuit is one whose outputs depend only on its current inputs. The rotary channel selector knob on an old-fashioned television is like a combinational circuitits output selects a channel based only on the current position of the knob (input). The outputs of a sequential logic circuit depend not only on the current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time. The channel selector controlled by the up and down pushbuttons on a TV or VCR is a sequential circuitthe channel selection depends on the past sequence of up/down pushes, at least since when you started viewing 10 hours before, and perhaps as far back as when you first powered-up the device. Sequential circuits are discussed in Chapters xx through yy. A combinational circuit may contain an arbitrary number of logic gates and inverters but no feedback loops. A feedback loop is a signal path of a circuit that allows the output of a gate to propagate back to the input of that same gate; such a loop generally creates sequential circuit behavior. In combinational circuit analysis we start with a logic diagram, and proceed to a formal description of the function performed by that circuit, such as a truth table or a logic expression. In synthesis, we do the reverse, starting with a formal description and proceeding to a logic diagram.
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SYNTHESIS VS. DESIGN Logic circuit design is a superset of synthesis, since in a real design problem we usually start out with an informal (word or thought) description of the circuit. Often the most challenging and creative part of design is to formalize the circuit description, defining the circuits input and output signals and specifying its functional behavior by means of truth tables and equations. Once weve created the formal circuit description, we can usually follow a turn-the-crank synthesis procedure to obtain a logic diagram for a circuit with the required functional behavior. The material in the first four sections of this chapter is the basis for turn-the-crank procedures, whether the crank is turned by hand or by a computer. The last two sections describe actual design languages, ABEL and VHDL. When we create a design using one of these languages, a computer program can perform the synthesis steps for us. In later chapters well encounter many examples of the real design process.
Combinational circuits may have one or more outputs. Most analysis and synthesis techniques can be extended in an obvious way from single-output to multiple-output circuits (e.g., Repeat these steps for each output). Well also point out how some techniques can be extended in a not-so-obvious way for improved effectiveness in the multiple-output case. The purpose of this chapter is to give you a solid theoretical foundation for the analysis and synthesis of combinational logic circuits, a foundation that will be doubly important later when we move on to sequential circuits. Although most of the analysis and synthesis procedures in this chapter are automated nowadays by computer-aided design tools, you need a basic understanding of the fundamentals to use the tools and to figure out whats wrong when you get unexpected or undesirable results. With the fundamentals well in hand, it is appropriate next to understand how combinational functions can be expressed and analyzed using hardware description languages (HDLs). So, the last two sections of this chapter introduce basic features of ABEL and VHDL, which well use to design for all kinds of logic circuits throughout the balance of the text. Before launching into a discussion of combinational logic circuits, we must introduce switching algebra, the fundamental mathematical tool for analyzing and synthesizing logic circuits of all types.
4.1 Switching Algebra
Formal analysis techniques for digital circuits have their roots in the work of an English mathematician, George Boole. In 1854, he invented a two-valued algebraic system, now called Boolean algebra, to give expression . . . to the fundamental laws of reasoning in the symbolic language of a Calculus. Using this system, a philosopher, logician, or inhabitant of the planet Vulcan can forCopyright 1999 by John F. Wakerly Copying Prohibited
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mulate propositions that are true or false, combine them to make new propositions, and determine the truth or falsehood of the new propositions. For example, if we agree that People who havent studied this material are either failures or not nerds, and No computer designer is a failure, then we can answer questions like If youre a nerdy computer designer, then have you already studied this? Long after Boole, in 1938, Bell Labs researcher Claude E. Shannon showed how to adapt Boolean algebra to analyze and describe the behavior of circuits built from relays, the most commonly used digital logic elements of that time. In Shannons switching algebra, the condition of a relay contact, open or closed, is represented by a variable X that can have one of two possible values, 0 or 1. In todays logic technologies, these values correspond to a wide variety of physical conditionsvoltage HIGH or LOW, light off or on, capacitor discharged or charged, fuse blown or intact, and so onas we detailed in Table 3-1 on page 77. In the remainder of this section, we develop the switching algebra directly, using first principles and what we already know about the behavior of logic elements (gates and inverters). For more historical and/or mathematical treatments of this material, consult the References. 4.1.1 Axioms In switching algebra we use a symbolic variable, such as X, to represent the condition of a logic signal. A logic signal is in one of two possible conditionslow or high, off or on, and so on, depending on the technology. We say that X has the value 0 for one of these conditions and 1 for the other. For example, with the CMOS and TTL logic circuits in Chapter 3, the positive-logic convention dictates that we associate the value 0 with a LOW voltage and 1 with a HIGH voltage. The negative-logic convention makes the opposite association: 0 = HIGH and 1 = LOW. However, the choice of positive or negative logic has no effect on our ability to develop a consistent algebraic description of circuit behavior; it only affects details of the physical-to-algebraic abstraction, as well explain later in our discussion of duality. For the moment, we may ignore the physical realities of logic circuits and pretend that they operate directly on the logic symbols 0 and 1. The axioms (or postulates) of a mathematical system are a minimal set of basic definitions that we assume to be true, from which all other information about the system can be derived. The first two axioms of switching algebra embody the digital abstraction by formally stating that a variable X can take on only one of two values:
(A1)
X=0
Notice that we stated these axioms as a pair, with the only difference between A1 and A1 being the interchange of the symbols 0 and 1. This is a characteristic
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switching algebra positive-logic convention negative-logic convention axiom postulate
if X 1
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complement prime ( )
algebraic operator expression NOT operation
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(A2) If X = 0, then X = 1 (A2) If X = 1, then X = 0 Figure 4-1 Signal naming and algebraic notation for an inverter.
X Y = X
of all the axioms of switching algebra, and is the basis of the duality principle that well study later. In Section 3.3.3 we showed the design of an inverter, a logic circuit whose output signal level is the opposite (or complement) of its input signal level. We use a prime ( ) to denote an inverters function. That is, if a variable X denotes an inverters input signal, then X denotes the value of a signal on the inverters output. This notation is formally specified in the second pair of axioms:
As shown in Figure 4-1, the output of an inverter with input signal X may have an arbitrary signal name, say Y. However, algebraically, we write Y = X to say signal Y always has the opposite value as signal X. The prime () is an algebraic operator, and X is an expression, which you can read as X prime or NOT X. This usage is analogous to what youve learned in programming languages, where if J is an integer variable, then J is an expression whose value is 0 J. Although this may seem like a small point, youll learn that the distinction between signal names (X, Y), expressions (X), and equations (Y = X) is very important when we study documentation standards and software tools for logic design. In the logic diagrams in this book, we maintain this distinction by writing signal names in black and expressions in color.
In Section 3.3.6 we showed how to build a 2-input CMOS AND gate, a circuit whose output is 1 if both of its inputs are 1. The function of a 2-input AND gate is sometimes called logical multiplication and is symbolized algebraically by a multiplication dot (). That is, an AND gate with inputs X and Y has an output signal whose value is X Y, as shown in Figure 4-2(a). Some authors, especially mathematicians and logicians, denote logical multiplication with a wedge X Y). We follow standard engineering practice by using the dot (X Y). When
NOTE ON NOTATION
The notations X, ~ X, and X are also used by some authors to denote the complement of X. The overbar notation is probably the most widely used and the best looking typographically. However, we use the prime notation to get you used to writing logic expressions on a single text line without the more graphical overbar, and to force you to parenthesize complex complemented subexpressionsbecause this is what youll have to do when you use HDLs and other tools.
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we study hardware design languages (HDLs), well encounter several other symbols that are used to denote the same thing. We also described in Section 3.3.6 how to build a 2-input CMOS OR gate, a circuit whose output is 1 if either of its inputs is 1. The function of a 2-input OR gate is sometimes called logical addition and is symbolized algebraically by a plus sign (+). An OR gate with inputs X and Y has an output signal whose value is X + Y, as shown in Figure 4-2(b). Some authors denote logical addition with a vee (X Y), but we follow the standard engineering practice of using the plus sign (X + Y). Once again, other symbols may be used in HDLs. By convention, in a logic expression involving both multiplication and addition, multiplication has precedence, just as in integer expressions in conventional programming languages. That is, the expression W X + Y Z is equivalent to (W X) + (Y Z). The last three pairs of axioms state the formal definitions of the AND and OR operations by listing the output produced by each gate for each possible input combination:
(A3) 00=0 (A3) 1+1=1 (A4) 11=1 (A4) 0+0=0
The five pairs of axioms, A1A5 and A1A5, completely define switching algebra. All other facts about the system can be proved using these axioms as a starting point.
JUXT A MINUTE
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X Y Z=XY X Y Z=X+Y (a) (b)
Figure 4-2 Signal naming and algebraic notation: (a) AND gate; (b) OR gate.
logical addition
precedence
AND operation OR operation
(A5)
01=10=0
(A5)
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Older texts use simple juxtaposition (XY) to denote logical multiplication, but we dont. In general, juxtaposition is a clear notation only when signal names are limited to a single character. Otherwise, is X Y a logical product or a two-character signal name? One-character variable names are common in algebra, but in real digital design problems, we prefer to use multicharacter signal names that mean something. Thus, we need a separator between names, and the separator might just as well be a multiplication dot rather than a space. The HDL equivalent of the multiplication dot (often * or &) is absolutely required when logic formulas are written in a hardware design language.
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Ta b l e 4 - 1 Switching-algebra theorems with one variable. (T1)
X+0=X X+1=1
(T1 ) (T2 ) (T3 )
X1=X X0=0
(Identities)
(T2) (T4) (T5)
(Null elements) (Idempotency) (Involution) (Complements)
(T3)
X+X=X
XX=X
(X ) = X
X + X = 1
(T5 )
X X = 0
4.1.2 Single-Variable Theorems During the analysis or synthesis of logic circuits, we often write algebraic expressions that characterize a circuits actual or desired behavior. Switchingalgebra theorems are statements, known to be always true, that allow us to manipulate algebraic expressions to allow simpler analysis or more efficient synthesis of the corresponding circuits. For example, the theorem X + 0 = X allows us to substitute every occurrence of X + 0 in an expression with X. Table 4-1 lists switching-algebra theorems involving a single variable X. How do we know that these theorems are true? We can either prove them ourselves or take the word of someone who has. OK, were in college now, lets learn how to prove them. Most theorems in switching algebra are exceedingly simple to prove using a technique called perfect induction. Axiom A1 is the key to this technique since a switching variable can take on only two different values, 0 and 1, we can prove a theorem involving a single variable X by proving that it is true for both X = 0 and X = 1. For example, to prove theorem T1, we make two substitutions:
[X = 0] 0+0=0 1+0=1 true, according to axiom A4 true, according to axiom A5 [X = 1]
All of the theorems in Table 4-1 can be proved using perfect induction, as youre asked to do in the Drills 4.2 and 4.3.
4.1.3 Two- and Three-Variable Theorems Switching-algebra theorems with two or three variables are listed in Table 4-2. Each of these theorems is easily proved by perfect induction, by evaluating the theorem statement for the four possible combinations of X and Y, or the eight possible combinations of X, Y, and Z. The first two theorem pairs concern commutativity and associativity of logical addition and multiplication and are identical to the commutative and associative laws for addition and multiplication of integers and reals. Taken together, they indicate that the parenthesization or order of terms in a logical sum or logical product is irrelevant. For example, from a strictly algebraic point of view, an expression such as W X Y Z is ambiguous; it should be written as (W (X (Y Z))) or (((W X) Y) Z) or (W X) (Y Z) (see Exercise 4.29). But the theorems tell us that the ambiguous form of the expression is OK
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(T6) (T7)
(T8) (T9)
(T10) (T11)
(T11)
because we get the same results in any case. We even could have rearranged the order of the variables (e.g., X Z Y W) and gotten the same results. As trivial as this discussion may seem, it is very important because it forms the theoretical basis for using logic gates with more than two inputs. We defined and + as binary operatorsoperators that combine two variables. Yet we use 3-input, 4-input, and larger AND and OR gates in practice. The theorems tell us we can connect gate inputs in any order; in fact, many printed-circuit-board and ASIC layout programs take advantage of this. We can use either one n-input gate or (n 1) 2-input gates interchangeably, though propagation delay and cost are likely to be higher with multiple 2-input gates. Theorem T8 is identical to the distributive law for integers and realsthat is, logical multiplication distributes over logical addition. Hence, we can multiply out an expression to obtain a sum-of-products form, as in the example below: V (W + X) (Y + Z) = V W Y + V W Z + V X Y + V X Z However, switching algebra also has the unfamiliar property that the reverse is truelogical addition distributes over logical multiplicationas demonstrated by theorem T8. Thus, we can also add out an expression to obtain a productof-sums form: (V W X) + (Y Z) = (V + Y) (V + Z) (W + Y) (W + Z) (X + Y) (X + Z) Theorems T9 and T10 are used extensively in the minimization of logic functions. For example, if the subexpression X + X Y appears in a logic expression, the covering theorem T9 says that we need only include X in the expression; X is said to cover X Y. The combining theorem T10 says that if the subexpression X Y + X Y appears in an expression, we can replace it with X. Since Y must be 0 or 1, either way the original subexpression is 1 if and only if X is 1.
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Ta b l e 4 - 2 Switching-algebra theorems with two or three variables.
X+Y=Y+X
(T6)
XY=YX
(Commutativity) (Associativity)
(X + Y) + Z = X + (Y + Z)
X+XY=X
(T7)
(X Y) Z = X (Y Z)
X (X + Y)=X
X Y + X Z = X (Y + Z)
(T8)
(X + Y) (X + Z) = X + Y Z (Distributivity) (Covering)
(T9)
X Y + X Y = X
(T10)
(X + Y) (X + Y)=X
(Combining) (Consensus)
X Y + X Z + Y Z = X Y + X Z
(X + Y) (X + Z) (Y + Z) = (X + Y) (X+ Z)
binary operator
covering theorem cover combining theorem
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consensus theorem consensus
finite induction basis step induction step
DeMorgans theorems
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X+XY = X1+XY
Although we could easily prove T9 by perfect induction, the truth of T9 is more obvious if we prove it using the other theorems that weve proved so far:
(according to T1) (according to T8) (according to T2) = X (1 + Y) = X1 =X
(according to T1)
Likewise, the other theorems can be used to prove T10, where the key step is to use T8 to rewrite the left-hand side as X (Y + Y). Theorem T11 is known as the consensus theorem. The Y Z term is called the consensus of X Y and X Z. The idea is that if Y Z is 1, then either X Y or X Z must also be 1, since Y and Z are both 1 and either X or X must be 1. Thus. the Y Z term is redundant and may be dropped from the right-hand side of T11. The consensus theorem has two important applications. It can be used to eliminate certain timing hazards in combinational logic circuits, as well see in Section 4.5. And it also forms the basis of the iterative-consensus method of finding prime implicants (see References). In all of the theorems, it is possible to replace each variable with an arbitrary logic expression. A simple replacement is to complement one or more variables:
(X + Y) + Z = X + (Y + Z) (based on T7)
But more complex expressions may be substituted as well:
(V + X) (W (Y + Z)) + (V + X) (W (Y + Z)) = V + X
(based on T10)
4.1.4 n-Variable Theorems Several important theorems, listed in Table 4-3, are true for an arbitrary number of variables, n. Most of these theorems can be proved using a two-step method called finite inductionfirst proving that the theorem is true for n = 2 (the basis step) and then proving that if the theorem is true for n = i, then it is also true for n = i + 1 (the induction step). For example, consider the generalized idempotency theorem T12. For n = 2, T12 is equivalent to T3 and is therefore true. If it is true for a logical sum of i Xs, then it is also true for a sum of i + 1 Xs, according to the following reasoning: X + X + X + + X = X + (X + X + + X) (i + 1 Xs on either side)
= X + (X) (if T12 is true for n = i) (according to T3) =X
Thus, the theorem is true for all finite values of n. DeMorgans theorems (T13 and T13) are probably the most commonly used of all the theorems of switching algebra. Theorem T13 says that an n-input
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(T12) (T12) (T13) (T13) (T14)
(T15) (T15)
AND gate whose output is complemented is equivalent to an n-input OR gate whose inputs are complemented. That is, the circuits of Figure 4-3(a) and (b) are equivalent. In Section 3.3.4 we showed how to build a CMOS NAND gate. The output of a NAND gate for any set of inputs is the complement of an AND gates output for the same inputs, so a NAND gate can have the logic symbol in Figure 4-3(c). However, the CMOS NAND circuit is not designed as an AND gate followed by a transistor inverter (NOT gate); its just a collection of transistors that happens to perform the AND-NOT function. In fact, theorem T13 tells us that the logic symbol in (d) denotes the same logic function (bubbles on the OR-gate inputs indicate logical inversion). That is, a NAND gate may be viewed as performing a NOT-OR function. By observing the inputs and output of a NAND gate, it is impossible to determine whether it has been built internally as an AND gate followed by an inverter, as inverters followed by an OR gate, or as a direct CMOS realization, because all NAND circuits perform precisely the same logic function. Although the choice of symbol has no bearing on the functionality of a circuit, well show in Section 5.1 that the proper choice can make the circuits function much easier to understand.
Figure 4-3 Equivalent circuits according to DeMorgans theorem T13: (a) AND-NOT; (b) NOT-OR; (c) logic symbol for a NAND gate; (d) equivalent symbol for a NAND gate.
(a) X Y XY Z = (X Y) (c) X Y
(b)
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Ta b l e 4 - 3 Switching-algebra theorems with n variables. X+X++X=X XX X=X (X1 X2 Xn) = X1 + X2+ + Xn (X + X + + X ) = X X X
1 2
(Generalized idempotency) (DeMorgans theorems)
n
1
2
n
[F(X1,X2,,Xn,+, )] = F(X1,X2,, Xn, , +)
(Generalized DeMorgans theorem)
(Shannons expansion theorems) F(X1,X2,,Xn) = X1 F(1X2,,Xn) + X1 F(0,X2,,Xn) F(X1,X2,,Xn) = [X1 + F(0,X2, ,Xn)] [X1 + F(1,X2,,Xn)]
Z = (X Y)
X Y
X Y
Z = X + Y
(d)
X Y
Z = X + Y
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X+Y Z = (X + Y) X Y Z = (X + Y)
generalized DeMorgans theorem complement of a logic expression
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(a) (c) X Y X Y (b) Z = X Y (d) X Y
Z = X Y
Figure 4-4 Equivalent circuits according to DeMorgans theorem T13: (a) OR-NOT; (b) NOT-AND; (c) logic symbol for a NOR gate; (d) equivalent symbol for a NOR gate.
A similar symbolic equivalence can be inferred from theorem T13. As shown in Figure 4-4, a NOR gate may be realized as an OR gate followed by an inverter, or as inverters followed by an AND gate. Theorems T13 and T13 are just special cases of a generalized DeMorgans theorem, T14, that applies to an arbitrary logic expression F. By definition, the complement of a logic expression, denoted (F), is an expression whose value is the opposite of Fs for every possible input combination. Theorem T14 is very important because it gives us a way to manipulate and simplify the complement of an expression. Theorem T14 states that, given any n-variable logic expression, its complement can be obtained by swapping + and and complementing all variables. For example, suppose that we have
F(W ,X,Y,Z) = (W X) + (X Y) + (W (X + Z))
= ((W ) X) + (X Y) + (W ((X) + (Z)))
In the second line we have enclosed complemented variables in parentheses to remind you that the is an operator, not part of the variable name. Applying theorem T14, we obtain
[F(W ,X,Y,Z)] = ((W) + X) (X + Y) (W + ((X) (Z))) [F(W,X,Y,Z)] = (W) + X) (X + Y) (W + (X (Z))
Using theorem T4, this can be simplified to
In general, we can use theorem T14 to complement a parenthesized expression by swapping + and , complementing all uncomplemented variables, and uncomplementing all complemented ones. The generalized DeMorgans theorem T14 can be proved by showing that all logic functions can be written as either a sum or a product of subfunctions,
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and then applying T13 and T13 recursively. However, a much more enlightening and satisfying proof can be based on the principle of duality, explained next.
4.1.5 Duality We stated all of the axioms of switching algebra in pairs. The primed version of each axiom (e.g., A5 ) is obtained from the unprimed version (e.g., A5) by simply swapping 0 and 1 and, if present, and +. As a result, we can state the following metatheorem, a theorem about theorems:
Principle of Duality Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and and + are swapped throughout. The metatheorem is true because the duals of all the axioms are true, so duals of all switching-algebra theorems can be proved using duals of the axioms. After all, whats in a name, or in a symbol for that matter? If the software that was used to typeset this book had a bug, one that swapped 0 1 and + throughout this chapter, you still would have learned exactly the same switching algebra; only the nomenclature would have been a little weird, using words like product to describe an operation that uses the symbol +. Duality is important because it doubles the usefulness of everything that you learn about switching algebra and manipulation of switching functions. Stated more practically, from a students point of view, it halves the amount that you have to learn! For example, once you learn how to synthesize two-stage AND-OR logic circuits from sum-of-products expressions, you automatically know a dual technique to synthesize OR -AND circuits from product-of-sums expressions. There is just one convention in switching algebra where we did not treat and + identically, so duality does not necessarily hold truecan you figure out what it is before reading the answer below? Consider the following statement of theorem T9 and its clearly absurd dual:
X+X Y = X X X+Y = X X+Y = X
Obviously the last line above is falsewhere did we go wrong? The problem is in operator precedence. We were able to write the left-hand side of the first line without parentheses because of our convention that has precedence. However, once we applied the principle of duality, we should have given precedence to + instead, or written the second line as X (X + Y) = X. The best way to avoid problems like this is to parenthesize an expression fully before taking its dual. Let us formally define the dual of a logic expression . If F(X1,X2,,Xn,+, ,) is a fully parenthesized logic expression involving the variables X1,X2,,Xn and
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metatheorem
(theorem T9)
(after applying the principle of duality) (after applying theorem T3)
dual of a logic expression
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(a) X Y
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(b) X Y (c) X Y Z =X+Y
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type 1
Z
type 1
Z =XY
type 1
X
Y
Z
X 0 0 1 1
Y 0 1 0 1
Z 0 0 0 1
X 1 1 0 0
Y 1 0 1 0
Z 1 1 1 0
LOW LOW
LOW
LOW LOW
HIGH LOW
HIGH HIGH
LOW
HIGH
HIGH
Figure 4-5 A type-1logic gate: (a) electrical function table; (b) logic function table and symbol with positive logic; (c) logic function table and symbol with negative logic.
the operators +, , and , then the dual of F, written FD, is the same expression with + and swapped:
FD(X1,X2,,Xn,+, ,) = F(X1,X2,,Xn, ,+,)
You already knew this, of course, but we wrote the definition in this way just to highlight the similarity between duality and the generalized DeMorgans theorem T14, which may now be restated as follows:
[F(X1,X2,,Xn)] = FD(X1,X2,,Xn)
Lets examine this statement in terms of a physical network. Figure 4-5(a) shows the electrical function table for a logic element that well simply call a type-1 gate. Under the positive-logic convention (LOW = 0 and HIGH = 1), this is an AND gate, but under the negative-logic convention (LOW = 1 and HIGH = 0), it is an OR gate, as shown in (b) and (c). We can also imagine a type-2 gate, shown in Figure 4-6, that is a positive-logic OR or a negative-logic AND . Similar tables can be developed for gates with more than two inputs.
Figure 4-6 A type-2 logic gate: (a) electrical function table; (b) logic function table and symbol with positive logic; (c) logic function table and symbol with negative logic.
(b) X Y
type 2
X Y
type 2
Z
Z =X+Y
(c)
X Y
type 2
Z = X Z
X
Y
Z
X 0 0 1 1
Y 0 1 0 1
Z 0 1 1 1
X 1 1 0 0
Y 1 0 1 0
Z 1 0 0 0
LOW LOW
LOW
LOW
HIGH LOW
HIGH
HIGH HIGH
HIGH HIGH
HIGH
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X4 X5
Xn
Figure 4-7 Circuit for a logic function using inverters and type-1 and type-2 gates under a positive-logic convention.
Suppose that we are given an arbitrary logic expression, F(X1,X2,,Xn). Following the positive-logic convention, we can build a circuit corresponding to this expression using inverters for NOT operations, type-1 gates for AND, and type-2 gates for OR, as shown in Figure 4-7. Now suppose that, without changing this circuit, we simply change the logic convention from positive to negative. Then we should redraw the circuit as shown in Figure 4-8. Clearly, for every possible combination of input voltages (HIGH and LOW), the circuit still produces the same output voltage. However, from the point of view of switching algebra, the output value0 or 1is the opposite of what it was under the positive-logic convention. Likewise, each input value is the opposite of what it was. Therefore, for each possible input combination to the circuit in Figure 4-7, the output is the opposite of that produced by the opposite input combination applied to the circuit in Figure 4-8:
F(X1,X2,,Xn) = [FD(X1,X2,,Xn)]
X1 X2 X3
X4 X5
Xn
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type 1 type 2 type 2 type 1 type 2 type 1 type 1
F(X1, X2, ... , Xn)
type 1
type 2
type 1
type 2
type 2
Figure 4-8 Negative-logic interpretation of the previous circuit.
type 1
type 2
type 1
type 1
FD(X1, X2, ... , Xn)
type 1
type 2
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truth table
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By complementing both sides, we get the generalized DeMorgans theorem:
[F(X1,X2,,Xn)] = FD(X1,X2,,Xn)
Ta b l e 4 - 4 t General truth table structure for a 3-variable logic function, F(X,Y,Z).
Row
X Y Z F
Amazing! So, we have seen that duality is the basis for the generalized DeMorgans theorem. Going forward, duality will halve the number of methods you must learn to manipulate and simplify logic functions.
4.1.6 Standard Representations of Logic Functions Before moving on to analysis and synthesis of combinational logic functions well introduce some necessary nomenclature and notation. The most basic representation of a logic function is the truth table. Similar in philosophy to the perfect-induction proof method, this brute-force representation simply lists the output of the circuit for every possible input combination. Traditionally, the input combinations are arranged in rows in ascending binary counting order, and the corresponding output values are written in a column next to the rows. The general structure of a 3-variable truth table is shown below in Table 4-4.
0
0
0
0
F(0,0,0) F(0,0,1) F(0,1,0) F(0,1,1) F(1,0,0) F(1,0,1) F(1,1,0) F(1,1,1)
1 2 3 4 5 6 7
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
The rows are numbered 07 corresponding to the binary input combinations, but this numbering is not an essential part of the truth table. The truth table for a particular 3-variable logic function is shown in Table 4-5. Each distinct pattern of 0s and 1s in the output column yields a different logic function; there are 28 such patterns. Thus, the logic function in Table 4-5 is one of 28 different logic functions of three variables. The truth table for an n-variable logic function has 2n rows. Obviously, truth tables are practical to write only for logic functions with a small number of variables, say, 10 for students and about 45 for everyone else.
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The information contained in a truth table can also be conveyed algebraically. To do so, we first need some definitions:
A literal is a variable or the complement of a variable. Examples: X, Y, X, Y .
A product term is a single literal or a logical product of two or more literals. Examples: Z, W X Y, X Y Z, W Y Z. A sum-of-products expression is a logical sum of product terms. Example: Z + W X Y + X Y Z + W Y Z .
A sum term is a single literal or a logical sum of two or more literals. Examples: Z, W + X + Y, X + Y + Z, W + Y + Z. A product-of-sums expression is a logical product of sum terms. Example: Z (W + X + Y) (X + Y + Z) (W + Y + Z). A normal term is a product or sum term in which no variable appears more than once. A nonnormal term can always be simplified to a constant or a normal term using one of theorems T3, T3, T5, or T5. Examples of nonnormal terms: W X X Y, W + W + X + Y, X X Y. Examples of normal terms: W X Y, W + X + Y.
An n-variable minterm is a normal product term with n literals. There are 2n such product terms. Examples of 4-variable minterms: W X Y Z, W X Y Z, W X Y Z. An n-variable maxterm is a normal sum term with n literals. There are 2n such sum terms. Examples of 4-variable maxterms: W + X + Y + Z, W + X + Y + Z, W + X + Y + Z. There is a close correspondence between the truth table and minterms and maxterms. A minterm can be defined as a product term that is 1 in exactly one row of the truth table. Similarly, a maxterm can be defined as a sum term that is 0 in exactly one row of the truth table. Table 4-6 shows this correspondence for a 3-variable truth table.
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0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 Ta b l e 4 - 5 Truth table for a particular 3-variable logic function, F(X,Y,Z). literal product term sum-of-products expression sum term product-of-sums expression normal term minterm maxterm
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Row
X Y Z F
minterm number minterm i
maxterm i
canonical sum
minterm list on-set
canonical product
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Ta b l e 4 - 6 Minterms and maxterms for a 3-variable logic function, F(X,Y,Z).
Minterm Maxterm
0 1 2 3 4 5 6 7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
F(0,0,0) F(0,0,1) F(0,1,0) F(0,1,1) F(1,0,0) F(1,0,1) F(1,1,0) F(1,1,1)
X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z XYZ X Y Z
X+Y+Z
X + Y + Z X + Y + Z X + Y + Z
X + Y + Z X + Y + Z X + Y + Z
X + Y + Z
An n-variable minterm can be represented by an n-bit integer, the minterm number. Well use the name minterm i to denote the minterm corresponding to row i of the truth table. In minterm i, a particular variable appears complemented if the corresponding bit in the binary representation of i is 0; otherwise, it is uncomplemented. For example, row 5 has binary representation 101 and the corresponding minterm is X Y Z. As you might expect, the correspondence for maxterms is just the opposite: in m axterm i, a variable appears complemented if the corresponding bit in the binary representation of i is 1. Thus, maxterm 5 (101) is X + Y + Z. Based on the correspondence between the truth table and minterms, we can easily create an algebraic representation of a logic function from its truth table. The canonical sum of a logic function is a sum of the minterms corresponding to truth-table rows (input combinations) for which the function produces a 1 output. For example, the canonical sum for the logic function in Table 4-5 on page 205 is
F = X,Y,Z(0,3,4,6,7)
= X Y Z + X Y Z + X Y Z + X Y Z + X Y Z
Here, the notation X,Y,Z(0,3,4,6,7) is a minterm list and means the sum of minterms 0, 3, 4, 6, and 7 with variables X, Y, and Z. The minterm list is also known as the on-set for the logic function. You can visualize that each minterm turns on the output for exactly one input combination. Any logic function can be written as a canonical sum. The canonical product of a logic function is a product of the maxterms corresponding to input combinations for which the function produces a 0 output. For example, the canonical product for the logic function in Table 4-5 is
F = X,Y,Z(1,2,5)
= (X + Y + Z) (X + Y + Z) (X + Y + Z)
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Here, the notation X,Y,Z(1,2,5) is a maxterm list and means the product of maxterms 1, 2, and 5 with variables X, Y, and Z. The maxterm list is also known as the off-set for the logic function. You can visualize that each maxterm turns off the output for exactly one input combination. Any logic function can be written as a canonical product. Its easy to convert between a minterm list and a maxterm list. For a function of n variables, the possible minterm and maxterm numbers are in the set {0, 1, , 2n 1}; a minterm or maxterm list contains a subset of these numbers. To switch between list types, take the set complement, for example,
A,B,C(0,1,2,3) = A,B,C(4,5,6,7) X,Y(1) = X,Y(0,2,3)
We have now learned five possible representations for a combinational logic function: 1. 2. 3. 4. 5. A truth table. An algebraic sum of minterms, the canonical sum. A minterm list using the notation. An algebraic product of maxterms, the canonical product. A maxterm list using the notation.
Each one of these representations specifies exactly the same information; given any one of them, we can derive the other four using a simple mechanical process.
4.2 Combinational Circuit Analysis
We analyze a combinational logic circuit by obtaining a formal description of its logic function. Once we have a description of the logic function, a number of other operations are possible:
We can determine the behavior of the circuit for various input combinations. We can manipulate an algebraic description to suggest different circuit structures for the logic function. We can transform an algebraic description into a standard form corresponding to an available circuit structure. For example, a sum-of-products expression corresponds directly to the circuit structure used in PLDs (programmable logic devices). We can use an algebraic description of the circuits functional behavior in the analysis of a larger system that includes the circuit.
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maxterm list off-set
W,X,Y,Z(0,1,2,3,5,7,11,13) = W,X,Y,Z(4,6,8,9,10,12,14,15)
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X Y Z
Figure 4-9 A three-input, oneoutput logic circuit.
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F
Given a logic diagram for a combinational circuit, such as Figure 4-9, there are a number of ways to obtain a formal description of the circuits function. The most primitive functional description is the truth table. Using only the basic axioms of switching algebra, we can obtain the truth table of an n-input circuit by working our way through all 2n input combinations. For each input combination, we determine all of the gate outputs produced by that input, propagating information from the circuit inputs to the circuit outputs. Figure 4-10 applies this exhaustive technique to our example circuit. Written on each signal line in the circuit is a sequence of eight logic values, the values present on that line when the circuit inputs XYZ are 000, 001, , 111. The truth table can be written by transcribing the output sequence of the final OR gate, as
Figure 4-10 Gate outputs created by all input combinations.
00001111 11001100
X Y Z
00001111 00110011 01010101
11001111
01010101
01000101
11110000 00110011 10101010
01100101 F
00100000
A LESS EXHAUSTING WAY TO GO
You can easily obtain the results in Figure 4-10 with typical logic design tools that include a logic simulator. First, you draw the schematic. Then, you apply the outputs of a 3-bit binary counter to the X, Y, and Z inputs. (Most simulators have such counter outputs built-in for just this sort of exercise.) The counter repeatedly cycles through the eight possible input combinations, in the same order that weve shown in the figure. The simulator allows you to graph the resulting signal values at any point in the schematic, including the intermediate points as well as the output.
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X Y Z F
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shown in Table 4-7. Once we have the truth table for the circuit, we can also directly write a logic expressionthe canonical sum or productif we wish. The number of input combinations of a logic circuit grows exponentially with the number of inputs, so the exhaustive approach can quickly become exhausting. Instead, we normally use an algebraic approach whose complexity is more linearly proportional to the size of the circuit. The method is simplewe build up a parenthesized logic expression corresponding to the logic operators and structure of the circuit. We start at the circuit inputs and propagate expressions through gates toward the output. Using the theorems of switching algebra, we may simplify the expressions as we go, or we may defer all algebraic manipulations until an output expression is obtained. Figure 4-11 applies the algebraic technique to our example circuit. The output function is given on the output of the final OR gate:
F = ((X+Y) Z) + (X Y Z)
No switching-algebra theorems were used in obtaining this expression. However, we can use theorems to transform this expression into another form. For example, a sum of products can be obtained by multiplying out:
F = X Z + Y Z + X Y Z
X Y Z
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0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 Ta b l e 4 - 7 Truth table for the logic circuit of Figure 4-9.
Y X + Y (X + Y ) Z
Figure 4-11 Logic expressions for signal lines.
X
F = ((X + Y) Z ) + (X Y Z)
X Y Z
Z
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XZ
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Y Y Y Z X Z X Y Z Z
F = X Z + Y Z + X Y Z
Figure 4-12 Two-level AND-OR circuit.
The new expression corresponds to a different circuit for the same logic function, as shown in Figure 4-12. Similarly, we can add out the original expression to obtain a product of sums:
F = ((X + Y) Z) + (X Y Z)
= (X + Y + X) (X + Y + Y) (X + Y + Z) (Z + X) (Z + Y) (Z + Z)
= 1 1 (X + Y + Z) (X + Z) (Y + Z) 1 = (X + Y + Z) (X + Z) (Y + Z)
The corresponding logic circuit is shown in Figure 4-13. Our next example of algebraic analysis uses a circuit with NAND and NOR gates, shown in Figure 4-14. This analysis is a little messier than the previous example, because each gate produces a complemented subexpression, not just a simple sum or product. However, the output expression can be simplified by repeated application of the generalized DeMorgans theorem:
Figure 4-13 Two-level OR-AND circuit.
Y Z
X
X + Y + Z
X + Z
F = (X + Y + Z) (X + Z) (Y + Z)
X
Y Z
Y+Z
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Z
Quite often, DeMorgans theorem can be applied graphically to simplify algebraic analysis. Recall from Figures 4-3 and 4-4 that NAND and NOR gates each have two equivalent symbols. By judiciously redrawing Figure 4-14, we make it possible to cancel out some of the inversions during the analysis by using theorem T4 [(X) = X], as shown in Figure 4-15. This manipulation leads us to a simplified output expression directly:
F = ((W + X) Y) (W + X + Y) (W + Z)
Figures 4-14 and 4-15 were just two different ways of drawing the same physical logic circuit. However, when we simplify a logic expression using the theorems of switching algebra, we get an expression corresponding to a different physical circuit. For example, the simplified expression above corresponds to the circuit of Figure 4-16, which is physically different from the one in the previous two figures. Furthermore, we could multiply out and add out the
W X Y W + X
Z
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X ((W X) Y ) F W = ((W + X) Y ) (W + X + Y) (W + Z) (W + X + Y) Y (W + Z)
Figure 4-14 Algebraic analysis of a logic circuit with NAND a nd NOR gates.
F = [((W X) Y) + (W + X + Y) + (W + Z)]
= ((W + X) + Y) (W X Y) (W Z) = ((W + X) Y) (W + X + Y) (W + Z)
= ((W X) Y) (W + X + Y) (W + Z)
X
(W X) Y
W
W + X + Y
Figure 4-15 Algebraic analysis of the previous circuit after substituting some NAND and NOR symbols.
F
Y
W+Z
= ((W + X) Y ) (W + X + Y) (W + Z)
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W X Y
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W + X
Z
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X (W + X) Y W W + X + Y F Y = ((W + X) Y ) (W + X + Y) (W + Z) W+Z
Figure 4-16 A different circuit for same logic function.
expression to obtain sum-of-products and product-of-sums expressions corresponding to two more physically different circuits for the same logic function. Although we used logic expressions above to convey information about the physical structure of a circuit, we dont always do this. For example, we might use the expression G(W, X, Y, Z) = W X Y + Y Z to describe any one of the circuits in Figure 4-17. Normally, the only sure way to determine a circuits structure is to look at its schematic drawing. However, for certain restricted classes of circuits, structural information can be inferred from logic expressions. For example, the circuit in (a) could be described without reference to the drawing as a two-level AND-OR circuit for W X Y + Y Z, while the circuit in (b) could be described as a two-level NAND-NAND circuit for W X Y + Y Z.
Figure 4-17 Three circuits for G(W, X, Y, Z) = W X Y + Y Z : (a) two-level AND-OR; (b) two-level NAND-NAND; (c) ad hoc.
WXY (b) W X ( W X Y )
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4.3 Combinational Circuit Synthesis
4.3.1 Circuit Descriptions and Designs What is the starting point for designing combinational logic circuits? Usually, we are given a word description of a problem or we develop one ourselves. Occasionally, the description is a list of input combinations for which a signal should be on or off, the verbal equivalent of a truth table or the or notation introduced previously. For example, the description of a 4-bit prime-number detector might be, Given a 4-bit input combination N = N3N2N1N 0, this function produces a 1 output for N = 1, 2, 3, 5, 7, 11, 13, and 0 otherwise. A logic function described in this way can be designed directly from the canonical sum or product expression. For the prime-number detector, we have
F = N ,N ,N ,N (1, 2, 3, 5, 7, 11, 13) 3210 = N3 N2 N1 N0 + N 3 N2 N1 N0 + N3 N2 N1 N0+ N3 N2 N1 N0
The corresponding circuit is shown in Figure 4-18. More often, we describe a logic function using the English-language connectives and, or, and not. For example, we might describe an alarm circuit by saying, The ALARM output is 1 if the PANIC input is 1, or if the ENABLE input is 1, the EXITING input is 0, and the house is not secure; the house is secure
Figure 4-18 Canonical-sum design for 4-bit prime-number detector.
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+ N3 N2 N1 N0 + N3 N2 N1 N0 + N3 N2 N1 N0
N3 N2 N2 N3 N2 N1 N0 N3 N2 N1 N0 N3 N2 N1 N0 N3 N2 N1 N0 F N1 N1 N0 N0
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PANIC ENABLE EXITING WINDOW DOOR GARAGE SECURE
ALARM
Figure 4-19 Alarm circuit derived from logic expression.
if the WINDOW, DOOR, and GARAGE inputs are all 1. Such a description can be translated directly into algebraic expressions:
ALARM = PANIC + ENABLE EXITING SECURE SECURE = WINDOW DOOR GARAGE
ALARM = PANIC + ENABLE EXITING (WINDOW DOOR GARAGE)
Notice that we used the same method in switching algebra as in ordinary algebra to formulate a complicated expressionwe defined an auxiliary variable SECURE to simplify the first equation, developed an expression for SECURE, and used substitution to get the final expression. We can easily draw a circuit using AND , OR , and NOT gates that realizes the final expression, as shown in Figure 4-19. A circuit realizes [makes real] an expression if its output function equals that expression, and the circuit is called a realization of the function. Once we have an expression, any expression, for a logic function, we can do other things besides building a circuit directly from the expression. We can manipulate the expression to get different circuits. For example, the ALARM expression above can be multiplied out to get the sum-of-products circuit in Figure 4-20. Or, if the number of variables is not too large, we can construct the truth table for the expression and use any of the synthesis methods that apply to truth tables, including the canonical sum or product method described earlier and the minimization methods described later.
F igure 4-20 Sum-of-products version of alarm circuit.
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In general, its easier to describe a circuit in words using logical connectives and to write the corresponding logic expressions than it is to write a complete truth table, especially if the number of variables is large. However, sometimes we have to work with imprecise word descriptions of logic functions, for example, The ERROR output should be 1 if the GEARUP, GEARDOWN, and GEARCHECK inputs are inconsistent. In this situation, the truth-table approach is best because it allows us to determine the output required for every input combination, based on our knowledge and understanding of the problem environment (e.g., the brakes cannot be applied unless the gear is down).
4.3.2 Circuit Manipulations The design methods that weve described so far use AND, OR, and NOT gates. We might like to use NAND and NOR gates, tootheyre faster than ANDs and ORs in most technologies. However, most people dont develop logical propositions in terms of NAND and NOR connectives. That is, you probably wouldnt say, I wont date you if youre not clean or not wealthy and also youre not smart or not friendly. It would be more natural for you to say, Ill date you if youre clean and wealthy, or if youre smart and friendly. So, given a natural logic expression, we need ways to translate it into other forms. We can translate any logic expression into an equivalent sum-of-products expression, simply by multiplying it out. As shown in Figure 4-21(a), such an expression may be realized directly with AND and OR gates. The inverters required for complemented inputs are not shown. As shown in Figure 4-21(b), we may insert a pair of inverters between each AND-gate output and the corresponding OR-gate input in a two-level AND-OR
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Figure 4-21 Alternative sum-ofproducts realizations: (a) AND-OR; (b) AND-OR with extra inverter pairs; (c) NAND-NAND.
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Figure 4-22 Another two-level sum-of-products circuit: (a) AND-OR; (b) AND-OR with extra inverter pairs; (c) NAND-NAND.
AND-OR circuit NAND-NAND circuit
Figure 4-23 Realizations of a product-of-sums expression: (a) OR-AND; (b) OR-AND with extra inverter pairs; (c) NOR-NOR.
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circuit. According to theorem T4, these inverters have no effect on the output function of the circuit. In fact, weve drawn the second inverter of each pair with its inversion bubble on its input to provide a graphical reminder that the inverters cancel. However, if these inverters are absorbed into the AND and OR gates, we wind up with AND-NOT gates at the first level and a NOT-OR gate at the second level. These are just two different symbols for the same type of gatea NAND gate. Thus, a two-level AND-OR circuit may be converted to a two-level NAND-NAND circuit simply by substituting gates.
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If any product terms in the sum-of-products expression contain just a single literal, then we may gain or lose inverters in the transformation from ANDOR to NAND-NAND. For example, Figure 4-22 is an example where an inverter on the W input is no longer needed, but an inverter must be added to the Z input. We have shown that any sum-of-products expression can be realized in either of two waysas an AND-OR circuit or as a NAND-NAND circuit. The dual of this statement is also true: any product-of-sums expression can be realized as an OR-AND circuit or as a NOR -NOR circuit. Figure 4-23 shows an example. Any logic expression can be translated into an equivalent product-ofsums expression by adding it out, and hence has both OR-AND and NOR -NOR circuit realizations. The same kind of manipulations can be applied to arbitrary logic circuits. For example, Figure 4-24(a) shows a circuit built from AND and OR gates. After adding pairs of inverters, we obtain the circuit in (b). However, one of the gates, a 2-input AND gate with a single inverted input, is not a standard type. We can use a discrete inverter as shown in (c) to obtain a circuit that uses only standard gate typesNAND, AND, and inverters. Actually, a better way to use the inverter is shown in (d); one level of gate delay is eliminated, and the bottom gate becomes a NOR instead of AND . In most logic technologies, inverting gates like NAND and NOR are faster than noninverting gates like AND and OR.
Figure 4-24 Logic-symbol manipulations: (a) original circuit; (b) transformation with a nonstandard gate; (c) inverter used to eliminate nonstandard gate; (d) preferred inverter placement.
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WHY MINIMIZE?
Minimization is an important step in both ASIC design and in design PLDs. Extra gates and gate inputs require more area in an ASIC chip, and thereby increase cost. The number of gates in a PLD is fixed, so you might think that extra gates are free and they are, until you run out of them and have to upgrade to a bigger, slower, more expensive PLD. Fortunately, most software tools for both ASIC and PLD design have a minimization program built in. The purpose of Sections 4.3.3 through 4.3.8 is to give you a feel for how minimization works.
4.3.3 Combinational Circuit Minimization Its often uneconomical to realize a logic circuit directly from the first logic expression that pops into your head. Canonical sum and product expressions are especially expensive because the number of possible minterms or maxterms (and hence gates) grows exponentially with the number of variables. We minimize a combinational circuit by reducing the number and size of gates that are needed to build it. The traditional combinational circuit minimization methods that well study have as their starting point a truth table or, equivalently, a minterm list or maxterm list. If we are given a logic function that is not expressed in this form, then we must convert it to an appropriate form before using these methods. For example, if we are given an arbitrary logic expression, then we can evaluate it for every input combination to construct the truth table. The minimization methods reduce the cost of a two-level AND-OR, OR -AND, NAND-NAND, or NOR -NOR circuit in three ways: 1. By minimizing the number of first-level gates. 2. By minimizing the number of inputs on each first-level gate. 3. By minimizing the number of inputs on the second-level gate. This is actually a side effect of the first reduction.
However, the minimization methods do not consider the cost of input inverters; they assume that both true and complemented versions of all input variables are available. While this is not always the case in gate-level or ASIC design, its very appropriate for PLD-based design; PLDs have both true and complemented versions of all input variables available for free. Most minimization methods are based on a generalization of the combining theorems, T10 and T10:
given product term Y + given product term Y = given product term given sum term + Y) given sum term + Y) = given sum term
That is, if two product or sum terms differ only in the complementing or not of one variable, we can combine them into a single term with one less variable. So we save one gate and the remaining gate has one fewer input.
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We can apply this algebraic method repeatedly to combine minterms 1, 3, 5, and 7 of the prime-number detector shown in Figure 4-18 on page 213:
F = N ,N ,N ,N (1, 3, 5, 7, 2, 11, 13) 3210 = N3 N2N1N0 + N3 N2 N1 N0 + N3 N2 N1 N0 + N3 N2 N1 N0 +
The resulting circuit is shown in Figure 4-25; it has three fewer gates and one of the remaining gates has two fewer inputs. If we had worked a little harder on the preceding expression, we could have saved a couple more first-level gate inputs, though not any gates. Its difficult to find terms that can be combined in a jumble of algebraic symbols. In the next subsection, well begin to explore a minimization method that is more fit for human consumption. Our starting point will be the graphical equivalent of a truth table.
4.3.4 Karnaugh Maps A Karnaugh map is a graphical representation of a logic functions truth table. Figure 4-26 shows Karnaugh maps for logic functions of 2, 3, and 4 variables. The map for an n-input logic function is an array with 2n cells, one for each possible input combination or minterm. The rows and columns of a Karnaugh map are labeled so that the input combination for any cell is easily determined from the row and column headings for that cell. The small number inside each cell is the corresponding minterm number in the truth table, assuming that the truth table inputs are labeled alphabetically from left to right (e.g., X, Y, Z) and the rows are numbered in binary
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N3 N0 N3 N2 N1 N0 N3 N2 N1 N0 F N3 N2 N1 N0
Figure 4-25 Simplified sum-ofproducts realization for 4-bit primenumber detector.
= (N3 N2 N1 N0 + N3 N2 N1 N0) + ( N 3 N2 N1 N0 + N 3 N2 N1 N0) + = N3N2 N0 + N3 N2 N0 + = N3 N0 +
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Figure 4-26 Karnaugh maps: (a) 2-variable; (b) 3-variable; (c) 4-variable.
counting order, like all the examples in this text. For example, cell 13 in the 4variable map corresponds to the truth-table row in which W X Y Z = 1101. When we draw the Karnaugh map for a given function, each cell of the map contains the information from the like-numbered row of the functions truth tablea 0 if the function is 0 for that input combination, a 1 otherwise. In this text, we use two redundant labelings for map rows and columns. For example, consider the 4-variable map in Figure 4-26(c). The columns are labeled with the four possible combinations of W and X, W X = 00, 01, 11, and 10. Similarly, the rows are labeled with the Y Z combinations. These labels give us all the information we need. However, we also use brackets to associate four regions of the map with the four variables. Each bracketed region is the part of the map in which the indicated variable is 1. Obviously, the brackets convey the same information that is given by the row and column labels. When we draw a map by hand, it is much easier to draw the brackets than to write out all of the labels. However, we retain the labels in the texts Karnaugh maps as an additional aid to understanding. In any case, you must be sure to label the rows and columns in the proper order to preserve the correspondence between map cells and truth table row numbers shown in Figure 4-26. To represent a logic function on a Karnaugh map, we simply copy 1s and 0s from the truth table or equivalent to the corresponding cells of the map. Figures 4-27(a) and (b) show the truth table and Karnaugh map for a logic function that we analyzed (beat to death?) in Section 4.2. From now on, well reduce the clutter in maps by copying only the 1s or the 0s, not both. 4.3.5 Minimizing Sums of Products By now you must be wondering about the strange ordering of the row and column numbers in a Karnaugh map. There is a very important reason for this orderingeach cell corresponds to an input combination that differs from each of its immediately adjacent neighbors in only one variable. For example, cells 5 and 13 in the 4-variable map differ only in the value of W. In the 3- and
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Figure 4-27 F = X,Y,Z(1,2,5,7): (a) truth table; (b) Karnaugh map; (c) combining adjacent 1-cells.
4-variable maps, corresponding cells on the left/right or top/bottom borders are less obvious neighbors; for example, cells 12 and 14 in the 4-variable map are adjacent because they differ only in the value of Y. Each input combination with a 1 in the truth table corresponds to a minterm in the logic functions canonical sum. Since pairs of adjacent 1 cells in the Karnaugh map have minterms that differ in only one variable, the minterm pairs can be combined into a single product term using the generalization of theorem T10, term Y + term Y = term. Thus, we can use a Karnaugh map to simplify the canonical sum of a logic function. For example, consider cells 5 and 7 in Figure 4-27(b), and their contribution to the canonical sum for this function:
F = + X Y Z + X Y Z
Remembering wraparound, we see that cells 1 and 5 in Figure 4-27(b) are also adjacent and can be combined:
F = X Y Z + X Y Z +
In general, we can simplify a logic function by combining pairs of adjacent 1-cells (minterms) whenever possible, and writing a sum of product terms that cover all of the 1-cells. Figure 4-27(c) shows the result for our example logic function. We circle a pair of 1s to indicate that the corresponding minterms are combined into a single product term. The corresponding AND-OR circuit is shown in Figure 4-28. In many logic functions, the cell-combining procedure can be extended to combine more than two 1-cells into a single product term. For example, consider
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Figure 4-28 Minimized AND-OR circuit.
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the canonical sum for the logic function F = X,Y,Z(0, 1, 4, 5, 6). We can use the algebraic manipulations of the previous examples iteratively to combine four of the five minterms:
F = X Y Z + X Y Z + X Y Z + X Y Z + X Y Z
= [(X Y) Z + (X Y) Z] + [(X Y) Z + (X Y) Z] + X Y Z
= X Y + X Y + X Y Z = Y + X Y Z
= [X (Y) + X (Y)] + X Y Z
In general, 2i 1-cells may be combined to form a product term containing n i literals, where n is the number of variables in the function. A precise mathematical rule determines how 1-cells may be combined and the form of the corresponding product term: A set of 2i 1-cells may be combined if there are i variables of the logic function that take on all 2i possible combinations within that set, while the remaining n i variables have the same value throughout that set. The corresponding product term has n i literals, where a variable is complemented if it appears as 0 in all of the 1-cells, and uncomplemented if it appears as 1.
Graphically, this rule means that we can circle rectangular sets of 2n 1s, literally as well as figuratively stretching the definition of rectangular to account for wraparound at the edges of the map. We can determine the literals of the corresponding product terms directly from the map; for each variable we make the following determination: If a circle covers only areas of the map where the variable is 0, then the variable is complemented in the product term. If a circle covers only areas of the map where the variable is 1, then the variable is uncomplemented in the product term. If a circle covers both areas of the map where the variable is 0 and areas where it is 1, then the variable does not appear in the product term.
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A sum-of-products expression for a function must contain product terms (circled sets of 1-cells) that cover all of the 1s and none of the 0s on the map. The Karnaugh map for our most recent example, F = X,Y,Z(0, 1, 4, 5, 6), is shown in Figure 4-29(a) and (b). We have circled one set of four 1s, corresponding to the product term Y, and a set of two 1s corresponding to the product term X Z. Notice that the second product term has one less literal than the corresponding product term in our algebraic solution (X Y Z). By circling the largest possible set of 1s containing cell 6, we have found a less expensive realization of the logic function, since a 2-input AND gate should cost less than a 3-input one. The fact that two different product terms now cover the same 1-cell (4) does not affect the logic function, since for logical addition 1 + 1 = 1, not 2! The corresponding two-level AND/OR circuit is shown in (c). As another example, the prime-number detector circuit that we introduced in Figure 4-18 on page 213 can be minimized as shown in Figure 4-30. At this point, we need some more definitions to clarify what were doing: A minimal sum of a logic function F(X1,,Xn) is a sum-of-products expression for F such that no sum-of-products expression for F has fewer product terms, and any sum-of-products expression with the same number of product terms has at least as many literals. That is, the minimal sum has the fewest possible product terms (first-level gates and second-level gate inputs) and, within that constraint, the fewest possible literals (first-level gate inputs). Thus, among our three prime-number detector circuits, only the one in Figure 4-30 on the next page realizes a minimal sum. The next definition says precisely what the word imply means when we talk about logic functions:
A logic function P(X1,,Xn) implies a logic function F(X1,,Xn) if for every input combination such that P = 1, then F = 1 also.
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Figure 4-30 Prime-number detector: (a) initial Karnaugh map; (b) circled product terms; (c) minimized circuit.
That is, if P implies F, then F is 1 for every input combination that P is 1, and maybe some more. We may write the shorthand P F. We may also say that F includes P, or that F covers P. A prime implicant of a logic function F(X1,,Xn) is a normal product term P(X1,,Xn) that implies F, such that if any variable is removed from P, then the resulting product term does not imply F.
In terms of a Karnaugh map, a prime implicant of F is a circled set of 1-cells satisfying our combining rule, such that if we try to make it larger (covering twice as many cells), it covers one or more 0s. Now comes the most important part, a theorem that limits how much work we must do to find a minimal sum for a logic function: Prime Implicant Theorem A minimal sum is a sum of prime implicants.
That is, to find a minimal sum, we need not consider any product terms that are not prime implicants. This theorem is easily proved by contradiction. Suppose
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Figure 4-31 F = W,X,Y,Z(5,7,12,13,14,15): (a) Karnaugh map; (b) prime implicants.
that a product term P in a minimal sum is not a prime implicant. Then according to the definition of prime implicant, if P is not one, it is possible to remove some literal from P to obtain a new product term P* that still implies F. If we replace P w ith P* in the presumed minimal sum, the resulting sum still equals F but has one fewer literal. Therefore, the presumed minimal sum was not minimal after all. Another minimization example, this time a 4-variable function, is shown in Figure 4-31. There are just two prime implicants, and its quite obvious that both of them must be included in the minimal sum in order to cover all of the 1-cells on the map. We didnt draw the logic diagram for this example because you should know how to do that yourself by now. The sum of all the prime implicants of a logic function is called the complete sum. Although the complete sum is always a legitimate way to realize a logic function, its not always minimal. For example, consider the logic function shown in Figure 4-32. It has five prime implicants, but the minimal sum includes
Figure 4-32 F = W,X,Y,Z(1,3,4,5,9,11,12,13,14,15): (a) Karnaugh map; (b) prime implicants and distinguished 1-cells.
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Figure 4-33 F =W,X,Y,Z(2,3,4,5,6,7,11,13,15): (a) Karnaugh map; (b) prime implicants and distinguished 1-cells.
only three of them. So, how can we systematically determine which prime implicants to include and which to leave out? Two more definitions are needed: A distinguished 1-cell of a logic function is an input combination that is covered by only one prime implicant. An essential prime implicant of a logic function is a prime implicant that covers one or more distinguished 1-cells.
Since an essential prime implicant is the only prime implicant that covers some 1-cell, it must be included in every minimal sum for the logic function. So, the first step in the prime implicant selection process is simplewe identify distinguished 1-cells and the corresponding prime implicants, and include the essential prime implicants in the minimal sum. Then we need only determine how to cover the 1-cells, if any, that are not covered by the essential prime implicants. In the example of Figure 4-32, the three distinguished 1-cells are shaded, and the corresponding essential prime implicants are circled with heavier lines. All of the 1-cells in this example are covered by essential prime implicants, so we need go no further. Likewise, Figure 4-33 shows an example where all of the prime implicants are essential, and so all are included in the minimal sum. A logic function in which not all the 1-cells are covered by essential prime implicants is shown in Figure 4-34. By removing the essential prime implicants and the 1-cells they cover, we obtain a reduced map with only a single 1-cell and two prime implicants that cover it. The choice in this case is simplewe use the W Z product term because it has fewer inputs and therefore lower cost. For more complex cases, we need yet another definition: Given two prime implicants P and Q in a reduced map, P is said to eclipse Q (written P Q) if P covers at least all the 1-cells covered by Q.
If P costs no more than Q and eclipses Q, then removing Q from consideration cannot prevent us from finding a minimal sum; that is, P is at least as good as Q.
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Figure 4-34 F = W,X,Y,Z(0,1,2,3,4,5,7,14,15): (a) Karnaugh map; (b) prime implicants and distinguished 1-cells; (c) reduced map after removal of essential prime implicants and covered 1-cells.
An example of eclipsing is shown in Figure 4-35. After removing essential prime implicants, we are left with two 1-cells, each of which is covered by two prime implicants. However, X Y Z eclipses the other two prime implicants, which therefore may be removed from consideration. The two 1-cells are then covered only by X Y Z, which is a secondary essential prime implicant that must be included in the minimal sum. Figure 4-36 shows a more difficult casea logic function with no essential prime implicants. By trial and error we can find two different minimal sums for this function. We can also approach the problem systematically using the branching method. Starting with any 1-cell, we arbitrarily select one of the prime implicants that covers it, and include it as if it were essential. This simplifies the
Figure 4-35 F = W,X,Y,Z(2,6,7,9,13,15): (a) Karnaugh map; (b) prime implicants and distinguished 1-cells; (c) reduced map after removal of essential prime implicants and covered 1-cells.
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Figure 4-36 F = W,X,Y,Z(1,5,7,9,11,15): (a) Karnaugh map; (b) prime implicants; (c) a minimal sum; (d) another minimal sum.
remaining problem, which we can complete in the usual way to find a tentative minimal sum. We repeat this process starting with all other prime implicants that cover the starting 1-cell, generating a different tentative minimal sum from each starting point. We may get stuck along the way and have to apply the branching method recursively. Finally, we examine all of the tentative minimal sums generated in this way and select one that is truly minimal. 4.3.6 Simplifying Products of Sums Using the principle of duality, we can minimize product-of-sums expressions by looking at the 0s on a Karnaugh map. Each 0 on the map corresponds to a maxterm in the canonical product of the logic function. The entire process in the preceding subsection can be reformulated in a dual way, including the rules for writing sum terms corresponding to circled sets of 0s, in order to find a minimal product. Fortunately, once we know how to find minimal sums, theres an easier way to find the minimal product for a given logic function F. The first step is to complement F to obtain F. Assuming that F is expressed as a minterm list or a
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truth table, complementing is very easy; the 1s of F are just the 0s of F. Next, we find a minimal sum for F using the method of the preceding subsection. Finally, we complement the result using the generalized DeMorgans theorem, which yields a minimal product for (F) = F. (Note that if you simply add out the minimal-sum expression for the original function, the resulting product-of-sums expression is not necessarily minimal; for example, see Exercise 4.56.) In general, to find the lowest-cost two-level realization of a logic function, we have to find both a minimal sum and a minimal product, and compare them. If a minimal sum for a logic function has many terms, then a minimal product for the same function may have few terms. As a trivial example of this tradeoff, consider a 4-input OR function:
F = (W) + (X) + (Y) + (Z) (a sum of four trivial product terms)
For a nontrivial example, youre invited to find the minimal product for the function that we minimized in Figure 4-33 on page 226; it has just two sum terms. The opposite situation is also sometimes true, as trivially illustrated by a 4-input AND:
F = (W) (X) (Y) (Z) (a product of four trivial sum terms)
A nontrivial example with a higher-cost product-of-sums is the function in Figure 4-29 on page 223. For some logic functions, both minimal forms are equally costly. For example, consider a 3-input exclusive OR function; both minimal expressions have four terms, and each term has three literals:
F = X,Y,Z(1,2,4,7)
Still, in most cases, one form or the other will give better results. Looking at both forms is especially useful in PLD-based designs.
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= (W + X + Y + Z) (a product of one sum term) = (W X Y Z) (a sum of one product term)
= (X Y Z) + (X Y Z) + (X Y Z) + (X Y Z) = (X + Y + Z) (X + Y + Z) (X + Y + Z) (X +Y + Z)
PLD MINIMIZATION
Typical PLDs have an AND-OR array corresponding to a sum-of-products form, so you might think that only the minimal sum-of-products is relevant to a PLD-based design. However, most PLDs also have a programmable inverter/buffer at the output of the AND-OR array, which can either invert or not. Thus, the PLD can utilize the equivalent of the minimal sum by using the AND-OR array to realize the complement of the desired function, and then programming the inverter/buffer to invert. Most logic minimization programs for PLDs automatically find both the minimal sum and the minimal product, and select the one that requires fewer terms.
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Figure 4-37 Prime BCD-digit detector: (a) initial Karnaugh map; (b) Karnaugh map with prime implicants and distinguished 1-cells.
*4.3.7 Dont-Care Input Combinations Sometimes the specification of a combinational circuit is such that its output doesnt matter for certain input combinations, called dont-cares. This may be true because the outputs really dont matter when these input combinations occur, or because these input combinations never occur in normal operation. For example, suppose we wanted to build a prime-number detector whose 4-bit input N = N3N 2N1N0 is always a BCD digit; then minterms 1015 should never occur. A prime BCD-digit detector function may therefore be written as follows:
F = N ,N ,N ,N (1,2,3,5,7) + d(10,11,12,13,14,15) 3210
The d() list specifies the dont-care input combinations for the function, also known as the d-set. Here F must be 1 for input combinations in the on-set (1,2,3,5,7), F can have any values for inputs in the d-set (10,11,12,13,14,15), and F must be 0 for all other input combinations (in the 0-set). Figure 4-37 shows how to find a minimal sum-of-products realization for the prime BCD-digit detector, including dont-cares. The ds in the map denote the dont-care input combinations. We modify the procedure for circling sets of 1s (prime implicants) as follows: Allow ds to be included when circling sets of 1s, to make the sets as large as possible. This reduces the number of variables in the corresponding prime implicants. Two such prime implicants (N2 N0 and N2 N1) appear in the example. Do not circle any sets that contain only ds. Including the corresponding product term in the function would unnecessarily increase its cost. Two such product terms (N3 N2 and N3 N1) are circled in the example. Just a reminder: As usual, do not circle any 0s.
* Throughout this book, optional sections are marked with an asterisk.
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The remainder of the procedure is the same. In particular, we look for distinguished 1-cells and not distinguished d-cells, and we include only the corresponding essential prime implicants and any others that are needed to cover all the 1s on the map. In Figure 4-37, the two essential prime implicants are sufficient to cover all of the 1s on the map. Two of the ds also happen to be covered, so F will be 1 for dont-care input combinations 10 and 11, and 0 for the other dont-cares. Some HDLs, including ABEL, provide a means for the designer to specify dont-care inputs, and the logic minimization program takes these into account when computing a minimal sum. *4.3.8 Multiple-Output Minimization Most practical combinational logic circuits require more than one output. We can always handle a circuit with n outputs as n independent single-output design problems. However, in doing so, we may miss some opportunities for optimization. For example, consider the following two logic functions:
F = X,Y,Z (3,6,7) G = X,Y,Z (0,1,3)
Figure 4-38 shows the design of F and G as two independent single-output functions. However, as shown in Figure 4-39, we can also find a pair of sum-ofproducts expressions that share a product term, such that the resulting circuit has one fewer gate than our original design.
Figure 4-38 Treating a 2-output design as two independent single-output designs: (a) Karnaugh maps; (b) minimal circuit.
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Z 00 01 11 1 10 XY 0 1 XY X Y Z 1 1 Z YZ Y YZ F = XY + YZ X XY Y Z 00 1 01 11 10 X Y 0 1 X 1 1 Z X Z Y X G = X Y + X Z
F =XY+YZ
G = X Y + X Z
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XY X Z 00 01 11 1 10 XY 0 1 1 1 Z (b) X Y Z XY Y F = X Y + X Y Z X XY X Y Z Z 00 1 01 11 10 0 1 X 1 1 Z Y X Y Y X Y Z G = X Y + X Y Z
F = X Y + X Y Z
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Figure 4-39 Multiple-output minimization for a 2-output circuit: (a) minimized maps including a shared term; (b) minimal multiple-output circuit
When we design multiple-output combinational circuits using discrete gates, as in an ASIC, product-term sharing obviously reduces circuit size and cost. In addition, PLDs contain multiple copies the sum-of-products structure that weve been learning how to minimize, one per output, and some PLDs allow product terms to be shared among multiple outputs. Thus, the ideas introduced in this subsection are used in many logic minimization programs. You probably could have eyeballed the Karnaugh maps for F and G in Figure 4-39, and discovered the minimal solution. However, larger circuits can be minimized only with a formal multiple-output minimization algorithm. Well outline the ideas in such an algorithm here; details can be found in the References. The key to successful multiple-output minimization of a set of n functions is to consider not only the n original single-output functions, but also product functions. An m-product function of a set of n functions is the product of m of the functions, where 2 m n. There are 2 n n 1 such functions. Fortunately, n = 2 in our example and there is only one product function, F G, to consider. The Karnaugh maps for F, G, and F G are shown in Figure 4-40; in general, the map for an m-product function is obtained by ANDing the maps of its m components. A multiple-output prime implicant of a set of n functions is a prime implicant of one of the n functions or of one of the product functions. The first step in multiple-output minimization is to find all of the multiple-output
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(a)
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Figure 4-40 Karnaugh maps for a set of two functions: (a) maps for F and G; (b) 2-product map for F G; (c) reduced maps for F and G after removal of essential prime implicants and covered 1-cells.
prime implicants. Each prime implicant of an m -product function is a possible term to include in the corresponding m outputs of the circuit. If we were trying to minimize a set of 8 functions, we would have to find the prime implicants for 28 8 1 = 247 product functions as well as for the 8 given functions. Obviously, multiple-output minimization is not for the faint-hearted! Once we have found the multiple-output prime implicants, we try to simplify the problem by identifying the essential ones. A distinguished 1-cell of a particular single-output function F is a 1-cell that is covered by exactly one prime implicant of F or of the product functions involving F. The distinguished 1-cells in Figure 4-39 are shaded. An essential prime implicant of a particular single-output function is one that contains a distinguished 1-cell. As in singleoutput minimization, the essential prime implicants must be included in a minimum-cost solution. Only the 1-cells that are not covered by essential prime implicants are considered in the remainder of the algorithm. The final step is to select a minimal set of prime implicants to cover the remaining 1-cells. In this step we must consider all n functions simultaneously, including the possibility of sharing; details of this procedure are discussed in the References. In the example of Figure 4-40(c), we see that there exists a single, shared product term that covers the remaining 1-cell in both F and G.
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XY X (c) XY X Z 00 01 11 1 10 XY Z 00 01 11 10 0 1 0 1 1 1 Z 1 YZ (b) XY X Y Z 00 01 11 10 X Y Z Y F=XY+... X 0 1 F = X Y + X Y Z X 1 XY Z XY Z 00 1 01 11 10 X Y Z Y Z 00 01 11 10 0 1 FG 0 1 1 1 Z 1 Y G = X Y + . . . X Z X Y Z Y G = X Y + X Y Z
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1 Uncomplemented. 0 Complemented. x Doesnt appear.
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Obviously, logic minimization can be a very involved process. In real logicdesign applications, you are likely to encounter only two kinds of minimization problems: functions of a few variables that you can eyeball using the methods of the previous section, and more complex, multiple-output functions that are hopeless without the use of a minimization program. We know that minimization can be performed visually for functions of a few variables using the Karnaugh-map method. Well show in this section that the same operations can be performed for functions of an arbitrarily large number of variables (at least in principle) using a tabular method called the QuineMcCluskey algorithm. Like all algorithms, the Quine-McCluskey algorithm can be translated into a computer program. And like the map method, the algorithm has two steps: (a) finding all prime implicants of the function, and (b) selecting a minimal set of prime implicants that covers the function. The Quine-McCluskey algorithm is often described in terms of handwritten tables and manual check-off procedures. However, since no one ever uses these procedures manually, its more appropriate for us to discuss the algorithm in terms of data structures and functions in a high-level programming language. The goal of this section is to give you an appreciation for computational complexity involved in a large minimization problem. We consider only fully specified, single-output functions; dont-cares and multiple-output functions can be handled by fairly straightforward modifications to the single-output algorithms, as discussed in the References. *4.4.1 Representation of Product Terms The starting point for the Quine-McCluskey minimization algorithm is the truth table or, equivalently, the minterm list of a function. If the function is specified differently, it must first be converted into this form. For example, an arbitrary n-variable logic expression can be multiplied out (perhaps using DeMorgans theorem along the way) to obtain a sum-of-products expression. Once we have a sum-of-products expression, each p-variable product term produces 2np minterms in the minterm list. We showed in Section 4.1.6 that a minterm of an n-variable logic function can be represented by an n-bit integer (the minterm number), where each bit indicates whether the corresponding variable is complemented or uncomplemented. However, a minimization algorithm must also deal with product terms that are not minterms, where some variables do not appear at all. Thus, we must represent three possibilities for each variable in a general product term:
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These possibilities are represented by a string of n of the above digits in the cube representation of a product term. For example, if we are working with product terms of up to eight variables, X7, X6, , X1, X0, we can write the following product terms and their cube representations:
X7 X6 X5 X4 X3 X2 X1 X0 01101110 X3 X2 X1 X0 xxxx1110 X6 x1xxxxxx X7 X5 X4 X3 X2 X1 1x01101x
Notice that for convenience, we named the variables just like the bit positions in n-bit binary integers. In terms of the n-cube and m-subcube nomenclature of Section 2.14, the string 1x01101x represents a 2-subcube of an 8-cube, and the string 01101110 represents a 0-subcube of an 8-cube. However, in the minimization literature, the maximum dimension n of a cube or subcube is usually implicit, and an m -subcube is simply called an m -cube or a cube for short; well follow this practice in this section. To represent a product term in a computer program, we can use a data structure with n elements, each of which has three possible values. In C, we might make the following declarations:
typedef enum {complemented, uncomplemented, doesntappear} TRIT; typedef TRIT[16] CUBE; /* Represents a single product term with up to 16 variables */
However, these declarations do not lead to a particularly efficient internal representation of cubes. As well see, cubes are easier to manipulate using conventional computer instructions if an n-variable product term is represented by two n-bit computer words, as suggested by the following declarations:
#define MAX_VARS 16 /* Max # of variables in a product term */ typedef unsigned short WORD; /* Use 16-bit words */ struct cube { WORD t; /* Bits 1 for uncomplemented variables. */ WORD f; /* Bits 1 for complemented variables. */ }; typedef struct cube CUBE; CUBE P1, P2, P3; /* Allocate three cubes for use by program. */
Here, a WORD is a 16-bit integer, and a 16-variable product term is represented by a record with two WORDs, as shown in Figure 4-41(a). The first word in a CUBE has a 1 for each variable in the product term that appears uncomplemented (or true, t), and the second has a 1 for each variable that appears complemented (or false, f). If a particular bit position has 0s in both WORDs, then the corresponding variable does not appear, while the case of a particular bit position
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Figure 4-41 Internal representation of 16-variable product terms in a Pascal program: (a) general format; (b) P1 = X15 X12 X10 X9 X4 X1 X0
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CUBE: .t .f 1 0 X8 0 1 X8 0 0 X8 doesn't appear (b)
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having 1s in both WORDs is not used. Thus, the program variable P1 in (b) represents the product term P1 = X15 X12 X10 X9 X4 X1 X0. If we wished to represent a logic function F of up to 16 variables, containing up to 100 product terms, we could declare an array of 100 CUBEs:
CUBE F[100]; /* Storage for a logic function with up to 100 product terms. */
Using the foregoing cube representation, it is possible to write short, efficient C functions that manipulate product terms in useful ways. Table 4-8 shows several such functions. Corresponding to two of the functions, Figure 4-42 depicts how two cubes can be compared and combined if possible
Figure 4-42 Cube manipulations: (a) determining whether two cubes are combinable using theorem T10, term X + term X = term; (b) combining cubes using theorem T10.
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AND bit-by-bit Logical AND operation
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int EqualCubes(CUBE C1, CUBE C2) /* Returns true if C1 and C2 are identical. { return ( (C1.t == C2.t) && (C1.f == C2.f) ); } int Oneone(WORD w) { int ones, b; ones = 0; for (b=0; b<MAX_VARS; b++) if (w & 1) ones++; w = w>>1; } return((ones==1)); } /* Returns true if w has exactly one 1 bit. /* Optimizing the speed of this routine is critical /* and is left as an exercise for the hacker. {
int Combinable(CUBE C1, CUBE C2) { /* Returns true if C1 and C2 differ in only one variable, */ WORD twordt, twordf; /* which appears true in one and false in the other. */ twordt = C1.t ^ C2.t; twordf = C1.f ^ C2.f; return( (twordt==twordf) && Oneone(twordt) ); }
void Combine(CUBE C1, CUBE C2, CUBE *C3) /* Combines C1 and C2 using theorem T10, and stores the { /* result in C3. Assumes Combinable(C1,C2) is true. C3->t = C1.t & C2.t; C3->f = C1.f & C2.f; }
using theorem T10, term X + term X = term. This theorem says that two product terms can be combined if they differ in only one variable that appears complemented in one term and uncomplemented in the other. Combining two mcubes yields an (m + 1)-cube. Using cube representation, we can apply the combining theorem to a few examples:
010 + 000 = 0x0 00111001 + 00111000 = 0011100x
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Ta b l e 4 - 8 Cube comparing and combining functions used in minimization program.
*/ */ */ */ */ */
101xx0x0 + 101xx1x0 = 101xxxx0
x111xx00110x000x + x111xx00010x000x = x111xx00x10x000x
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*4.4.2 Finding Prime Implicants by Combining Product Terms The first step in the Quine-McCluskey algorithm is to determine all of the prime implicants of the logic function. With a Karnaugh map, we do this visually by identifying largest possible rectangular sets of 1s. In the algorithm, this is done by systematic, repeated application of theorem T10 to combine minterms, then 1-cubes, 2-cubes, and so on, creating the largest possible cubes (smallest possible product terms) that cover only 1s of the function. The C program in Table 4-9 applies the algorithm to functions with up to 16 variables. It uses 2-dimensional arrays, cubes[m][j] and covered[m][j], to keep track of MAX_VARS m-cubes. The 0-cubes (minterms) are supplied by the user. Starting with the 0-cubes, the program examines every pair of cubes at each level and combines them when possible into cubes at the next level. Cubes that are combined into a next-level cube are marked as covered; cubes that are not covered are prime implicants. Even though the program in Table 4-9 is short, an experienced programmer could become very pessimistic just looking at its structure. The inner for loop is nested four levels deep, and the number of times it might be executed is on the order of MAX_VARS MAX_CUBES3. Thats right, thats an exponent, not a footnote! We picked the value maxCubes = 1000 somewhat arbitrarily (in fact, too optimistically for many functions), but if you believe this number, then the inner loop can be executed billions and billions of times. The maximum number of minterms of an n-variable function is 2n, of course, and so by all rights the program in Table 4-9 should declare maxCubes to be 216, at least to handle the maximum possible number of 0-cubes. Such a declaration would not be overly pessimistic. If an n-variable function has a product term equal to a single variable, then 2n1 minterms are in fact needed to cover that product term. For larger cubes, the situation is actually worse. The number of possible mn n subcubes of an n-cube is m 2 n m , where the binomial coefficient m is
the number of ways to choose m variables to be xs, and 2nm is the number of ways to assign 0s and 1s to the remaining variables. For 16-variable functions, the worst case occurs with m = 5; there are 8,945,664 possible 5-subcubes of a 16-cube. The total number of distinct m-subcubes of an n-cube, over all values of m , is 3n. So a general minimization program might require a lot more memory than weve allocated in Table 4-9. There are a few things that we can do to optimize the storage space and execution time required in Table 4-9 (see Exercises 4.724.75), but they are piddling compared to the overwhelming combinatorial complexity of the problem. Thus, even with todays fast computers and huge memories, direct application of the Quine-McCluskey algorithm for generating prime implicants is generally limited to functions with only a few variables (fewer than 1520).
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#define TRUE 1 #define FALSE 0 #define MAX_CUBES 50
void main() { CUBE cubes[MAX_VARS+1][MAX_CUBES]; int covered[MAX_VARS+1][MAX_CUBES]; int numCubes[MAX_VARS+1]; int m; /* Value of m in an m-cube, i.e., level m. */ int j, k, p; /* Indices into the cubes or covered array. */ CUBE tempCube; int found; /* Initialize number of m-cubes at each level m. */ for (m=0; m<MAX_VARS+1; m++) numCubes[m] = 0;
/* Read a list of minterms (0-cubes) supplied by the user, storing them /* in the cubes[0,j] subarray, setting covered[0,j] to false for each /* minterm, and setting numCubes[0] to the total number of minterms read. ReadMinterms;
for (m=0; m<MAX_VARS; m++) /* Do for all levels except the last */ for (j=0; j<numCubes[m]; j++) /* Do for all cubes at this level */ for (k=j+1; k<numCubes[m]; k++) /* Do for other cubes at this level */ if (Combinable(cubes[m][j], cubes[m][k])) { /* Mark the cubes as covered. */ covered[m][j] = TRUE; covered[m][k] = TRUE; /* Combine into an (m+1)-cube, store in tempCube. */ Combine(cubes[m][j], cubes[m][k], &tempCube); found = FALSE; /* See if weve generated this one before. */ for (p=0; p<numCubes[m+1]; p++) if (EqualCubes(cubes[m+1][p],tempCube)) found = TRUE; if (!found) { /* Add the new cube to the next level. */ numCubes[m+1] = numCubes[m+1] + 1; cubes[m+1][numCubes[m+1]-1] = tempCube; covered[m+1][numCubes[m+1]-1] = FALSE; } } for (m=0; m<MAX_VARS; m++) /* Do for all levels */ for (j=0; j<numCubes[m]; j++) /* Do for all cubes at this level */ /* Print uncovered cubes -- these are the prime implicants. */ if (!covered[m][j]) PrintCube(cubes[m][j]); }
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Ta b l e 4 - 9 A C program that finds prime implicants using the Quine-McCluskey algorithm.
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(a) 2 6 13 15 (b) 2 6 7 9 13 prime implicants A B C D E A B C D E (c) 7 15 (d) 7 15 (e) 7 B C D B C D C
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Figure 4-43 Prime-implicant tables: (a) original table; (b) showing distinguished 1-cells and essential prime implicants; (c) after removal of essential prime implicants; (d) showing eclipsed rows; (e) after removal of eclipsed rows, showing secondary essential prime implicant.
*4.4.3 Finding a Minimal Cover Using a Prime-Implicant Table The second step in minimizing a combinational logic function, once we have a list of all its prime implicants, is to select a minimal subset of them to cover all the 1s of the function. The Quine-McCluskey algorithm uses a two-dimensional array called a prime-implicant table to do this. Figure 4-43(a) shows a small but representative prime-implicant table, corresponding to the Karnaugh-map minimization problem of Figure 4-35. There is one column for each minterm of the function, and one row for each prime implicant. Each entry is a bit that is 1 if and only if the prime implicant for that row covers the minterm for that column (shown in the figure as a check). The steps for selecting prime implicants with the table are analogous to the steps that we used in Section 4.3.5 with Karnaugh maps: 1. Identify distinguished 1-cells. These are easily identified in the table as columns with a single 1, as shown in Figure 4-43(b). 2. Include all essential prime implicants in the minimal sum. A row that contains a check in one or more distinguished-1-cell columns corresponds to an essential prime implicant. 3. Remove from consideration the essential prime implicants and the 1-cells (minterms) that they cover. In the table, this is done by deleting the corresponding rows and columns, marked in color in Figure 4-43(b). If any rows
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have no checks remaining, they are also deleted; the corresponding prime implicants are redundant, that is, completely covered by essential prime implicants. This step leaves the reduced table shown in (c). 4. Remove from consideration any prime implicants that are eclipsed by others with equal or lesser cost. In the table, this is done by deleting any rows whose checked columns are a proper subset of another rows, and deleting all but one of a set of rows with identical checked columns. This is shown in color in (d), and leads to the further reduced table in (e). When a function is realized in a PLD, all of its prime implicants may be considered to have equal cost, because all of the AND gates in a PLD have all of the inputs available. Otherwise, the prime implicants must be sorted and selected according to the number of AND-gate inputs. 5. Identify distinguished 1-cells and include all secondary essential prime implicants in the minimal sum. As before, any row that contains a check in one or more distinguished-1-cell columns corresponds to a secondary essential prime implicant. 6. If all remaining columns are covered by the secondary essential prime implicants, as in (e), were done. Otherwise, if any secondary essential prime implicants were found in the previous step, we go back to step 3 and iterate. Otherwise, the branching method must be used, as described in Section 4.3.5. This involves picking rows one at a time, treating them as if they were essential, and recursing (and cursing) on steps 36. Although a prime-implicant table allows a fairly straightforward primeimplicant selection algorithm, the data structure required in a corresponding computer program is huge, since it requires on the order of p 2n bits, where p is the number of prime implicants and n is the number of input bits (assuming that the given function produces a 1 output for most input combinations). Worse, executing the steps that we so blithely described in a few sentences above requires a huge amount of computation. *4.4.4 Other Minimization Methods Although the previous subsections form an introduction to logic minimization algorithms, the methods they describe are by no means the latest and greatest. Spurred on by the ever increasing density of VLSI chips, many researchers have discovered more effective ways to minimize combinational logic functions. Their results fall roughly into three categories: 1. Computational improvements. Improved algorithms typically use clever data structures or rearrange the order of the steps to reduce the memory requirements and execution time of the classical algorithms. 2. Heuristic methods. Some minimization problems are just too big to be solved using an exact algorithm. These problems can be attacked using
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More information on these methods can be found in the References.
shortcuts and well-educated guesses to reduce memory size and execution time to a fraction of what an exact algorithm would require. However, rather than finding a provably minimal expression for a logic function, heuristic methods attempt to find an almost minimal one. Even for problems that can be solved by an exact method, a heuristic method typically finds a good solution ten times faster. The most successful heuristic program, Espresso-II, does in fact produce minimal or nearminimal results for the majority of problems (within one or two product terms), including problems with dozens of inputs and hundreds of product terms. 3. Looking at things differently. As we mentioned earlier, multiple-output minimization can be handled by straightforward, fairly mechanical modifications to single-output minimization methods. However, by looking at multiple-output minimization as a problem in multivalued (nonbinary) logic, the designers of the Espresso-MV algorithm were able to make substantial performance improvements over Espresso-II.
*4.5 Timing Hazards
The analysis methods that we developed in Section 4.2 ignore circuit delay and predict only the steady-state behavior of combinational logic circuits. That is, they predict a circuits output as a function of its inputs under the assumption that the inputs have been stable for a long time, relative to the delays in the circuits electronics. However, we showed in Section 3.6 that the actual delay from an input change to the corresponding output change in a real logic circuit is nonzero and depends on many factors. Because of circuit delays, the transient behavior of a logic circuit may differ from what is predicted by a steady-state analysis. In particular, a circuits output may produce a short pulse, often called a glitch, at a time when steadystate analysis predicts that the output should not change. A hazard is said to exist when a circuit has the possibility of producing such a glitch. Whether or not the glitch actually occurs depends on the exact delays and other electrical characteristics of the circuit. Since such parameters are difficult to control in production circuits, a logic designer must be prepared to eliminate hazards (the possibility of a glitch) even though a glitch may occur only under a worst-case combination of logical and electrical conditions.
*4.5.1 Static Hazards A static-1 hazard is the possibility of a circuits output producing a 0 glitch when we would expect the output to remain at a nice steady 1 based on a static analysis of the circuit function. A formal definition is given as follows.
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Figure 4-44 Circuit with a static-1 hazard: (a) logic diagram; (b) timing diagram.
Definition: A static-1 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both give a 1 output; such that it is possible for a momentary 0 output to occur during a transition in the differing input variable. For example, consider the logic circuit in Figure 4-44(a). Suppose that X and Y are both 1, and Z is changing from 1 to 0. Then (b) shows the timing diagram assuming that the propagation delay through each gate or inverter is one unit time. Even though static analysis predicts that the output is 1 for both input combinations X,Y,Z = 111 and X,Y,Z = 110, the timing diagram shows that F goes to 0 for one unit time during a 1-0 transition on Z, because of the delay in the inverter that generates Z. A static-0 hazard is the possibility of a 1 glitch when we expect the circuit to have a steady 0 output:
Definition: A static-0 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both give a 0 output; such that it is possible for a momentary 1 output to occur during a transition in the differing input variable.
Since a static-0 hazard is just the dual of a static-1 hazard, an OR-AND circuit that is the dual of Figure 4-44(a) would have a static-0 hazard. An OR-AND circuit with four static-0 hazards is shown in Figure 4-45(a). One of the hazards occurs when W,X,Y = 000 and Z is changed, as shown in (b). You should be able to find the other three hazards and eliminate all of them after studying the next subsection. *4.5.2 Finding Static Hazards Using Maps A Karnaugh map can be used to detect static hazards in a two-level sum-ofproducts or product-of-sums circuit. The existence or nonexistence of static hazards depends on the circuit design for a logic function. A properly designed two-level sum-of-products (AND-OR) circuit has no static-0 hazards. A static-0 hazard would exist in such a circuit only if both a
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Figure 4-46 Karnaugh map for the circuit of Figure 4-44: (a) as originally designed; (b) with static-1 hazard eliminated.
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variable and its complement were connected to the same AND gate, which would be silly. However, the circuit may have static-1 hazards. Their existence can be predicted from a Karnaugh map where the product terms corresponding to the AND gates in the circuit are circled. Figure 4-46(a) shows the Karnaugh map for the circuit of Figure 4-44. It is clear from the map that there is no single product term that covers both input combinations X,Y,Z = 111 and X,Y,Z = 110. Thus, intuitively, it is possible for the output to glitch momentarily to 0 if the AND gate output that covers one of the combinations goes to 0 before the AND gate output covering the other input combination goes to 1. The way to eliminate the hazard is also quite apparent: Simply include an extra product term (AND gate) to cover the hazardous input pair, as shown in Figure 4-46(b). The extra product term, it turns out, is the consensus of the two original terms; in general, we must add consensus terms to eliminate hazards. The corresponding hazard-free circuit is shown in Figure 4-47. Another example is shown in Figure 4-48. In this example, three product terms must be added to eliminate the static-1 hazards. A properly designed two-level product-of-sums (OR-AND) circuit has no static-1 hazards. It m ay have static-0 hazards, however. These hazards can be detected and eliminated by studying the adjacent 0s in the Karnaugh map, in a manner dual to the foregoing.
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*4.5.3 Dynamic Hazards A dynamic hazard is the possibility of an output changing more than once as the result of a single input transition. Multiple output transitions can occur if there are multiple paths with different delays from the changing input to the changing output. For example, consider the circuit in Figure 4-49; it has three different paths from input X to the output F. One of the paths goes through a slow OR gate, and another goes through an OR gate that is even slower. If the input to the circuit is W,X,Y,Z = 0,0,0,1, then the output will be 1, as shown. Now suppose we change the X input to 1. Assuming that all of the gates except the two marked slow and slower are very fast, the transitions shown in black occur next, and the output goes to 0. Eventually, the output of the slow OR gate changes, creating the transitions shown in nonitalic color, and the output goes to 1. Finally, the output of the slower OR gate changes, creating the transitions shown in italic color, and the output goes to its final state of 0. Dynamic hazards do not occur in a properly designed two-level AND-OR or OR-AND circuit, that is, one in which no variable and its complement are con-
Figure 4-48 Karnaugh map for another sum-of-products circuit: (a) as originally designed; (b) with extra product terms to cover static-1 hazards.
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nected to the same first-level gate. In multilevel circuits, dynamic hazards can be discovered using a method described in the References.
*4.5.4 Designing Hazard-Free Circuits There are only a few situations, such as the design of feedback sequential circuits, that require hazard-free combinational circuits. Techniques for finding hazards in arbitrary circuits, described in the References, are rather difficult to use. So, when you require a hazard-free design, its best to use a circuit structure that is easy to analyze. In particular, we have indicated that a properly designed two-level ANDOR circuit has no static-0 or dynamic hazards. Static-1 hazards may exist in such a circuit, but they can be found and eliminated using the map method described earlier. If cost is not a problem, then a brute-force method of obtaining a hazardfree realization is to use the complete sumthe sum of all of the prime implicants of the logic function (see Exercise 4.79). In a dual manner, a hazard-free two-level OR-AND circuit can be designed for any logic function. Finally, note that everything weve said about AND-OR circuits naturally applies to the corresponding N AND-NAND designs, and for OR-AND applies to NOR-NOR.
Any combinational circuit can be analyzed for the presence of hazards. However, a well-designed, synchronous digital system is structured so that hazard analysis is not needed for most of its circuits. In a synchronous system, all of the inputs to a combinational circuit are changed at a particular time, and the outputs are not looked at until they have had time to settle to a steady-state value. Hazard analysis and elimination are typically needed only in the design of asynchronous sequential circuits, such as the feedback sequential circuits discussed in \secref{fdbkseq}. Youll rarely have reason to design such a circuit, but if you do, an understanding of hazards will be absolutely essential for a reliable result.
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4.6 The ABEL Hardware Design Language
ABEL is a hardware design language (HDL) that was invented to allow designers to specify logic functions for realization in PLDs. An ABEL program is a text file containing several elements:
Documentation, including program name and comments. Declarations that identify the inputs and outputs of the logic functions to be performed. Statements that specify the logic functions to be performed. Usually, a declaration of the type of PLD or other targeted device in which the specified logic functions are to be performed. Usually, test vectors that specify the logic functions expected outputs for certain inputs.
ABEL is supported by an ABEL language processor, which well simply call an ABEL compiler. The compilers job is to translate the ABEL text file into a fuse pattern that can be downloaded into a physical PLD. Even though most PLDs can be physically programmed only with patterns corresponding to sum-ofproducts expressions, ABEL allows PLD functions to be expressed using truth tables or nested IF statements as well as by any algebraic expression format. The compiler manipulates these formats and minimizes the resulting equations to fit, if possible, into the available PLD structure. Well talk about PLD structures, fuse patterns, and related topics later, in \secref{PLDs} and show how to target ABEL programs to specific PLDs. In the meantime, well show how ABEL can be used to specify combinational logic functions without necessarily having to declare the targeted device type. Later, in \chapref{seqPLDs}, well do the same for sequential logic functions. 4.6.1 ABEL Program Structure Table 4-10 shows the typical structure of an ABEL program, and Table 4-11 shows an actual program exhibiting the following language features:
Identifiers must begin with a letter or underscore, may contain up to 31 letters, digits, and underscores, and are case sensitive. A program file begins with a module statement, which associates an identifier (Alarm_Circuit) with the program module. Large programs can have multiple modules, each with its own local title, declarations, and equations. Note that keywords such as module are not case sensitive.
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ABEL language processor ABEL compiler identifier
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LEGAL NOTICE
ABEL (Advanced Boolean Equation Language) is a trademark of Data I/O Corporation (Redmond, WA 98073).
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Ta b l e 4 - 1 0 Typical structure of an ABEL program.
module module name title string deviceID device deviceType;
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The title statement specifies a title string that will be inserted into the documentation files that are created by the compiler. A string is a series of characters enclosed by single quotes. The optional device declaration includes a device identifier (ALARMCKT) and a string that denotes the device type (P16V8C for a GAL16V8). The compiler uses the device identifier in the names of documentation files that it generates, and it uses the device type to determine whether the device can really perform the logic functions specified in the program. Comments begin with a double quote and end with another double quote or the end of the line, whichever comes first. Pin declarations tell the compiler about symbolic names associated with the devices external pins. If the signal name is preceded with the NOT prefix (!), then the complement of the named signal will appear on the pin. Pin declarations may or may not include pin numbers; if none are given, the compiler assigns them based on the capabilities of the targeted device. The istype keyword precedes a list of one or properties, separated by commas. This tells the compiler the type of output signal. The com keyword indicates a combinational output. If no istype keyword is given, the compiler generally assumes that the signal is an input unless it appears on the left-hand side of an equation, in which case it tries to figure out the outputs properties from the context. For your own protection, its best just to use the istype keyword for all outputs! Other declarations allow the designer to define constants and expressions to improve program readability and to simplify logic design. The equations statement indicates that logic equations defining output signals as functions of input signals will follow. Equations are written like assignment statements in a conventional programming language. Each equation is terminated by a semicolon. ABEL uses the following symbols for logical operations:
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module Alarm_Circuit title Alarm Circuit Example J. Wakerly, Micro Systems Engineering ALARMCKT device P16V8C; " Input pins PANIC, ENABLEA, EXITING WINDOW, DOOR, GARAGE " Output pins ALARM " Constant definition X = .X.;
" Intermediate equation SECURE = WINDOW & DOOR & GARAGE;
equations ALARM = PANIC # ENABLEA & !EXITING & !(WINDOW & DOOR & GARAGE); test_vectors ([PANIC,ENABLEA,EXITING,WINDOW,DOOR,GARAGE] [ 1, .X., .X., .X., .X., .X.] [ 0, 0, .X., .X., .X., .X.] [ 0, 1, 1, .X., .X., .X.] [ 0, 1, 0, 0, .X., .X.] [ 0, 1, 0, .X., 0, .X.] [ 0, 1, 0, .X., .X., 0] [ 0, 1, 0, 1, 1, 1] end Alarm_Circuit
compiler recognize an alternate set of symbols for these operations: +, *, / , :+:, and :*:, respectively. This book uses the default symbols. The optional test_vectors statement indicates that test vectors follow. Test vectors associate input combinations with expected output values; they are used for simulation and testing as explained in Section 4.6.7.
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Ta b l e 4 - 1 1 An ABEL program for the alarm circuit of Figure 4-11.
pin 1, 2, 3; pin 4, 5, 6; pin 11 istype com; -> -> -> -> -> -> -> -> [ALARM]) [ 1]; [ 0]; [ 0]; [ 1]; [ 1]; [ 1]; [ 0];
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The compiler recognizes several special constants, including .X., a single bit whose value is dont-care. The end statement marks the end of the module.
Equations for combinational outputs use the unclocked assignment operator, =. The left-hand side of an equation normally contains a signal name. The right-hand side is a logic expression, not necessarily in sum-of-products form. The signal name on the left-hand side of an equation may be optionally preceded by the NOT operator !; this is equivalent to complementing the right-hand side. The compilers job is to generate a fuse pattern such that the signal named on the left-hand side realizes the logic expression on the right-hand side.
4.6.2 ABEL Compiler Operation The program in Table 4-11 realizes the alarm function that we described on page 213. The signal named ENABLE has been coded as ENABLEA because ENABLE is a reserved word in ABEL. Notice that not all of the equations appear under the equations statement. An equation for an intermediate variable, SECURE, appears earlier. This equation is merely a definition that associates an expression with the identifier SECURE. The ABEL compiler substitutes this expression for the identifier SECURE in every place that SECURE appears after its definition. In Figure 4-19 on page 214 we realized the alarm circuit directly from the SECURE and ALARM expressions, using multiple levels of logic. The ABEL compiler doesnt use expressions to interconnect gates in this way. Rather, it crunches the expressions to obtain a minimal two-level sum-of-products result appropriate for realization in a PLD. Thus, when compiled, Table 4-11 should yield a result equivalent to the AND-OR circuit that we showed in Figure 4-20 on page 214, which happens to be minimal. In fact, it does. Table 4-12 shows the synthesized equations file created by the ABEL compiler. Notice that the compiler creates equations only for the ALARM signal, the only output. The SECURE signal does not appear anywhere. The compiler finds a minimal sum-of-products expression for both ALARM and its complement, !ALARM. As mentioned previously, many PLDs have the ability selectively to invert or not to invert their AND-OR output. The reverse polarity equation in Table 4-12 is a sum-of-products realization of !ALARM, and would be used if output inversion were selected. In this example, the reverse-polarity equation has one less product term than the normal-polarity equation for ALARM, so the compiler would select this equation if the targeted device has selectable output inversion. A user can also force the compiler to use either normal or reverse polarity for a signal by including the keyword buffer or invert, respectively, in the signals istype property list. (With some ABEL compilers, keywords pos and neg can be used for this purpose, but see Section 4.6.6.)
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Design alarmckt created Tue Nov 24 1998
Title: Alarm Circuit Example Title: J. Wakerly, Micro Systems Engineering P-Terms --------4/3 ========= 4/3 Fan-in -----6 Fan-out ------1 Type ---Pin
Equations:
ALARM = (ENABLEA & !EXITING & !DOOR # ENABLEA & !EXITING & !WINDOW # ENABLEA & !EXITING & !GARAGE # PANIC);
Reverse-Polarity Equations:
!ALARM = (!PANIC & WINDOW & DOOR & GARAGE # !PANIC & EXITING # !PANIC & !ENABLEA);
4.6.3 WHEN Statements and Equation Blocks In addition to equations, ABEL provides the WHEN statement as another means to specify combinational logic functions in the equations section of an ABEL program. Table 4-13 shows the general structure of a WHEN statement, similar to an IF statement in a conventional programming language. The ELSE clause is optional. Here LogicExpression is an expression which results in a value of true (1) or false (0). Either TrueEquation or FalseEquation is executed depending
WHEN LogicExpression THEN TrueEquation; ELSE FalseEquation;
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Ta b l e 4 - 1 2 Synthesized equations file produced by ABEL for program in Table 4-11.
Name (attributes) ----------------ALARM 3 7 0 3 Best P-Term Total: Total Pins: Total Nodes: Average P-Term/Output:
WHEN statement
Ta b l e 4 - 1 3 Structure of an ABEL WHEN statement.
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equation block
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on the value of LogicExpression . But we need to be a little more precise about what we mean by executed, as discussed below. In the simplest case, TrueEquation and the optional FalseEquation are assignment statements, as in the first two WHEN statements in Table 4-14 (for X1 and X2). In this case, LogicExpression is logically ANDed with the right-hand side of TrueEquation, and the complement of LogicExpression is ANDed with the right-hand side of FalseEquation. Thus, the equations for X1A and X2A produce the same results as the corresponding WHEN statements but do not use WHEN. Notice in the first example that X1 appears in the TrueEquation, but there is no FalseEquation. So, what happens to X1 when LogicExpression (!A#B) is false? You might think that X1s value should be dont-care for these input combinations, but its not, as explained below. Formally, the unclocked assignment operator, =, specifies input combinations that should be added to the on-set for the output signal appearing on the left-hand side of the equation. An outputs on-set starts out empty, and is augmented each time that the output appears on the left-hand side of an equation. That is, the right-hand sides of all equations for the same (uncomplemented) output are ORed together. (If the output appears complemented on the left-hand side, the right-hand side is complemented before being ORed.) Thus, the value of X1 is 1 only for the input combinations for which LogicExpression (!A#B) is true and the right-hand side of TrueEquation (C&!D) is also true. In the second example, X2 appears on the left-hand side of two equations, so the equivalent equation shown for X2A is obtained by OR ing two right-hand sides after ANDing each with the appropriate condition. The TrueEquation and the optional FalseEquation in a WHEN statement can be any equation. In addition, WHEN statements can be nested by using another WHEN statement as the FalseEquation. When statements are nested, all of the conditions leading to an executed statement are ANDed. The equation for X3 and its WHEN-less counterpart for X3A in Table 4-14 illustrate the concept. The TrueEquation can be another WHEN statement if its enclosed in braces, as shown in the X4 example in the table. This is just one instance of the general use of braces described shortly. Although each of our WHEN examples have assigned values to the same output within each part of a given WHEN statement, this does not have to be the case. The second-to-last WHEN statement in Table 4-14 is such an example. Its often useful to make more than one assignment in TrueEquation or FalseEquation or both. For this purpose, ABEL supports equation blocks anywhere that it supports a single equation. An equation block is just a sequence of statements enclosed in braces, as shown in the last WHEN statement in the table. The individual statements in the sequence may be simple assignment statements, or they may be WHEN statements or nested equation blocks. A semicolon is not used after a blocks closing brace. Just for fun, Table 4-15 shows the equations that the ABEL compiler produces for the entire example program.
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module WhenEx title WHEN Statement Examples " Input pins A, B, C, D, E, F
" Output pins X1, X1A, X2, X2A, X3, X3A, X4 X5, X6, X7, X8, X9, X10 equations
WHEN (!A # B) THEN X1 = C & !D; X1A = (!A # B) & (C & !D);
WHEN (A & B) THEN X2 = C # D; ELSE X2 = E # F; X2A = (A & B) & (C # D) # !(A & B) & (E # F);
WHEN (A) THEN X3 = D; ELSE WHEN (B) THEN X3 = E; ELSE WHEN (C) THEN X3 = F;
X3A = (A) & (D) # !(A) & (B) & (E) # !(A) & !(B) & (C) & (F); WHEN (A) THEN {WHEN (B) THEN X4 = D;} ELSE X4 = E;
WHEN (A & B) THEN X5 = D; ELSE WHEN (A # !C) THEN X6 = E; ELSE WHEN (B # C) THEN X7 = F; WHEN (A) X8 = WHEN } ELSE { X8 = WHEN {X10 }
end WhenEx
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Ta b l e 4 - 1 4 Examples of WHEN statements.
pin; pin istype com; pin istype com; THEN { D & E & F; (B) THEN X8 = 1; ELSE {X9 = D; X10 = E;} !D # !E; (D) THEN X9 = 1; = C & D;}
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Design whenex created Wed Dec 2 1998 Title: WHEN Statement Examples
P-Terms Fan-in Fan-out Type Name --------- ------ ------- ---- ----2/3 4 1 Pin X1 2/3 4 1 Pin X1A 6/3 6 1 Pin X2 6/3 6 1 Pin X2A 3/4 6 1 Pin X3 3/4 6 1 Pin X3A 2/3 4 1 Pin X4 1/3 3 1 Pin X5 2/3 4 1 Pin X6 1/3 3 1 Pin X7 4/4 5 1 Pin X8 2/2 3 1 Pin X9 2/4 5 1 Pin X10 ========= 36/42 Best P-Term Total: 30 Total Pins: 19 Total Nodes: 0 Average P-Term/Output: 2
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Ta b l e 4 - 1 5 Synthesized equations file produced by ABEL for program in Table 4-14.
Equations: X1 = (C & !D & !A # C & !D & B); X1A = (C & !D & !A # C & !D & B); X2 = (D & A & B #C&A&B # !B & E # !A & E # !B & F # !A & F); X2A = (D & A & B #C&A&B # !B & E # !A & E # !B & F # !A & F); !X1 = (A & !B #D # !C); !X1A = (A & !B #D # !C); !X3 = (!C # !A # !D # !A !X3A = # # # & & & & !A & !B B & !E A !B & !F); X3 = (C & !A & !B & F # !A & B & E # D & A); X3A = (C & !A & !B & F # !A & B & E # D & A); X4 = (D & A & B # !A & E); (!C & !A & !B !A & B & !E !D & A !A & !B & !F); !X4 = (A & !B # !D & A # !A & !E); !X5 = (!A # !D # !B); X5 = (D & A & B); X6 = (A & !B & E # !C & !A & E); X7 = (C & !A & F); !X6 = (A & B # C & !A # !E); !X7 = (A # !C # !F); X8 = (D & A & E & F #A&B # !A & !E # !D & !A); X9 = (D & !A # D & !B); !X8 = (A & !B # D & !A # A & !B # !D & A & & & & !F E !E !B); !X9 = (!D # A & B); !X10 = # # # X10 = (C & D & !A # A & !B & E); (A & B !D & !A !C & !A A & !E);
Reverse-Polarity Eqns:
!X2 = (!C & !D & A & B # !B & !E & !F # !A & !E & !F); !X2A = (!C & !D & A & B # !B & !E & !F # !A & !E & !F);
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4.6.4 Truth Tables ABEL provides one more way to specify combinational logic functions the truth table, with the general format shown in Table 4-16. The keyword truth_table introduces a truth table. The input-list and output-list give the names of the input signals and the outputs that they affect. Each of these lists is either a single signal name or a set; sets are described fully in Section 4.6.5. Following the truth-table introduction are a series of statements, each of which specifies an input value and a required output value using the -> operator. For example, the truth table for an inverter is shown below:
truth_table (X -> NOTX) 0 -> 1; 1 -> 0;
The list of input values does not need to be complete; only the on-set of the function needs to be specified unless dont-care processing is enabled (see Section 4.6.6). Table 4-17 shows how the prime-number detector function described on page 213 can be specified using an ABEL program. For convenience, the identifier NUM is defined as a synonym for the set of four input bits [N3,N2,N1,N0], allowing a 4-bit input value to be written as a decimal integer.
Ta b l e 4 - 1 7 An ABEL program for the prime number detector.
module PrimeDet title '4-Bit Prime Number Detector' " Input and output pins N0, N1, N2, N3 F " Definition NUM = [N3,N2,N1,N0]; truth_table (NUM 1 2 3 5 7 11 13 end PrimeDet -> -> -> -> -> -> -> ->
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truth_table (input-list -> output-list) input-value -> output-value; ... input-value -> output-value;
Ta b l e 4 - 1 6 Structure of an ABEL truth table.
truth table truth_table input-list output-list
unclocked truth-table operator, ->
pin; pin istype 'com';
F) 1; 1; 1; 1; 1; 1; 1;
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range
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relation relational operator
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Y1 Y2 Y3 Y4 = = = = N3 N2 N1 N0 & & & & M3; M2; M1; M0;
Both truth tables and equations can be used within the same ABEL program. The equations keyword introduces a sequence of equations, while the truth_table keyword introduces a single truth table.
4.6.5 Ranges, Sets, and Relations Most digital systems include buses, registers, and other circuits that handle a group of two or more signals in an identical fashion. ABEL provides several shortcuts for conveniently defining and using such signals. The first shortcut is for naming similar, numbered signals. As shown in the pin definitions in Table 4-18, a range of signal names can be defined by stating the first and last names in the range, separated by ... For example, writing N3..N0 is the same as writing N3,N2,N1,N0. Notice in the table that the range can be ascending or descending. Next, we need a facility for writing equations more compactly when a group of signals are all handled identically, in order to reduce the chance of errors and inconsistencies. An ABEL set is simply a defined collection of signals that is handled as a unit. When a logical operation such as AND, OR, or assignment is applied to a set, it is applied to each element of the set. Each set is defined at the beginning of the program by associating a set name with a bracketed list of the set elements (e.g., N=[N3,N2,N1,N0] in Table 4-18). The set element list may use shortcut notation (YOUT=[Y1..Y4]), but the element names need not be similar or have any correspondence with the set name (COMP=[EQ,GE]). Set elements can also be constants (GT=[0,1]). In any case, the number and order of elements in a set are significant, as well see. Most of ABELs operators, can be applied to sets. When an operation is applied to two or more sets, all of the sets must have the same number of elements, and the operation is applied individually to set elements in like positions, regardless of their names or numbers. Thus, the equation YOUT = N & M is equivalent to four equations:
When an operation includes both set and nonset variables, the nonset variables are combined individually with set elements in each position. Thus, the equation ZOUT = (SEL & N) # (!SEL & M) is equivalent to four equations of the form Zi = (SEL & Ni) # (!SEL & Mi) for i equal 0 to 3. Another important feature is ABELs ability to convert relations into logic expressions. A relation is a pair of operands combined with one of the relational operators listed in Table 4-19. The compiler converts a relation into a logic expression that is 1 if and only if the relation is true. The operands in a relation are treated as unsigned integers, and either operand may be an integer or a set. If the operand is a set, it is treated as an unsigned
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module SetOps title 'Set Operation Examples'
" Input and output pins N3..N0, M3..M0, SEL Y1..Y4, Z0..Z3, EQ, GE, GTR, LTH, UNLUCKY " Definitions N = [N3,N2,N1,N0]; M = [M3,M2,M1,M0]; YOUT = [Y1..Y4]; ZOUT = [Z3..Z0]; COMP = [EQ,GE]; GT = [ 0, 1]; LT = [ 0, 0]; equations
YOUT = N & M; ZOUT = (SEL & N) # (!SEL & M); EQ = (N == M); GE = (N >= M); GTR = (COMP == GT); LTH = (COMP == LT); UNLUCKY = (N == 13) # (M == ^hD) # ((N + M) == ^b1101); end SetOps
binary integer with the leftmost variable representing the most significant bit. By default, numbers in ABEL programs are assumed to be base-10. Hexadecimal and binary numbers are denoted by a prefix of ^h or ^b, respectively, as shown in the last equation in Table 4-18. ABEL sets and relations allow a lot of functionality to be expressed in very few lines of code. For example, the equations in Table 4-18 generate minimized equations with 69 product terms, as shown in the summary in Table 4-20.
Symbol Relation
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Ta b l e 4 - 1 8 Examples of ABEL ranges, sets, and relations.
pin; pin istype 'com';
== != < <= > >= equal not equal less than less than or equal greater than greater than or equal
^h hexadecimal prefix ^b binary prefix
Ta b l e 4 - 1 9 Relational operators in ABEL.
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@DCSET dc ?= dont-care unclocked assignment operator
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Ta b l e 4 - 2 0 Synthesized equations summary produced by ABEL for program in Table 4-18.
Fan-in -----2 2 2 2 3 3 3 3 8 8 2 2 8 Fan-out ------1 1 1 1 1 1 1 1 1 1 1 1 1 Type ---Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Name (attributes) ----------------Y1 Y2 Y3 Y4 Z0 Z1 Z2 Z3 EQ GE GTR LTH UNLUCKY 53 22 0 4 P-Terms --------1/2 1/2 1/2 1/2 2/2 2/2 2/2 2/2 16/8 23/15 1/2 1/2 16/19 ========= 69/62 Best P-Term Total: Total Pins: Total Nodes: Average P-Term/Output:
*4.6.6 Dont-Care Inputs Some versions of the ABEL compiler have a limited ability to handle dont-care inputs. As mentioned previously, ABEL equations specify input combinations that belong to the on-set of a logic function; the remaining combinations are assumed to belong to the off-set. If some input combinations can instead be assigned to the d-set, then the program may be able to use these dont-care inputs to do a better job of minimization. The ABEL language defines two mechanisms for assigning input combinations to the d-set. In order to use either mechanism, you must include the compiler directive @DCSET in your program, or include dc in the istype property list of the outputs for which you want dont-cares to be considered. The first mechanism is the dont-care unclocked assignment operator, ?=. This operator is used instead of = in equations to indicate that input combinations matching the right-hand side should be put into the d-set instead of the on-set. Although this operator is documented in the ABEL compiler that I use, unfortunately it is broken, so Im not going to talk about it anymore. The second mechanism is the truth table. When dont-care processing is enabled, any input combinations that are not explicitly listed in the truth table are put into the d-set. Thus, the prime BCD-digit detector described on page 230 can be specified in ABEL as shown in Table 4-21. A dont-care value is implied for input combinations 1015 because these combinations do not appear in the truth table and the @DCSET directive is in effect.
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module DontCare title 'Dont Care Examples' @DCSET " Input and output pins N3..N0, A, B F, Y NUM = [N3..N0]; X = .X.;
truth_table (NUM->F) 0->0; 1->1; 2->1; 3->1; 4->0; 5->1; 6->0; 7->1; 8->0; 9->0;
truth_table ([A,B]->Y) [0,0]->0; [0,1]->X; [1,0]->X; [1,1]->1; end DontCare
Its also possible to specify dont-care combinations explicitly, as shown in the second truth table. As introduced at the very beginning of this section, ABEL recognizes .X. as a special one-bit constant whose value is dont-care. In Table 4-21, the identifier X has been equated to this constant just to make it easier to type dont-cares in the truth table. The minimized equations resulting from Table 4-21 are shown in Table 4-22. Notice that the two equations for F are not equal; the compiler has selected different values for the dont-cares.
Equations: F = (!N2 & N1 # !N3 & N0); Y = (B);
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Ta b l e 4 - 2 1 ABEL program using dont-cares.
pin; pin istype 'com';
Ta b l e 4 - 2 2 Minimized equations derived from Table 4-21.
Reverse-Polarity Equations: !F = (N2 & !N0 # N3 # !N1 & !N0); !Y = (!B);
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input-list output-list
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test_vectors (input-list -> output-list) input-value -> output-value; ... input-value -> output-value;
Ta b l e 4 - 2 3 Structure of ABEL test vectors.
4.6.7 Test Vectors ABEL programs may contain optional test vectors, as we showed in Table 4-11 on page 249. The general format of test vectors is very similar to a truth table and is shown in Table 4-23. The keyword test_vectors introduces a truth table. The input-list and output-list give the names of the input signals and the outputs that they affect. Each of these lists is either a single signal name or a set. Following the test-vector introduction are a series of statements, each of which specifies an input value and an expected output value using the -> operator. ABEL test vectors have two main uses and purposes: 1. After the ABEL compiler translates the program into fuse pattern for a particular device, it simulates the operation of the final programmed device by applying the test-vector inputs to a software model of the device and comparing its outputs with the corresponding test-vector outputs. The designer may specify a series of test vectors in order to double-check that device will behave as expected for some or all input combinations. 2. After a PLD is physically programmed, the programming unit applies the test-vector inputs to the physical device and compares the device outputs with the corresponding test-vector outputs. This is done to check for correct device programming and operation.
Unfortunately, ABEL test vectors seldom do a very good job at either one of these tasks, as well explain. The test vectors from Table 4-11 are repeated in Table 4-24, except that for readability weve assumed that the identifier X has been equated to the dont-care constant .X., and weve added comments to number the test vectors. Table 4-24 actually appears to be a pretty good set of test vectors. From the designers point of view, these vectors fully cover the expected operation of the alarm circuit, as itemized vector-by-vector below: 1. If PANIC is 1, then the alarm output (F) should be on regardless of the other input values. All of the remaining vectors cover cases where PANIC is 0. 2. If the alarm is not enabled, then the output should be off. 3. If the alarm is enabled but were exiting, then the output should be off. 4-6. If the alarm is enabled and were not exiting, then the output should be on if any of the sensor signals WINDOW, DOOR, or GARAGE is 0. 7. If the alarm is enabled, were not exiting, and all of the sensor signals are 1, then the output should be off.
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test_vectors ([PANIC,ENABLEA,EXITING,WINDOW,DOOR,GARAGE] [ 1, X, X, X, X, X] [ 0, 0, X, X, X, X] [ 0, 1, 1, X, X, X] [ 0, 1, 0, 0, X, X] [ 0, 1, 0, X, 0, X] [ 0, 1, 0, X, X, 0] [ 0, 1, 0, 1, 1, 1]
The problem is that ABEL doesnt handle dont-cares in test-vector inputs the way that it should. For example, by all rights, test vector 1 should test 32 distinct input combinations corresponding to all 32 possible combinations of dontcare inputs ENABLEA, EXITING, WINDOW, DOOR, and GARAGE. But it doesnt. In this situation, the ABEL compiler interprets dont care as the user doesnt care what input value I use, and it just assigns 0 to all dont-care inputs in a test vector. In this example, you could have erroneously written the output equation as F = PANIC & !ENABLEA # ENABLEA & ...; the test vectors would still pass even though the panic button would work only when the system is disabled. The second use of test vectors is in physical device testing. Most physical defects in logic devices can be detected using the single stuck-at fault model, which assumes that any physical defect is equivalent to having a single gate input or output stuck at a logic 0 or 1 value. Just putting together a set of test vectors that seems to exercise a circuits functional specifications, as we did in Table 4-24, doesnt guarantee that all single stuck-at faults can be detected. The test vectors have to be chosen so that every possible stuck-at fault causes an incorrect value at the circuit output for some test-vector input combination. Table 4-25 shows a complete set of test vectors for the alarm circuit when it is realized as a two-level sum-of-products circuit. The first four vectors check for stuck-at-1 faults on the OR gate, and the last three check for stuck-at-0 faults on the AND gates; it turns out that this is sufficient to detect all single stuck-at faults. If you know something about fault testing you can generate test vectors for small circuits by hand (as I did in this example), but most designers use automated third-party tools to create high-quality test vectors for their PLD designs.
test_vectors ([PANIC,ENABLEA,EXITING,WINDOW,DOOR,GARAGE] [ 1, 0, 1, 1, 1, 1] [ 0, 1, 0, 0, 1, 1] [ 0, 1, 0, 1, 0, 1] [ 0, 1, 0, 1, 1, 0] [ 0, 0, 0, 0, 0, 0] [ 0, 1, 1, 0, 0, 0] [ 0, 1, 0, 1, 1, 1]
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-> -> -> -> -> -> -> -> [ALARM]) [ 1]; [ 0]; [ 0]; [ 1]; [ 1]; [ 1]; [ 0]; 1 2 3 4 5 6 7
Ta b l e 4 - 2 4 Test vectors for the alarm circuit program in Table 4-11.
single stuck-at fault model
-> -> -> -> -> -> -> ->
[ALARM]) [ 1]; [ 1]; [ 1]; [ 1]; [ 0]; [ 0]; [ 0];
1 2 3 4 5 6 7
Ta b l e 4 - 2 5 Single-stuck-at-fault test vectors for the minimal sum-ofproducts realization of the alarm circuit.
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4.7 VHDL References
WX YZ 00 01 10 11 00 01 10 11
0 1 4 5 8 12 13 9
A historical description of Booles development of the science of Logic appears in The Computer from Pascal to von Neumann by Herman H. Goldstine (Princeton University Press, 1972). Claude E. Shannon showed how Booles work could be applied to logic circuits in A Symbolic Analysis of Relay and Switching Circuits (Trans. AIEE, Vol. 57, 1938, pp. 713723). Although the two-valued Boolean algebra is the basis for switching algebra, a Boolean algebra need not have only two values. Boolean algebras with 2n values exist for every integer n; for example, see Discrete Mathematical Structures and Their Applications by Harold S. Stone (SRA, 1973). Such algebras may be formally defined using the so-called Huntington postulates devised by E. V. Huntington in 1907; for example, see Digital Design by M. Morris Mano (Prentice Hall, 1984). A mathematicians development of Boolean algebra based on a more modern set of postulates appears in M odern Applied Algebra by G. Birkhoff and T. C. Bartee (McGraw-Hill, 1970). Our engineering-style, direct development of switching algebra follows that of Edward J. McCluskey in his Introduction to the Theory of Switching Circuits (McGraw-Hill, 1965) and Logic Design Principles (Prentice Hall, 1986). The prime implicant theorem was proved by W. V. Quine in The Problem of Simplifying Truth Functions (Am. Math. Monthly, Vol. 59, No. 8, 1952, pp. 521531). In fact it is possible to prove a more general prime implicant theorem showing that there exists at least one minimal sum that is a sum of prime implicants even if we remove the constraint on the number of literals in the definition of minimal. A graphical method for simplifying Boolean functions was proposed by E. W. Veitch in A Chart Method for Simplifying Boolean Functions (Proc. ACM , May 1952, pp. 127133). His Veitch diagram, shown in Figure 4-50, actually reinvented a chart proposed by an English archaeologist, A. Marquand (On Logical Diagrams for n Terms, Philosophical Magazine XII, 1881, pp. 266270). The Veitch diagram or Marquand chart uses natural binary count-
Figure 4-50 A 4-variable Veitch diagram or Marquand chart.
2 3
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ing order for its rows and columns, with the result that some adjacent rows and columns differ in more than one value, and product terms do not always cover adjacent cells. M. Karnaugh showed how to fix the problem in A Map Method for Synthesis of Combinational Logic Circuits (Trans. AIEE, Comm. and Electron., Vol. 72, Part I, November 1953, pp. 593599). On the other hand, George J. Klir, in his book Introduction to the Methodology of Switching Circuits, claims that binary counting order is just as good as, perhaps better than Karnaugh-map order for minimizing logic functions. At this point, the Karnaugh vs. Veitch argument is of course irrelevant, because no one draws charts any more to minimize logic circuits. Instead, we use computer programs running logic minimization algorithms. The first of such algorithms was described by W. V. Quine in A Way to Simplify Truth Functions (Am. Math. Monthly, Vol. 62, No. 9, 1955, pp. 627631) and modified by E. J. McCluskey in Minimization of Boolean Functions (Bell Sys. Tech. J., Vol. 35, No. 5, November 1956, pp. 14171444). The Quine-McCluskey algorithm is fully described in McCluskeys books cited earlier. McCluskeys 1965 book also covers the iterative consensus algorithm for finding prime implicants, and proves that it works. The starting point for this algorithm is a sum-of-products expression, or equivalently, a list of cubes. The product terms need not be minterms or prime implicants, but may be either or anything in between. In other words, the cubes in the list may have any and all dimensions, from 0 to n in an n-variable function. Starting with the list of cubes, the algorithm generates a list of all the prime-implicant cubes of the function, without ever having to generate a full minterm list. The iterative consensus algorithm was first published by T. H. Mott, Jr., in Determination of the Irredundant Normal Forms of a Truth Function by Iterated Consensus of the Prime Implicants (IRE Trans. Electron. Computers, Vol. EC-9, No. 2, 1960, pp. 245252). A generalized consensus algorithm was published by Pierre Tison in Generalization of Consensus Theory and Application to the Minimization of Boolean Functions (IEEE Trans. Electron. Computers, Vol. EC-16, No. 4, 1967, pp. 446456). All of these algorithms are described by Thomas Downs in Logic Design with Pascal (Van Nostrand Reinhold, 1988). As we explained in Section 4.4.4, the huge number of prime implicants in some logic functions makes it impractical or impossible deterministically to find them all or select a minimal cover. However, efficient heuristic methods can find solutions that are close to minimal. The Espresso-II method is described in Logic Minimization Algorithms for VLSI Synthesis by R. K. Brayton, C. McMullen, G. D. Hachtel, and A. Sangiovanni-Vincentelli (Kluwer Academic Publishers, 1984). The more recent Espresso-MV and Espresso-EXACT algorithms are described in Multiple-Valued Minimization for PLA Optimization by R. L. Rudell and A. Sangiovanni-Vincentelli (IEEE Trans. CAD, Vol. CAD-6, No. 5, 1987, pp. 727750).
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4.1 Copyright 1999 by John F. Wakerly
In this chapter we described a map method for finding static hazards in two-level AND -OR and OR-AND circuits, but any combinational circuit can be analyzed for hazards. In both his 1965 and 1986 books, McCluskey defines the 0-set and 1-sets of a circuit and shows how they can be used to find static hazards. He also defines P-sets and S-sets and shows how they can be used to find dynamic hazards. Many deeper and varied aspects of switching theory have been omitted from this book, but have been beaten to death in other books and literature. A good starting point for an academic study of classical switching theory is Zvi Kohavis book, Switching and Finite Automata Theory, 2nd ed. (McGrawHill, 1978), which includes material on set theory, symmetric networks, functional decomposition, threshold logic, fault detection, and path sensitization. Another area of great academic interest (but little commercial activity) is nonbinary multiple-valued logic, in which each signal line can take on more than two values. In his 1986 book, McCluskey gives a good introduction to multiplevalued logic, explaining its pros and cons and why it has seen little commercial development. Over the years, Ive struggled to find a readily accessible and definitive reference on the ABEL language, and Ive finally found itAppendix A of Digital Design Using ABEL, by David Pellerin and Michael Holley (Prentice Hall, 1994). It makes sense that this would be the definitive workPellerin and Holley invented the language and wrote the original compiler code! All of the ABEL and VHDL examples in this chapter and throughout the text were compiled and in most cases simulated using Foundation 1.5 Student Edition software from Xilinx, Inc. (San Jose, CA 95124, www.xilinx.com). This package integrates a schematic editor, HDL editor, compilers for ABEL, VHDL and Verilog, and a simulator from Aldec, Inc. (Henderson, NV 89014, www.aldec.com) along with Xilinx own specialized tools for CPLD and FPGA design and programming. This software package includes an excellent on-line help system, including reference manuals for both ABEL and VHDL. We briefly discussed device testing in the context of ABEL test vectors. There is a large, well-established body of literature on digital device testing, and a good starting point for study is McCluskeys 1986 book. Generating a set of test vectors that completely tests a large circuit such as a PLD is a task best left to a program. At least one companys entire business is focused on programs that automatically create test vectors for PLD testing (ACUGEN Software, Inc., Nashua, NH 03063, www.acugen.com).
Using variables NERD, DESIGNER, FAILURE, and STUDIED, write a boolean expression that is 1 for successful designers who never studied and for nerds who studied all the time. Copying Prohibited
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4.2 4.3 4.4 4.5
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4.10 Write the canonical sum and product for each of the following logic functions: (a) F = X,Y,Z(0,3) (b) F = A,B,C(1,2,4) (c) F = A,B,C,D(1,2,5,6) (d) F = M,N,P(0,1,3,6,7) (f) F = AB + BC + A
4.11 If the canonical sum for an n-input logic function is also a minimal sum, how many literals are in each product term of the sum? Might there be any other minimal sums in this case? 4.12 Give two reasons why the cost of inverters is not included in the definition of minimal for logic minimization.
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Prove theorems T2T5 using perfect induction. Prove theorems T1T3 and T5 using perfect induction. Prove theorems T6T9 using perfect induction. According to DeMorgans theorem, the complement of X + Y Z is X Y+ Z. Yet both functions are 1 for XYZ = 110. How can both a function and its complement be 1 for the same input combination? Whats wrong here? Use the theorems of switching algebra to simplify each of the following logic functions: (b) F = A B + A B C D + A B D E + A B C E + C D E (c) F = M N O + Q P N + P R M + Q O M P + M R (a) F = W X Y Z (W X Y Z + W X Y Z + W X Y Z + W X Y Z) Write the truth table for each of the following logic functions:
(a) F = X Y + X Y Z
(b) F = W X + Y Z + X Z
(c) F = W + X (Y + Z)
(d) F = A B + B C + C D + D A (h) F = (((A + B) + C) + D)
(e) F = V W + X Y Z
(f) F = (A + B + C D) (B + C + D E)
(g) F = (W X) (Y + Z)
(i) F = (A + B + C) (A + B + D ) (B + C + D) (A + B + C + D)
Write the truth table for each of the following logic functions: (a) F = X Y Z + X Y Z + X Y Z (c) F = A B + A B C + A B C
(b) F = M N + M P + N P
(d) F = A B (C B A + B C ) (h) F = X Y + Y Z + Z X
(e) F = X Y (X Y Z + X Y Z + X Y Z + X Y Z) (f) F = M N + M N P (g) F = (A + A) B + B A C + C (A + B) (A + B)
Write the canonical sum and product for each of the following logic functions: (b) F = A,B(0,1,2) (d) F = W,X,Y(0,1,3,4,5) (f) F = V + (W X)
(a) F = X,Y(1,2)
(c) F = A,B,C(2,4,6,7) (e) F = X + Y Z
(e) F = X + Y Z + Y Z
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(a) F = X,Y,Z(1,3,5,6,7) (b) F = W,X,Y,Z(1,4,5,6,7,9,14,15) (c) F = W,X,Y(0,1,3,4,5) (d) F = W,X,Y,Z(0,2,5,7,8,10,13,15) (e) F = A,B,C,D(1,7,9,13,15) (f) F = A,B,C,D(1,4,5,7,12,14,15) (a) F = A,B,C(0,1,2,4) (b) F = W,X,Y,Z(1,4,5,6,11,12,13,14) (c) F = A,B,C(1,2,6,7) (e) F = W,X,Y,X(1,2,4,7,8,11,13,14) (a) F = W,X,Y,Z(0,1,3,5,14) + d(8,15) (c) F = A,B,C,D(1,5,9,14,15) + d(11) (e) F = W,X,Y,Z(3,5,6,7,13) + d(1,2,4,12,15) (a) F = W X + WY (c) F = W Y + X Y + W X Z (e) F = (W + X + Y) (X + Z) (g) F = (W + Y + Z) (W + X + Y + Z) (X + Y) (X + Z) Exercises Copyright 1999 by John F. Wakerly
4.13 Using Karnaugh maps, find a minimal sum-of-products expression for each of the following logic functions. Indicate the distinguished 1-cells in each map.
4.14 Find a minimal product-of-sums expression for each function in Drill 4.13 using the method of Section 4.3.6. 4.15 Find a minimal product-of-sums expression for the function in each of the following figures and compare its cost with the previously found minimal sum-ofproducts expression: (a) Figure 4-27; (b) Figure 4-29; (c) Figure 4-33. 4.16 Using Karnaugh maps, find a minimal sum-of-products expression for each of the following logic functions. Indicate the distinguished 1-cells in each map. (d) F = W,X,Y,Z(0,1,2,3,7,8,10,11,15)
(f) F = A,B,C,D(1,3,4,5,6,7,9,12,13,14)
4.17 Find a minimal product-of-sums expression for each function in Drill 4.16 using the method of Section 4.3.6. 4.18 Find the complete sum for the logic functions in Drill 4.16(d) and (e). 4.19 Using Karnaugh maps, find a minimal sum-of-products expression for each of the following logic functions. Indicate the distinguished 1-cells in each map. (b) F = W,X,Y,Z(0,1,2,8,11) + d(3,9,15) (d) F = A,B,C,D(1,5,6,7,9,13) + d(4,15)
4.20 Repeat Drill 4.19, finding a minimal product-of-sums expression for each logic function. 4.21 For each logic function in the two preceding exercises, determine whether the minimal sum-of-products expression equals the minimal product-of-sums expression. Also compare the circuit cost for realizing each of the two expressions. 4.22 For each of the following logic expressions, find all of the static hazards in the corresponding two-level AND-OR or OR-AND circuit, and design a hazard-free circuit that realizes the same logic function. (b) F = W X Y + X Y Z + X Y (d) F = W X + Y Z + W X Y Z + W X Y Z
(f) F = (W + Y+Z) (W + X + Z) (X+Y+Z)
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4.23 Design a non-trivial-looking logic circuit that contains a feedback loop but whose output depends only on its current input. 4.24 Prove the combining theorem T10 without using perfect induction, but assuming that theorems T1T9 and T1 T9 are true. 4.25 Show that the combining theorem, T10, is just a special case of consensus (T11) used with covering (T9). 4.26 Prove that (X + Y) Y = X Y without using perfect induction. You may assume that theorems T1T11 and T1T11 are true. 4.27 Prove that (X+Y) (X+ Z) = X Z + X Y without using perfect induction. You may assume that theorems T1T11 and T1T11 are true. 4.28 Show that an n-input AND gate can be replaced by n1 2-input AND gates. Can the same statement be made for NAND gates? Justify your answer. 4.29 How many physically different ways are there to realize V W X Y Z using four 2-input AND gates (4/4 of a 74LS08)? Justify your answer. 4.30 Use switching algebra to prove that tying together two inputs of an n + 1-input AND or OR gate gives it the functionality of an n-input gate. 4.31 Prove DeMorgans theorems (T13 and T13) using finite induction. 4.32 Which logic symbol more closely approximates the internal realization of a TTL NOR gate, Figure 4-4(c) or (d)? Why? 4.33 Use the theorems of switching algebra to rewrite the following expression using as few inversions as possible (complemented parentheses are allowed):
B C + A C D + A C + E B + E (A + C) (A + D)
4.34 Prove or disprove the following propositions: (a) Let A and B be switching-algebra variables. Then A B = 0 and A + B = 1 implies that A = B. (b) Let X and Y be switching-algebra expressions. Then X Y = 0 and X + Y = 1 implies that X = Y. 4.35 Prove Shannons expansion theorems. (Hint: Dont get carried away; its easy.) 4.36 Shannons expansion theorems can be generalized to pull out not just one but i variables so that a logic function can be expressed as a sum or product of 2 i terms. State the generalized Shannon expansion theorems. 4.37 Show how the generalized Shannon expansion theorems lead to the canonical sum and canonical product representations of logic functions. 4.38 An Exclusive OR (XOR) gate is a 2-input gate whose output is 1 if and only if exactly one of its inputs is 1. Write a truth table, sum-of-products expression, and corresponding AND-OR circuit for the Exclusive OR function. 4.39 From the point of view of switching algebra, what is the function of a 2-input XOR gate whose inputs are tied together? How might the output behavior of a real XOR gate differ? 4.40 After completing the design and fabrication of a digital system, a designer finds that one more inverter is required. However, the only spare gates in the system are
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4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 (a) F = X (b) F = X,Y,Z(0,3,5,6) (c) F = X Y + X Y (e) A function F of 7 variables such that F = 1 if and only if 4 or more of the variables are 1
A1 B1 A2 B2 Z1 Z2
a 3-input OR, a 2-input AND, and a 2-input XOR. How should the designer realize the inverter function without adding another IC? Any set of logic-gate types that can realize any logic function is called a complete set of logic gates. For example, 2-input AND gates, 2-input OR gates, and inverters are a complete set, because any logic function can be expressed as a sum of products of variables and their complements, and AND and OR gates with any number of inputs can be made from 2-input gates. Do 2-input N AND gates form a complete set of logic gates? Prove your answer. Do 2-input NOR gates form a complete set of logic gates? Prove your answer. Do 2-input XOR gates form a complete set of logic gates? Prove your answer. Define a two-input gate, other than NAND , NOR, or XOR, that forms a complete set of logic gates if the constant inputs 0 and 1 are allowed. Prove your answer. Some people think that there are four basic logic functions, AND, OR, NOT, and BUT. Figure X4.45 is a possible symbol for a 4-input, 2-output BUT gate. Invent a useful, nontrivial function for the BUT gate to perform. The function should have something to do with the name (BUT ). Keep in mind that, due to the symmetry of the symbol, the function should be symmetric with respect to the A and B inputs of each section and with respect to sections 1 and 2. Describe your BUTs function and write its truth table. Write logic expressions for the Z1 and Z2 outputs of the BUT gate you designed in the preceding exercise, and draw a corresponding logic diagram using AND gates, OR gates, and inverters. Most students have no problem using theorem T8 to multiply out logic expressions, but many develop a mental block if they try to use theorem T8 to add out a logic expression. How can duality be used to overcome this problem? How many different logic functions are there of n variables? How many different 2-variable logic functions F(X,Y) are there? Write a simplified algebraic expression for each of them. A self-dual logic function is a function F such that F = FD. Which of the following functions are self-dual? (The symbol denotes the Exclusive OR (XOR) operation.) (d) F = W (XYZ) + W (XYZ) (f) A function F of 10 variables such that F = 1 if and only if 5 or more of the variables are 1
4.51 How many self-dual logic functions of n input variables are there? (Hint: Consider the structure of the truth table of a self-dual function.)
Figure X4.45
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4.52 Prove that any n-input logic function F(X1,,Xn) that can be written in the form F = X1 G(X2,,Xn) + X1 GD(X2,,Xn) is self-dual. 4.53 Assuming that an inverting gate has a propagation delay of 5 ns, and a noninverting gate has a propagation delay of 8 ns, compare the speeds of the circuits in Figure 4-24(a), (c), and (d). 4.54 Find the minimal product-of-sums expressions for the logic functions in Figures 4-27 and 4-29. 4.55 Use switching algebra to show that the logic functions obtained in Exercise 4.54 equal the AND-OR functions obtained in Figures 4-27 and 4-29. 4.56 Determine whether the product-of-sums expressions obtained by adding out the minimal sums in Figure 4-27 and 4-29 are minimal. 4.57 Prove that the rule for combining 2 i 1-cells in a Karnaugh map is true, using the axioms and theorems of switching algebra. 4.58 An irredundant sum for a logic function F is a sum of prime implicants for F such that if any prime implicant is deleted, the sum no longer equals F. This sounds a lot like a minimal sum, but an irredundant sum is not necessarily minimal. For example, the minimal sum of the function in Figure 4-35 has only three product terms, but there is an irredundant sum with four product terms. Find the irredundant sum and draw a map of the function, circling only the prime implicants in the irredundant sum. 4.59 Find another logic function in Section 4.3 that has one or more nonminimal irredundant sums, and draw its map, circling only the prime implicants in the irredundant sum. 4.60 Derive the minimal product-of-sums expression for the prime BCD-digit detector function of Figure 4-37. Determine whether or not the expression algebraically equals the minimal sum-of-products expression and explain your result. 4.61 Draw a Karnaugh map and assign variables to the inputs of the AND-XOR circuit in Figure X4.61 so that its output is F = W,X,Y,Z(6,7,12,13). Note that the output gate is a 2-input XOR rather than an OR.
4.62 The text indicates that a truth table or equivalent is the starting point for traditional combinational minimization methods. A Karnaugh map itself contains the same information as a truth table. Given a sum-of-products expression, it is possible to write the 1s corresponding to each product term directly on the map without developing an explicit truth table or minterm list, and then proceed with
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Figure X4.61
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the map minimization procedure. Find a minimal sum-of-products expression for each of the following logic functions in this way: (b) F = A C D + B C D + A C D + B C D (d) F = (X + Y) (W + X + Y) (W+ X + Z)
(a) F = X Z + X Y + X Y Z
(c) F = W X Z + W X Y Z + X Z
(e) F = A B C D + A B C + A B D + A C D + B C D
4.63 Repeat Exercise 4-60, finding a minimal product-of-sums expression for each logic function. 4.64 A Karnaugh map for a 5-variable function can be drawn as shown in Figure X4.64. In such a map, cells that occupy the same relative position in the V = 0 and V = 1 submaps are considered to be adjacent. (Many worked examples of 5-variable Karnaugh maps appear in Sections \ref{synD} and~\ref{synJK}.) Find a minimal sum-of-products expression for each of the following functions using a 5-variable map: (a) F = V,W,X,Y,Z(5,7,13,15,16,20,25,27,29,31) (b) F = V,W,X,Y,Z(0,7,8,9,12,13,15,16,22,23,30,31)
(c) F = V,W,X,Y,Z(0,1,2,3,4,5,10,11,14,20,21,24,25,26,27,28,29,30) (d) F = V,W,X,Y,Z(0,2,4,6,7,8,10,11,12,13,14,16,18,19,29,30) (e) F = V,W,X,Y,Z(4,5,10,12,13,16,17,21,25,26,27,29)
(f) F = V,W,X,Y,Z(4,6,7,9,11,12,13,14,15,20,22,25,27,28,30)+d(1,5,29,31)
4.65 Repeat Exercise 4.64, finding a minimal product-of-sums expression for each logic function. 4.66 A Karnaugh map for a 6-variable function can be drawn as shown in Figure X4.66. In such a map, cells that occupy the same relative position in adjacent submaps are considered to be adjacent. Minimize the following functions using 6-variable maps: (a) F = U,V,W,X,Y,Z(1,5,9,13,21,23,29,31,37,45,53,61) (b) F = U,V,W,X,Y,Z(0,4,8,16,24,32,34,36,37,39,40,48,50,56)
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4.67 A 3-bit comparator circuit receives two 3-bit numbers, P = P2P1P0 and Q = Q2Q1Q 0. Design a minimal sum-of-products circuit that produces a 1 output if and only if P > Q. 4.68 Find minimal multiple-output sum-of-products expressions for F = X,Y,Z(0,1,2), G = X,Y,Z(1,4,6), and H = X,Y,Z(0,1,2,4,6). 4.69 Prove whether or not the following expression is a minimal sum. Do it the easiest way possible (algebraically, not using maps).
F
4.70 There are 2n m-subcubes of an n-cube for the value m = n 1. Show their text representations and the corresponding product terms. (You may use ellipses as required, e.g., 1, 2, , n.) 4.71 There is just one m-subcube of an n-cube for the value m = n; its text representation is xxxx. Write the product term corresponding to this cube. 4.72 The C program in Table 4-9 uses memory inefficiently because it allocates memory for a maximum number of cubes at each level, even if this maximum is never used. Redesign the program so that the cubes and used arrays are one-dimensional arrays, and each level uses only as many array entries as needed. (Hint: You can still allocate cubes sequentially, but keep track of the starting point in the array for each level.) 4.73 As a function of m, how many times is each distinct m-cube rediscovered in Table 4-9, only to be found in the inner loop and thrown away? Suggest some ways to eliminate this inefficiency. Copyright 1999 by John F. Wakerly Copying Prohibited
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4.74 The third for-loop in Table 4-9 tries to combine all m-cubes at a given level with all other m-cubes at that level. In fact, only m-cubes with xs in the same positions can be combined, so it is possible to reduce the number of loop iterations by using a more sophisticated data structure. Design a data structure that segregates the cubes at a given level according to the position of their xs, and determine the maximum size required for various elements of the data structure. Rewrite Table 4-9 accordingly. 4.75 Estimate whether the savings in inner-loop iterations achieved in Exercise 4.75 outweighs the overhead of maintaining a more complex data structure. Try to make reasonable assumptions about how cubes are distributed at each level, and indicate how your results are affected by these assumptions. 4.76 Optimize the Oneones function in Table 4-8. An obvious optimization is to drop out of the loop early, but other optimizations exist that eliminate the for loop entirely. One is based on table look-up and another uses a tricky computation involving complementing, Exclusive ORing, and addition. 4.77 Extend the C program in Table 4-9 to handle dont-care conditions. Provide another data structure, dc[MAX_VARS+1][MAX_CUBES], that indicates whether a given cube contains only dont-cares, and update it as cubes are read and generated. 4.78 (Hamlet circuit.) Complete the timing diagram and explain the function of the circuit in Figure X4.78. Where does the circuit get its name?
Figure X4.78
4.79 Prove that a two-level AND-OR circuit corresponding to the complete sum of a logic function is always hazard free. 4.80 Find a four-variable logic function whose minimal sum-of-products realization is not hazard free, but where there exists a hazard-free sum-of-products realization with fewer product terms than the complete sum. 4.81 Starting with the WHEN statements in the ABEL program in Table 4-14, work out the logic equations for variables X4 through X10 in the program. Explain any discrepancies between your results and the equations in Table 4-15. 4.82 Draw a circuit diagram corresponding to the minimal two-level sum-of-products equations for the alarm circuit, as given in Table 4-12. On each inverter, AND gate, and OR gate input and output, write a pair of numbers (t0,t1), where t0 is the test number from Table 4-25 that detects a stuck-at-0 fault on that line, and t1 is the test number that detects a stuck-at-1 fault.
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he preceding chapter described the theoretical principles used in combinational logic design. In this chapter, well build on that foundation and describe many of the devices, structures, and methods used by engineers to solve practical digital design problems. A practical combinational circuit may have dozens of inputs and outputs and could require hundreds, thousands, even millions of terms to describe as a sum of products, and billions and billions of rows to describe in a truth table. Thus, most real combinational logic design problems are too large to solve by brute-force application of theoretical techniques. But wait, you say, how could any human being conceive of such a complex logic circuit in the first place? The key is structured thinking. A complex circuit or system is conceived as a collection of smaller subsystems, each of which has a much simpler description. In combinational logic design, there are several straightforward structuresdecoders, multiplexers, comparators, and the likethat turn up quite regularly as building blocks in larger systems. The most important of these structures are described in this chapter. We describe each structure generally and then give examples and applications using 74-series components, ABEL, and VHDL. Before launching into these combinational building blocks, we need to discuss several important topics. The first topic is documentation standards
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THE IMPORTANCE OF 74-SERIES LOGIC
circuit specification
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Later in this chapter, well look at commonly used 74-series ICs that perform wellstructured logic functions. These parts are important building blocks in a digital designers toolbox because their level of functionality often matches a designers level of thinking when partitioning a large problem into smaller chunks. Even when you design for PLDs, FPGAs, or ASICs, understanding 74-series MSI functions is important. In PLD-based design, standard MSI functions can be used as a starting point for developing logic equations for more specialized functions. And in FPGA and ASIC design, the basic building blocks (or standard cells or macros) provided by the FPGA or ASIC manufacturer may actually be defined as 74-series MSI functions, even to the extent of having similar descriptive numbers.
that are used by digital designers to ensure that their designs are correct, manufacturable, and maintainable. Next we discuss circuit timing, a crucial element for successful digital design. Third, we describe the internal structure of combinational PLDs, which we use later as universal building blocks.
5.1 Documentation Standards
Good documentation is essential for correct design and efficient maintenance of digital systems. In addition to being accurate and complete, documentation must be somewhat instructive, so that a test engineer, maintenance technician, or even the original design engineer (six months after designing the circuit) can figure out how the system works just by reading the documentation. Although the type of documentation depends on system complexity and the engineering and manufacturing environments, a documentation package should generally contain at least the following six items: 1. A specification describes exactly what the circuit or system is supposed to do, including a description of all inputs and outputs (interfaces) and the functions that are to be performed. Note that the spec doesnt have to specify how the system achieves its results, just what the results are supposed to be. However, in many companies it is common practice also to incorporate one or more of the documents below into the spec to describe how the system works at the same time. 2. A block diagram is an informal pictorial description of the systems major functional modules and their basic interconnections. 3. A schematic diagram is a formal specification of the electrical components of the system, their interconnections, and all of the details needed to construct the system, including IC types, reference designators, and pin numbers. Weve been using the term logic diagram for an informal drawing that does not have quite this level of detail. Most schematic drawing
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programs have the ability to generate a bill of materials (BOM) from the schematic; this tells the purchasing department what electrical components they have to order to build the system. 4. A timing diagram shows the values of various logic signals as a function of time, including the cause-and-effect delays between critical signals. 5. A structured logic device description describes the internal function of a programmable logic device (PLD), field-programmable gate array (FPGA), or application-specific integrated circuit (ASIC). It is normally written in a hardware description language (HDL) such as ABEL or VHDL, but it may be in the form of logic equations, state tables, or state diagrams. In some cases, a conventional programming language such as C may be used to model the operation of a circuit or to specify its behavior. 6. A circuit description is a narrative text document that, in conjunction with the other documentation, explains how the circuit works internally. The circuit description should list any assumptions and potential pitfalls in the circuits design and operation, and point out the use of any nonobvious design tricks. A good circuit description also contains definitions of acronyms and other specialized terms, and has references to related documents. Youve probably already seen block diagrams in many contexts. We present a few rules for drawing them in the next subsection, and then we concentrate on schematics for combinational logic circuits in the rest of this section. Section 5.2.1 introduces timing diagrams. Structured logic descriptions in the form of ABEL and VHDL programs were covered in Sections 4.6 and 4.7. In Section 11.1.6, well show how a C program can be used to generate the contents of a read-only memory. The last area of documentation, the circuit description, is very important in practice. Just as an experienced programmer creates a program design document before beginning to write code, an experienced logic designer starts writing the circuit description before drawing the schematic. Unfortunately, the circuit description is sometimes the last document to be created, and sometimes its never written at all. A circuit without a description is difficult to debug, manufacture, test, maintain, modify, and enhance.
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DOCUMENTS ON-LINE Professional engineering documentation nowadays is carefully maintained on corporate intranets, so its very useful to include URLs in circuit specifications and descriptions so that references can be easily located. On-line documentation is so important and authoritative in one company that the footer on every page of every specification contains the warning that A printed version of this document is an uncontrolled copy. That is, a printed copy could very well be obsolete. timing diagram circuit description
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block diagram
Figure 5-1 Block diagram for a digital design project.
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DONT FORGET TO WRITE! In order to create great products, logic designers must develop their language and writing skills, especially in the area of logical outlining and organization. The most successful logic designers (and later, project leaders, system architects, and entrepreneurs) are the ones who communicate their ideas, proposals, and decisions effectively to others. Even though its a lot of fun to tinker in the digital design lab, dont use that as an excuse to shortchange your writing and communications courses and projects!
SHIFT-AND-ADD MULTIPLIER
RESET LOAD RUN R/W IN 4 CONTROL ADDR 16-word x 32-bit RAM OUT DISPLAY BYTE EN INBUS 32 32 32 32 2 direct left right SEL MULTIPLEXER 4 to 1 32 LDA LDB A REGISTER 32 B REGISTER 32 CARRY LOOKAHEAD ADDER 32 OUTBUS
5.1.1 Block Diagrams A block diagram shows the inputs, outputs, functional modules, internal data paths, and important control signals of a system. In general, it should not be so detailed that it occupies more than one page, yet it must not be too vague. A small block diagram may have three to six blocks, while a large one may have 10 to 15, depending on system complexity. In any case, the block diagram must
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show the most important system elements and how they work together. Large systems may require additional block diagrams of individual subsystems, but there should always be a top-level diagram showing the entire system. Figure 5-1 shows a sample block diagram. Each block is labeled with the function of the block, not the individual chips that comprise it. As another example, Figure 5-2(a) shows the block-diagram symbol for a 32-bit register. If the register is to be built using four 74x377 8-bit registers, and this information is important to someone reading the diagram (e.g., for cost reasons), then it can be conveyed as shown in (b). However, splitting the block to show individual chips as in (c) is incorrect. A bus is a collection of two or more related signal lines. In a block diagram, buses are drawn with a double or heavy line. A slash and a number may indicate how many individual signal lines are contained in a bus. Alternatively, size denoted in the bus name (e.g., INBUS[31..0] or INBUS[31:0]). Active levels (defined later) and inversion bubbles may or may not appear in block diagrams; in most cases, they are unimportant at this level of detail. However, important control signals and buses should have names, usually the same names that appear in the more detailed schematic. The flow of control and data in a block diagram should be clearly indicated. Logic diagrams are generally drawn with signals flowing from left to right, but in block diagrams this ideal is more difficult to achieve. Inputs and outputs may be on any side of a block, and the direction of signal flow may be arbitrary. Arrowheads are used on buses and ordinary signal lines to eliminate ambiguity.
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32 32-BIT REGISTER 32 32-BIT REGISTER 4 x 74LS377 32 (c) 32 8 8 8 8 74LS377 8 74LS377 8 74LS377 8 74LS377 8 32
Figure 5-2 A 32-bit register block: (a) realization unspecified; (b) chips specified; (c) too much detail.
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inversion bubble
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AND NAND OR NOR BUFFER (a) (b) (c)
INVERTER
Figure 5-3 Shapes for basic logic gates: (a) AND, OR, and buffers; (b) expansion of inputs; (c) inversion bubbles.
5.1.2 Gate Symbols The symbol shapes for AND and OR gates and buffers are shown in Figure 5-3(a). (Recall from Chapter 3 that a buffer is a circuit that simply converts weak logic signals into strong ones.) To draw logic gates with more than a few inputs, we expand the AND and OR symbols as shown in (b). A small circle, called an inversion bubble, denotes logical inversion or complementing and is used in the symbols for N AND and N OR gates and inverters in (c). Using the generalized DeMorgans theorem, we can manipulate the logic expressions for gates with complemented outputs. For example, if X and Y are the inputs of a NAND gate with output Z, then we can write Z = ( X Y ) = X + Y
This gives rise to two different but equally correct symbols for a NAND gate, as we demonstrated in Figure 4-3 on page 199. In fact, this sort of manipulation may be applied to gates with uncomplemented inputs as well. For example, consider the following equations for an AND gate: Z = XY = ( ( X Y ) )
= ( X + Y )
IEEE STANDARD LOGIC SYMBOLS
Together with the American National Standards Institute (ANSI), the Institute of Electrical and Electronic Engineers (IEEE) has developed a standard set of logic symbols. The most recent revision of the standard is ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions. The standard allows both rectangular- and distinctive-shape symbols for logic gates. We have been using and will continue to use the distinctive-shape symbols throughout this book, but the rectangular-shape symbols are described in Appendix A.
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Thus, an AND gate may be symbolized as an OR gate with inversion bubbles on its inputs and output. Equivalent symbols for standard gates that can be obtained by these manipulations are summarized in Figure 5-4. Even though both symbols in a pair represent the same logic function, the choice of one symbol or the other in a logic diagram is not arbitrary, at least not if we are adhering to good documentation standards. As well show in the next three subsections, proper choices of signal names and gate symbols can make logic diagrams much easier to use and understand.
5.1.3 Signal Names and Active Levels Each input and output signal in a logic circuit should have a descriptive alphanumeric label, the signals name. Most computer-aided design systems for drawing logic circuits also allow certain special characters, such as *, _, and !, to be included in signal names. In the analysis and synthesis examples in Chapter 4, we used mostly single-character signal names (X, Y, etc.) because the circuits didnt do much. However, in a real system, well-chosen signal names convey information to someone reading the logic diagram the same way that variable names in a software program do. A signals name indicates an action that is controlled (GO, PAUSE), a condition that it detects (READY, ERROR), or data that it carries (INBUS[31:0]). Each signal name should have an active level associated with it. A signal is active high if it performs the named action or denotes the named condition when it is HIGH or 1. (Under the positive-logic convention, which we use throughout this book, HIGH and 1 are equivalent.) A signal is active low if it performs the named action or denotes the named condition when it is LOW or 0. A signal is said to be asserted when it is at its active level. A signal is said to be negated (or, sometimes, deasserted) when it is not at its active level.
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OR BUFFER NOR INVERTER AND NAND
Figure 5-4 Equivalent gate symbols under the generalized DeMorgans theorem.
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active-level naming convention
_L suffix
signal name logic expression logic equation
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Ta b l e 5 - 1 Each line shows a different naming convention for active levels.
Active Low Active High
READY ERROR.L ADDR15(L) RESET* ENABLE~ ~GO /RECEIVE READY+ ERROR.H ADDR15(H) RESET ENABLE GO RECEIVE TRANSMIT_L TRANSMIT
The active level of each signal in a circuit is normally specified as part of its name, according to some convention. Examples of several different active-level naming conventions are shown in Table 5-1. The choice of one of these or other signal naming conventions is sometimes just a matter of personal preference, but more often it is constrained by the engineering environment. Since the activelevel designation is part of the signal name, the naming convention must be compatible with the input requirements of any computer-aided design tools that will process the signal names, such as schematic editors, HDL compilers, and simulators. In this text, well use the last convention in the table: An active-low signal name has a suffix of _L, and an active-high signal has no suffix. The _L suffix may be read as if it were a prefix not. Its extremely important for you to understand the difference between signal names, expressions, and equations. A signal name is just a namean alphanumeric label. A logic expression combines signal names using the operators of switching algebraAND, OR, and NOTas we explained and used throughout Chapter 4. A logic equation is an assignment of a logic expression to a signal nameit describes one signals function in terms of other signals. The distinction between signal names and logic expressions can be related to a concept used in computer programming languages: The left-hand side of an assignment statement contains a variable name, and the right-hand side contains an expression whose value will be given to the named variable (e.g., Z = -(X+Y) in C). In a programming language, you cant put an expression on the left-hand side of an assignment statement. In logic design, you cant use a logic expression as a signal name. Logic signals may have names like X, READY, and GO_L. The _L in GO_L is just part of the signals name, like an underscore in a variable name in a C program. There is no signal whose name is READYthis is an expression, since is an operator. However, there may be two signals named READY and READY_L such that READY_L = R EADY during normal operation of the circuit. We are very careful in this book to distinguish between signal names, which are always printed in black, and logic expressions, which are always printed in color when they are written near the corresponding signal lines.
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Figure 5-5 Logic symbols: (a) AND, OR, and a larger-scale logic element; (b) the same elements with active-low inputs and outputs.
5.1.4 Active Levels for Pins When we draw the outline of an AND or OR symbol, or a rectangle representing a larger-scale logic element, we think of the given logic function as occurring inside that symbolic outline. In Figure 5-5(a), we show the logic symbols for an AND and OR gate and for a larger-scale element with an ENABLE input. The AND and OR gates have active-high inputsthey require 1s on the input to assert their outputs. Likewise, the larger-scale element has an active-high ENABLE input, which must be 1 to enable the element to do its thing. In (b), we show the same logic elements with active-low input and output pins. Exactly the same logic functions are performed inside the symbolic outlines, but the inversion bubbles indicate that 0s must now be applied to the input pins to activate the logic functions, and that the outputs are 0 when they are doing their thing. Thus, active levels may be associated with the input and output pins of gates and larger-scale logic elements. We use an inversion bubble to indicate an active-low pin and the absence of a bubble to indicate an active-high pin. For example, the AND gate in Figure 5-6(a) performs the logical AND of two activehigh inputs and produces an active-high output: if both inputs are asserted (1), the output is asserted (1). The NAND gate in (b) also performs the AND function, but it produces an active-low output. Even a NOR or OR gate can be construed to perform the AND function using active-low inputs and outputs, as shown in (c) and (d). All four gates in the figure can be said to perform the same function: the output of each gate is asserted if both of its inputs are asserted. Figure 5-7 shows the same idea for the OR function: The output of each gate is asserted if either of its inputs is asserted.
Figure 5-6 Four ways of obtaining an AND function: (a) AND gate (74x08); (b) NAND gate (74x00); (c) NOR gate (74x02); (d) OR gate (74x32).
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DO ENABLE MY ... THING ... ... ... ... DO ENABLE MY ... THING ... ... ... ... (a) (b) (a) (b) (c) (d)
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(a) (b) (c) (d) (a) (b) (c) (d)
Figure 5-7 Four ways of obtaining an OR function: (a) OR gate (74x32); (b) NOR gate (74x02); (c) N AND gate (74x00); (d) AND gate (74x08).
Figure 5-8 Alternate logic symbols: (a, b) inverters; (c, d) noninverting buffers.
Sometimes a noninverting buffer is used simply to boost the fanout of a logic signal without changing its function. Figure 5-8 shows the possible logic symbols for both inverters and noninverting buffers. In terms of active levels, all of the symbols perform exactly the same function: Each asserts its output signal if and only if its input is asserted.
5.1.5 Bubble-to-Bubble Logic Design Experienced logic circuit designers formulate their circuits in terms of the logic functions performed inside the symbolic outlines. Whether youre designing with discrete gates or in an HDL like ABEL or VHDL, its easiest to think of logic signals and their interactions using active-high names. However, once youre ready to realize your circuit, you may have to deal with active-low signals due to the requirements of the environment. When you design with discrete gates, either at board or ASIC level, a key requirement is often speed. As we showed in Section 3.3.6, inverting gates are typically faster than noninverting ones, so theres often a significant performance payoff in carrying some signals in active-low form. When you design with larger-scale elements, many of them may be offthe-shelf chips or other existing components that already have some inputs and outputs fixed in active-low form. The reasons that they use active-low signals may range from performance improvement to years of tradition, but in any case, you still have to deal with it.
NAME THAT SIGNAL!
Although it is absolutely necessary to name only a circuits main inputs and outputs, most logic designers find it useful to name internal signals as well. During circuit debugging, its nice to have a name to use when pointing to an internal signal thats behaving strangely. Most computer-aided design systems automatically generate labels for unnamed signals, but a user-chosen name is preferable to a computer-generated one like XSIG1057 .
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READY_L REQUEST_L
Figure 5-9 Many ways to GO: (a) active-high inputs and output; (b) active-high inputs, active-low output; (c) active-low inputs, active-high output; (d) active-low inputs and outputs.
Bubble-to-bubble logic design is the practice of choosing logic symbols and signal names, including active-level designators, that make the function of a logic circuit easier to understand. Usually, this means choosing signal names and gate types and symbols so that most of the inversion bubbles cancel out and the logic diagram can be analyzed as if all of the signals were active high. For example, suppose we need to produce a signal that tells a device to GO when we are READY and we get a REQUEST. Clearly from the problem statement, an AND function is required; in switching algebra, we would write GO = READY REQUEST. However, we can use different gates to perform the AND function, depending on the active level required for the GO signal and the active levels of the available input signals. Figure 5-9(a) shows the simplest case, where GO must be active-high and the available input signals are also active-high; we use an AND gate. If, on the other hand, the device that were controlling requires an active-low GO_L signal, we can use a NAND gate as shown in (b). If the available input signals are activelow, we can use a NOR or OR gate as shown in (c) and (d). The active levels of available signals dont always match the active levels of available gates. For example, suppose we are given input signals READY_L (active-low) and R EQUEST (active-high). Figure 5-10 shows two different ways to generate GO using an inverter to generate the active level needed for the AND function. The second way is generally preferred, since inverting gates like NOR are generally faster than noninverting ones like AND. We drew the inverter differently in each case to make the outputs active level match its signal name.
Figure 5-10 Two more ways to GO, with mixed input levels: (a) with an AND gate; (b) with a NOR gate.
READY_L REQUEST READY GO READY_L
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GO GO_L (a) (b) GO READY_L REQUEST_L GO_L (c) (d) REQUEST REQUEST_L (b) (a)
bubble-to-bubble logic design
GO
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A SEL
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DATA B (b) A ASEL ADATA_L BDATA_L DATA BSEL = ASEL A + ASEL B
B
F igure 5-11 A 2-input multiplexer (youre not supposed to know what that is yet): (a) cryptic logic diagram; (b) proper logic diagram using active-level designators and alternate logic symbols.
To understand the benefits of bubble-to-bubble logic design, consider the circuit in Figure 5-11(a). What does it do? In Section 4.2 we showed several ways to analyze such a circuit, and we could certainly obtain a logic expression for the DATA output using these techniques. However, when the circuit is redrawn in Figure 5-11(b), the output function can be read directly from the logic diagram, as follows. The DATA output is asserted when either ADATA_L or BDATA_L is asserted. If ASEL is asserted, then ADATA_L is asserted if and only if A is asserted; that is, ADATA_L is a copy of A. If ASEL is negated, BSEL is asserted and BDATA_L is a copy of B. In other words, DATA is a copy of A if ASEL is asserted, and DATA is a copy of B if ASEL is negated. Even though there are five inversion bubbles in the logic diagram, we mentally had to perform only one negation to understand the circuitthat BSEL is asserted if ASEL is not asserted. If we wish, we can write an algebraic expression for the DATA output. We use the technique of Section 4.2, simply propagating expressions through gates toward the output. In doing so, we can ignore pairs of inversion bubbles that cancel, and directly write the expression shown in color in the figure.
Figure 5-12 Another properly drawn logic diagram.
GO = READY_L REQUEST_L = READY REQUEST
ENABLE_L = (TEST + (READY REQUEST) ) ENABLE = TEST + (READY REQUEST)
TEST
LOCK_L
HALT = LOCK + (READY REQUEST)
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Another example is shown in Figure 5-12. Reading directly from the logic diagram, we see that ENABLE_L is asserted if READY_L and REQUEST_L are asserted or if TEST is asserted. The HALT output is asserted if READY_L and REQUEST_L are not both asserted or if LOCK_L is asserted. Once again, this example has only one place where a gate inputs active level does not match the input signal level, and this is reflected in the verbal description of the circuit. We can, if we wish, write algebraic equations for the ENABLE_L and HALT outputs. As we propagate expressions through gates towards the output, we obtain expressions like READY_L REQUEST. However, we can use our active-level naming convention to simplify terms like READY_L. The circuit contains no signal with the name READY; but if it did, it would satisfy the relationship READY = READY_L according to the naming convention. This allows us to write the ENABLE_L and HALT equations as shown. Complementing both sides of the ENABLE_L equation, we obtain an equation that describes a hypothetical active-high ENABLE output in terms of hypothetical active-high inputs. Well see more examples of bubble-to-bubble logic design in this and later chapters, especially as we begin to use larger-scale logic elements. 5.1.6 Drawing Layout Logic diagrams and schematics should be drawn with gates in their normal orientation with inputs on the left and outputs on the right. The logic symbols for larger-scale logic elements are also normally drawn with inputs on the left and outputs on the right. A complete schematic page should be drawn with system inputs on the left and outputs on the right, and the general flow of signals should be from left to right. If an input or output appears in the middle of a page, it should be extended to the left or right edge, respectively. In this way, a reader can find all inputs and outputs by looking at the edges of the page only. All signal paths on the page
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BUBBLE-TOBUBBLE LOGIC DESIGN RULES The following rules are useful for performing bubble-to-bubble logic design:
The signal name on a devices output should have the same active level as the
devices output pin, that is, active-low if the device symbol has an inversion bubble on the output pin, active-high if not.
If the active level of an input signal is the same as that of the input pin to which
it is connected, then the logic function inside the symbolic outline is activated when the signal is asserted. This is the most common case in a logic diagram. which it is connected, then the logic function inside the symbolic outline is activated when the signal is negated. This case should be avoided whenever possible because it forces us to keep track mentally of a logical negation to understand the circuit.
If the active level of an input signal is the opposite of that of the input pin to
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Figure 5-13 Line crossings and connections.
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Hand drawn Machine drawn not allowed connection crossing connection
should be connected when possible; paths may be broken if the drawing gets crowded, but breaks should be flagged in both directions, as described later. Sometimes block diagrams are drawn without crossing lines for a neater appearance, but this is never done in logic diagrams. Instead, lines are allowed to cross and connections are indicated clearly with a dot. Still, some computeraided design systems (and some designers) cant draw legible connection dots. To distinguish between crossing lines and connected lines, they adopt the convention that only T-type connections are allowed, as shown in Figure 5-13. This is a good convention to follow in any case. Schematics that fit on a single page are the easiest to work with. The largest practical paper size for a schematic might be E-size (3444). Although its drawing capacity is great, such a large paper size is unwieldy to work with. The best compromise of drawing capacity and practicality is B-size (1117). It can be easily folded for storage and quick reference in standard 3-ring notebooks, and it can be copied on most office copiers. Regardless of paper size, schematics
Figure 5-14 Flat schematic structure.
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come out best when the page is used in landscape format, that is, with its long dimension oriented from left to right, the direction of most signal flow. Schematics that dont fit on a single page should be broken up into individual pages in a way that minimizes the connections (and confusion) between pages. They may also use a coordinate system, like that of a road map, to flag the sources and destinations of signals that travel from one page to another. An outgoing signal should have flags referring to all of the destinations of that signal, while an incoming signal should have a flag referring to the source only. That is, an incoming signal should be flagged to the place where it is generated, not to a place somewhere in the middle of a chain of destinations that use the signal. A multiple-page schematic usually has a flat structure. As shown in Figure 5-14, each page is carved out from the complete schematic and can connect to any other page as if all the pages were on one large sheet. However, much like programs, schematics can also be constructed hierarchically, as illustrated in Figure 5-15. In this approach, the top-level schematic is just a single page that may take the place of a block diagram. Typically, the top-level schematic conPage 1
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flat schematic structure
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Figure 5-15 Hierarchical schematic structure.
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tains no gates or other logic elements; it only shows blocks corresponding to the major subsystems, and their interconnections. The blocks or subsystems are turn on lower-level pages, which may contain ordinary gate-level descriptions, or may themselves use blocks defined in lower-level hierarchies. If a particular lower-level hierarchy needs to be used more than once, it may be reused (or called, in the programming sense) multiple times by the higher-level pages. Most computer-aided logic design systems support both flat and hierarchical schematics. Proper signal naming is very important in both styles, since there are a number of common errors that can occur: Like any other program, a schematic-entry program does what you say, not what you mean. If you use slightly different names for what you intend to be the same signal on different pages, they wont be connected. Conversely, if you inadvertently use the same name for different signals on different pages of a flat schematic, many programs will dutifully connect them together, even if you havent connected them with an off-page flag. (In a hierarchical schematic, reusing a name at different places in the hierarchy is generally OK, because the program qualifies each name with its position in the hierarchy.) In a hierarchical schematic, you have to be careful in naming the external interface signals on pages in the lower levels of the hierarchy. These are the names that will appear inside the blocks corresponding to these pages when they are used at higher levels of the hierarchy. Its very easy to transpose signal names or use a name with the wrong active level, yielding incorrect results when the block is used. This is not usually a naming problem, but all schematic programs seem to have quirks in which signals that appear to be connected are not. Using the T convention in Figure 5-13 can help minimize this problem. Fortunately, most schematic programs have error-checking facilities that can catch many of these errors, for example, by searching for signal names that have no inputs, no outputs, or multiple outputs associated with them. But most logic designers learn the importance of careful, manual schematic doublechecking only through the bitter experience of building a printed-circuit board or an ASIC based on a schematic containing some dumb error.
5.1.7 Buses As defined previously, a bus is a collection of two or more related signal lines. For example, a microprocessor system might have an address bus with 16 lines, ADDR0ADDR15, and a data bus with 8 lines, DATA0DATA7. The signal names in a bus are not necessarily related or ordered as in these first examples. For example, a microprocessor system might have a control bus containing five signals, ALE, MIO, R D_L, WR_L, and RDY.
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Logic diagrams use special notation for buses in order to reduce the amount of drawing and to improve readability. As shown in Figure 5-16, a bus has its own descriptive name, such as ADDR[15:0], DATA[7:0], or CONTROL. A bus name may use brackets and a colon to denote a range. Buses are drawn with thicker lines than ordinary signals. Individual signals are put into or pulled out of the bus by connecting an ordinary signal line to the bus and writing the signal name. Often a special connection dot is also used, as in the example. A computer-aided design system keeps track of the individual signals in a bus. When it actually comes time to build a circuit from the schematic, signal lines in a bus are treated just as though they had all been drawn individually. The symbols at the right-hand edge of Figure 5-16 are interpage signal flags. They indicate that LA goes out to page 2, DB is bidirectional and connects to page 2, and CONTROL is bidirectional and connects to pages 2 and 3.
Microprocessor
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
RDY
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A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LA[15:0] 2
ADDR15 LA15 LA14 LA13 LA12 LA11 LA10 LA7 LA8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
Figure 5-16 Examples of buses.
ADDR[15:0]
ALE
ALE
ALE
D7 D6 D5 D4 D3 D2 D1 D0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
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Figure 5-17 Schematic diagram for a circuit using a 74HCT00.
IC type
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5.1.8 Additional Schematic Information Complete schematic diagrams indicate IC types, reference designators, and pin numbers, as in Figure 5-17. The IC type is a part number identifying the integrated circuit that performs a given logic function. For example, a 2-input NAND gate might be identified as a 74HCT00 or a 74LS00. In addition to the logic function, the IC type identifies the devices logic family and speed. The reference designator for an IC identifies a particular instance of that IC type installed in the system. In conjunction with the systems mechanical documentation, the reference designator allows a particular IC to be located during assembly, test, and maintenance of the system. Traditionally, reference designators for ICs begin with the letter U (for unit). Once a particular IC is located, pin numbers are used to locate individual logic signals on its pins. The pin numbers are written near the corresponding inputs and outputs of the standard logic symbol, as shown in Figure 5-17. In the rest of this book, just to make you comfortable with properly drawn schematics, well include reference designators and pin numbers for all of the logic circuit examples that use SSI and MSI parts. Figure 5-18 shows the pinouts of many different SSI ICs that are used in examples throughout this book. Some special graphic elements appear in a few of the symbols: Symbols for the 74x14 Schmitt-trigger inverter has a special element inside the symbol to indicate hysteresis. Symbols for the 74x03 quad NAND and the 74x266 quad Exclusive NOR have a special element to indicate an open-drain or open-collector output.
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74x00 74x02 74x03
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F igure 5-18 Pinouts for SSI ICs in standard dual-inline packages.
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3 2 3 1 1 2 3 1 2 1 2 3 3 4 6 5 6 4 4 5 6 4 5 5 6 6 8 8 9 10 9 8 9 8 9 8 10 10 11 10 11 11 12 13 12 13 11 12 13 13 12 11
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5.2 Circuit Timing
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When you prepare a schematic diagram for a board-level design using a schematic drawing program, the program automatically provides the pin numbers for the devices that you select from its component library. Note that an ICs pin numbers may differ depending on package type, so you have to be careful to select the right version of the component from the library. Figure 5-18 shows the pin numbers that are used in a dual-inline package, the type of package that you would use in a digital design laboratory course or in a lowdensity, thru-hole commercial printed-circuit board.
Timing is everythingin investing, in comedy, and yes, in digital design. As we studied in Section 3.6, the outputs of real circuits take time to react to their inputs, and many of todays circuits and systems are so fast that even the speedof-light delay in propagating an output signal to an input on the other side of a board or chip is significant. Most digital systems are sequential circuits that operate step-by-step under the control of a periodic clock signal, and the speed of the clock is limited by the worst-case time that it takes for the operations in one step to complete. Thus, digital designers need to be keenly aware of timing behavior in order to build fast circuits that operate correctly under all conditions. The last several years have seen great advances in the number and quality of CAD tools for analyzing circuit timing. Still, quite often the greatest challenge in completing a board-level or especially an ASIC design is achieving the required timing performance. In this section, we start with the basics, so you can understand what the tools are doing when you use them, and so you can figure out how to fix your circuits when their timing isnt quite making it.
5.2.1 Timing Diagrams A timing diagram illustrates the logical behavior of signals in a digital circuit as a function of time. Timing diagrams are an important part of the documentation of any digital system. They can be used both to explain the timing relationships among signals within a system, and to define the timing requirements of external signals that are applied to the system. Figure 5-19(a) is the block diagram of a simple combinational circuit with two inputs and two outputs. Assuming that the ENB input is held at a constant value, (b) shows the delay of the two outputs with respect to the GO input. In each waveform, the upper line represents a logic 1, and the lower line a logic 0. Signal transitions are drawn as slanted lines to remind us that they do not occur in zero time in real circuits. (Also, slanted lines look nicer than vertical ones.) Arrows are sometimes drawn, especially in complex timing diagrams, to show causalitywhich input transitions cause which output transitions. In any case, the most important information provided by a timing diagram is a specification of the delay between transitions.
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(a)
ENB
Figure 5-19 Timing diagrams for a combinational circuit: (a) block diagram of circuit; (b) causality and propagation delay; (c) minimum and maximum delays.
Different paths through a circuit may have different delays. For example, Figure 5-19(b) shows that the delay from GO to READY is shorter than the delay from GO to DAT. Similarly, the delays from the ENB input to the outputs may vary, and could be shown in another timing diagram. And, as well discuss later, the delay through any given path may vary depending on whether the output is changing from LOW to HIGH or from HIGH to LOW (this phenomenon is not shown in the figure). Delay in a real circuit is normally measured between the centerpoints of transitions, so the delays in a timing diagram are marked this way. A single timing diagram may contain many different delay specifications. Each different delay is marked with a different identifier, such as tRDY and tDAT in the figure. In large timing diagrams, the delay identifiers are usually numbered for easier reference (e.g., t1, t2 , , t42 ). In either case, the timing diagram is normally accompanied by a timing table that specifies each delay amount and the conditions under which it applies. Since the delays of real digital components can vary depending on voltage, temperature, and manufacturing parameters, delay is seldom specified as a single number. Instead, a timing table may specify a range of values by giving minimum, typical, and maximum values for each delay. The idea of a range of delays is sometimes carried over into the timing diagram itself by showing the transitions to occur at uncertain times, as in Figure 5-19(c).
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GO READY tRDY tRDY DAT tDAT tDAT (c) GO GO READY DAT READY tRDYmin tRDYmax DAT tDATmin tDATmax
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Figure 5-20 Timing diagrams for data signals: (a) certain and uncertain transitions; (b) sequence of values on an 8-bit bus.
propagation delay
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(a) WRITE_L DATAIN must be stable DATAOUT old new data tsetup tOUTmin thold tOUTmax (b) CLEAR COUNT STEP[7:0] FF 00 01 02 03
For some signals, the timing diagram neednt show whether the signal changes from 1 to 0 or from 0 to 1 at a particular time, only that a transition occurs then. Any signal that carries a bit of data has this characteristicthe actual value of the data bit varies according to circumstances but, regardless of value, the bit is transferred, stored, or processed at a particular time relative to control signals in the system. Figure 5-20(a) is a timing diagram that illustrates this concept. The data signal is normally at a steady 0 or 1 value, and transitions occur only at the times indicated. The idea of an uncertain delay time can also be used with data signals, as shown for the DATAOUT signal. Quite often in digital systems, a group of data signals in a bus is processed by identical circuits. In this case, all signals in the bus have the same timing, and can be represented by a single line in the timing diagram and corresponding specifications in the timing table. If the bus bits are known to take on a particular combination at a particular time, this is sometimes shown in the timing diagram using binary, octal, or hexadecimal numbers, as in Figure 5-20(b).
5.2.2 Propagation Delay In Section 3.6.2, we formally defined the propagation delay of a signal path as the time that it takes for a change at the input of the path to produce a change at the output of the path. A combinational circuit with many inputs and outputs has many different paths, and each one may have a different propagation delay. Also, the propagation delay when the output changes from LOW to HIGH (tpLH) may be different from the delay when it changes from HIGH to LOW (tpHL). The manufacturer of a combinational-logic IC normally specifies all of these different propagation delays, or at least the delays that would be of interest
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in typical applications. A logic designer who combines ICs in a larger circuit uses the individual device specifications to analyze the overall circuit timing. The delay of a path through the overall circuit is the sum of the delays through subpaths in the individual devices. 5.2.3 Timing Specifications The timing specification for a device may give minimum, typical, and maximum values for each propagation-delay path and transition direction:
Maximum . This specification is the one that is most often used by experienced designers, since a path never has a propagation delay longer than the maximum. However, the definition of never varies among logic families and manufacturers. For example, maximum propagation delays of 74LS and 74S TTL devices are specified with VCC = 5 V, TA = 25C, and almost no capacitive load. If the voltage or temperature is different, or if the capacitive load is more than 15 pF, the delay may be longer. On the other hand, a maximum propagation delay is specified for 74AC and 74ACT devices over the full operating voltage and temperature range, and with a heavier capacitive load of 50 pF. Typical. This specification is the one that is most often used by designers who dont expect to be around when their product leaves the friendly environment of the engineering lab and is shipped to customers. The typical delay is what you see from a device that was manufactured on a good day and is operating under near-ideal conditions. Minimum. This is the smallest propagation delay that a path will ever exhibit. Most well-designed circuits dont depend on this number; that is, they will work properly even if the delay is zero. Thats good because manufacturers dont specify minimum delay in most moderate-speed logic families, including 74LS and 74S TTL. However, in high-speed families, including ECL and 74AC and 74ACT CMOS, a nonzero minimum delay is specified to help the designer ensure that timing requirements of latches and flip-flops discussed in \secref{llff}, are met. Table 5-2 lists the typical and maximum delays of several 74-series CMOS and TTL gates. Table 5-3 does the same thing for most of the CMOS and TTL MSI parts that are introduced later in this chapter.
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maximum delay typical delay minimum delay HOW TYPICAL IS TYPICAL? Most ICs, perhaps 99%, really are manufactured on good days and exhibit delays near the typical specifications. However, if you design a system that works only if all of its 100 ICs meet the typical timing specs, probability theory suggests that 63% (1 .99 100) of the systems wont work.But see the next box.... Copying Prohibited
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A COROLLARY OF MURPHYS LAW
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Ta b l e 5 - 2 Propagation delay in nanoseconds of selected 5-V CMOS and TTL SSI parts.
74HCT 74AHCT 74LS Typical Maximum
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Murphys law states, If something can go wrong, it will. A corollary to this is, If you want something to go wrong, it wont. In the boxed example on the previous page, you might think that you have a 63% chance of detecting the potential timing problems in the engineering lab. The problems arent spread out evenly, though, since all ICs from a given batch tend to behave about the same. Murphys Corollary says that all of the engineering prototypes will be built with ICs from the same, good batches. Therefore, everything works fine for a while, just long enough for the system to get into volume production and for everyone to become complacent and self-congratulatory. Then, unbeknownst to the production department, a slow batch of some IC type arrives from a supplier and gets used in every system that is built, so that nothing works. The production engineers scurry around trying to analyze the problem (not easy, because the designer is long gone and didnt bother to write a circuit description), and in the meantime the company loses big bucks because it is unable to ship its product.
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Ta b l e 5 - 3 Propagation delay in nanoseconds of selected CMOS and TTL MSI parts.
74HCT 74AHCT / FCT 74LS Typical Maximum
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any select any select G2A, G2B
G1
any select any select enable any select any select any data any data enable enable any select any data enable select any data enable any Gi, Pi any Gi, Pi any Pi
C0
output (2) output (3) output output output (2) output (3) output
Y Y Y Y Y Y
output output output output output output
any input any input
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any Ai, Bi any Ai, Bi
CIN
any Ai, Bi any Ai, Bi any Ai, Bi any select any select any Pi any Qi any Pi any Qi
C13 G P C13 EVEN ODD any Si any Si C4 C4 any Fi G P any Fi any Fi G, P PEQQ PEQQ PGTQ PGTQ
23 23 22 22 14 14 11 17 18 16 15 12 15 14 12 11 15 12 12 13 13 11 17 18 19 22 21 19 20
45 45 42 42 43 43 43 51 54 48 45 36 45 43 43 34 46 38 38 41 41 35 50 53 56 66 61 58 60
8.1 / 5 8.1 / 5 7.5 / 4 7.1 / 4 6.5 / 5 6.5 / 5 5.9 / 5 -/5 -/5 -/4 -/4 -/4 -/4 -/5 -/4 -/4 6.8 / 7 5.6 / 4 7.1 / 7
13 / 9 13 / 9 12 / 8 11.5 / 8 10.5 / 9 10.5 / 9 9.5 / 9 -/9 -/9 -/7 -/7 -/7 -/7 -/9 -/7 -/7 11.5 / 10.5 9.5 / 6 12.0 / 10.5
-/6 -/6
- / 10 - / 10
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- / 11 - / 11 - / 14 - / 14
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18 20 20 13 22 25 21 18 20 16 12 20 18 25 17 21 18 9 14 4.5 7 6.5 7 29 31 15 15 11 12 14 21 33 15 34 32 15 15 15 19
20 27 18 26 20 29 24 43 23 32 21 42 24 29 15 24 23 14 21 7 7.5 6.5 10 50 35 24 24 17 17 27 30 23 30 53 47 25 25 30 30
41 39 32 38 33 38 32 30 32 26 20 32 30 38 26 32 27 14 23 7 10.5 10 10.5 45 50 24 24 22 17 21 33 33 23 51 48 25 25 30 30
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If the minimum delay of an IC is not specified, a conservative designer assumes that it has a minimum delay of zero. Some circuits wont work if the propagation delay actually goes to zero, but the cost of modifying a circuit to handle the zero-delay case may be unreasonable, especially since this case is expected never to occur. To obtain a design that always works under reasonable conditions, logic designers often estimate that ICs have minimum delays of one-fourth to one-third of their published typical delays. Copyright 1999 by John F. Wakerly
All inputs of an SSI gate have the same propagation delay to the output. Note that TTL gates usually have different delays for LOW-to-HIGH and HIGHto-LOW transitions (tpLH and tpHL), but CMOS gates usually do not. CMOS gates have a more symmetrical output driving capability, so any difference between the two cases is usually not worth noting. The delay from an input transition to the corresponding output transition depends on the internal path taken by the changing signal, and in larger circuits the path may be different for different input combinations. For example, the 74LS86 2-input XOR gate is constructed from four NAND gates as shown in Figure 5-70 on page 372, and has two different-length paths from either input to the output. If one input is LOW, and the other is changed, the change propagates through two NAND gates, and we observe the first set of delays shown in Table 5-2. If one input is HIGH, and the other is changed, the change propagates through three NAND gates internally, and we observe the second set of delays. Similar behavior is exhibited by the 74LS138 and 74LS139 in Table 5-3. However, the corresponding CMOS parts do not show these differences; they are small enough to be ignored.
5.2.4 Timing Analysis To accurately analyze the timing of a circuit containing multiple SSI and MSI devices, a designer may have to study its logical behavior in excruciating detail. For example, when TTL inverting gates (NAND, NOR, etc.) are placed in series, a LOW-to-HIGH change at one gates output causes a HIGH -to-LOW change at the next ones, and so the differences between tpLH and tpHL tend to average out. On the other hand, when noninverting gates (AND, OR, etc.) are placed in series, a transition causes all outputs to change in the same direction, and so the gap between tpLH and tpHL tends to widen. As a student, youll have the privilege of carrying out this sort of analysis in Drills 5.85.13. The analysis gets more complicated if there are MSI devices in the delay path, or if there are multiple paths from a given input signal to a given output signal. Thus, in large circuits, analysis of all of the different delay paths and transition directions can be very complex.
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To permit a simplified worst-case analysis, designers often use a single worst-case delay specification that is the maximum of tpLH and tpHL specifications. The worst-case delay through a circuit is then computed as the sum of the worst-case delays through the individual components, independent of the transition direction and other circuit conditions. This may give an overly pessimistic view of the overall circuit delay, but it saves design time and its guaranteed to work.
5.2.5 Timing Analysis Tools Sophisticated CAD tools for logic design make timing analysis even easier. Their component libraries typically contain not only the logic symbols and functional models for various logic elements, but also their timing models. A simulator allows you to apply input sequences and observe how and when outputs are produced in response. You typically can control whether minimum, typical, maximum, or some combination of delay values are used. Even with a simulator, youre not completely off the hook. Its usually up the designer to supply the input sequences for which the simulator should produce outputs. Thus, youll need to have a good feel for what to look for and how to stimulate your circuit to produce and observe the worst-case delays. Some timing analysis programs can automatically find all possible delay paths in a circuit, and print out a sorted list of them, starting with the slowest. These results may be overly pessimistic, however, as some paths may actually not be used in normal operations of the circuit; the designer must still use some intelligence to interpret the results properly.
5.3 Combinational PLDs
5.3.1 Programmable Logic Arrays Historically, the first PLDs were programmable logic arrays (PLAs). A PLA is a combinational, two-level AND-OR device that can be programmed to realize any sum-of-products logic expression, subject to the size limitations of the device. Limitations are the number of inputs (n), the number of outputs (m), and the number of product terms (p).
We might describe such a device as an n m PLA with p product terms. In general, p is far less than the number of n-variable minterms (2n). Thus, a PLA cannot perform arbitrary n-input, m-output logic functions; its usefulness is limited to functions that can be expressed in sum-of-products form using p or fewer product terms. An n m PLA with p product terms contains p 2n-input AND gates and m p-input OR gates. Figure 5-21 shows a small PLA with four inputs, six AND
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worst-case delay programmable logic array (PLA) inputs outputs product terms
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P1 P2 P3 P4 P5 P6
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Figure 5-21 A 4 3 PLA with six product terms.
gates, and three OR gates and outputs. Each input is connected to a buffer that produces both a true and a complemented version of the signal for use within the array. Potential connections in the array are indicated by Xs; the device is programmed by establishing only the connections that are actually needed. The needed connections are made by fuses, which are actual fusible links or nonvolatile memory cells, depending on technology as we explain in Sections 5.3.4 and 5.3.5. Thus, each AND gates inputs can be any subset of the primary input signals and their complements. Similarly, each OR gates inputs can be any subset of the AND-gate outputs. As shown in Figure 5-22, a more compact diagram can be used to represent a PLA. Moreover, the layout of this diagram more closely resembles the actual internal layout of a PLA chip (e.g., Figure 5-28 on page 308).
Figure 5-22 Compact representation of a 4 3 PLA with six product terms.
I1
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The PLA in Figure 5-22 can perform any three 4-input combinational logic functions that can be written as sums of products using a total of six or fewer distinct product terms, for example: O1 = I1 I2 + I1 I2 I3 I4 O2 = I1 I3 + I1 I3 I4 + I2 O3 = I1 I2 + I1 I3 + I1 I2 I4
These equations have a total of eight product terms, but the first two terms in the O3 equation are the same as the first terms in the O1 and O2 equations. The programmed connection pattern in Figure 5-23 matches these logic equations. Sometimes a PLA output must be programmed to be a constant 1 or a constant 0. Thats no problem, as shown in Figure 5-24. Product term P1 is always 1 because its product line is connected to no inputs and is therefore always pulled HIGH ; this constant-1 term drives the O1 output. No product term drives the O2 output, which is therefore always 0. Another method of obtaining a constant-0 output is shown for O3. Product term P2 is connected to each input variable and its complement; therefore, its always 0 (X X = 0).
I1 I2 I3 I4
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Figure 5-23 A 4 3 PLA programmed with a set of three logic equations.
P1 P2 P3 P4 P5 P6 O1 O2 O3
PLA constant outputs
Figure 5-24 A 4 3 PLA programmed to produce constant 0 and 1 outputs.
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AN UNLIKELY GLITCH Theoretically, if all of the input variables in Figure 5-24 change simultaneously, the output of product term P2 could have a brief 0-1-0 glitch. This is highly unlikely in typical applications, and is impossible if one input happens to be unused and is connected to a constant logic signal. FRIENDS AND FOES PAL is a registered trademark of Advanced Micro Devices, Inc. Like other trademarks, it should be used only as an adjective. Use it as a noun or without a trademark notice at your own peril (as I learned in a letter from AMDs lawyers in February 1989). To get around AMDs trademark, I suggest that you use a descriptive name that is more indicative of the devices internal structure: a fixed-OR element (FOE). Copyright 1999 by John F. Wakerly
Our example PLA has too few inputs, outputs, and AND gates (product terms) to be very useful. An n-input PLA could conceivably use as many as 2n product terms, to realize all possible n-variable minterms. The actual number of product terms in typical commercial PLAs is far fewer, on the order of 4 to 16 per output, regardless of the value of n. The Signetics 82S100 was a typical example of the PLAs that were introduced in the mid-1970s. It had 16 inputs, 48 AND gates, and 8 outputs. Thus, it had 2 16 48 = 1536 fuses in the AND array and 8 48 = 384 in the OR array. Off-the-shelf PLAs like the 82S100 have since been supplanted by PALs, CPLDs, and FPGAs, but custom PLAs are often synthesized to perform complex combinational logic within a larger ASIC.
5.3.2 Programmable Array Logic Devices A special case of a PLA, and todays most commonly used type of PLD, is the programmable array logic (PAL) device. Unlike a PLA, in which both the AND and OR arrays are programmable, a PAL device has a fixed OR array. The first PAL devices used TTL-compatible bipolar technology and were introduced in the late 1970s. Key innovations in the first PAL devices, besides the introduction of a catchy acronym, were the use of a fixed OR array and bidirectional input/output pins. These ideas are well illustrated by the PAL16L8 , shown in Figures 5-25 and 5-26 and one of todays most commonly used combinational PLD structures. Its programmable AND array has 64 rows and 32 columns, identified for programming purposes by the small numbers in the figure, and 64 32 = 2048 fuses. Each of the 64 AND gates in the array has 32 inputs, accommodating 16 variables and their complements; hence, the 16 in PAL16L8.
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Figure 5-25 Logic diagram of the PAL16L8.
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Figure 5-26 Traditional logic symbol for the PAL16L8.
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Eight AND gates are associated with each output pin of the PAL16L8. Seven of them provide inputs to a fixed 7-input OR gate. The eighth, which we call the output-enable gate, is connected to the three-state enable input of the output buffer; the buffer is enabled only when the output-enable gate has a 1 output. Thus, an output of the PAL16L8 can perform only logic functions that can be written as sums of seven or fewer product terms. Each product term can be a function of any or all 16 inputs, but only seven such product terms are available. Although the PAL16L8 has up to 16 inputs and up to 8 outputs, it is housed in a dual in-line package with only 20 pins, including two for power and ground (the corner pins, 10 and 20). This magic is the result of six bidirectional pins (1318) that may be used as inputs or outputs or both. This and other differences between the PAL16L8 and a PLA structure are summarized below: The PAL16L8 has a fixed OR array, with seven AND gates permanently connected to each OR gate. AND-gate outputs cannot be shared; if a product term is needed by two OR gates, it must be generated twice. Each output of the PAL16L8 has an individual three-state output enable signal, controlled by a dedicated AND gate (the output-enable gate). Thus, outputs may be programmed as always enabled, always disabled, or enabled by a product term involving the device inputs.
HOW USEFUL ARE SEVEN PRODUCT TERMS?
The worst-case logic function for two-level AND-OR design is an n-input XOR (parity) function, which requires 2n1 product terms. However, less perverse functions with more than seven product terms of a PAL16L8 can often be built by decomposing them into a 4-level structure ( AND-OR-AND-OR) that can be realized with two passes through the AND-OR array. Unfortunately, besides using up PLD outputs for the first-pass terms, this doubles the delay, since a first-pass input must pass through the PLD twice to propagate to the output.
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COMBINATIONAL, NOT COMBINATORIAL!
There is an inverter between the output of each OR gate and the external pin of the device. Six of the output pins, called I/O pins, may also be used as inputs. This provides many possibilities for using each I/O pin, depending on how the device is programmed:
The PAL20L8 is another combinational PLD similar to the PAL16L8, except that its package has four more input-only pins and each of its AND gates has eight more inputs to accommodate them. Its output structure is the same as the PAL16L8s. 5.3.3 Generic Array Logic Devices In \chapref{SeqPLDs} well introduce sequential PLDs, programmable logic devices that provide flip-flops at some or all OR-gate outputs. These devices can be programmed to perform a variety of useful sequential-circuit functions.
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A step backwards in MMIs introduction of PAL devices was their popularization of the word combinatorial to describe combinational circuits. Combinational circuits have no memorytheir output at any time depends on the current input combination. For well-rounded computer engineers, the word combinatorial should conjure up vivid images of binomial coefficients, problem-solving complexity, and computer-science-great Donald Knuth. I/O pin
If an I/O pins output-control gate produces a constant 0, then the output is always disabled and the pin is used strictly as an input. If the input signal on an I/O pin is not used by any gates in the AND array, then the pin may be used strictly as an output. Depending on the programming of the output-enable gate, the output may always be enabled, or it may be enabled only for certain input conditions. If an I/O pins output-control gate produces a constant 1, then the output is always enabled, but the pin may still be used as an input too. In this way, outputs can be used to generate first-pass helper terms for logic functions that cannot be performed in a single pass with the limited number of AND terms available for a single output. Well show an example of this case on page 325. In another case with an I/O pin always output-enabled, the output may be used as an input to AND gates that affect the very same output. That is, we can embed a feedback sequential circuit in a PAL16L8. Well discuss this case in \secref{palatch}.
PAL16L8
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generic array logic GAL device GAL16V8
GAL16V8C
output polarity
PALCE16V8 GAL20V8 PALCE20V8
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COMBINATIONAL PLD SPEED The speed of a combinational PLD is usually stated as a single number giving the propagation delay tPD from any input to any output for either direction of transition. PLDs are available in a variety of speed grades; commonly used parts run at 10 ns. In 1998, the fastest available combinational PLDs included a bipolar PAL16L8 at 5 ns and a 3.3-V CMOS GAL22LV10 at 3.5 ns. LEGAL NOTICE GAL is a trademark of Lattice Semiconductor, Hillsboro, OR 97124. Copyright 1999 by John F. Wakerly
One type of sequential PLD, first introduced by Lattice Semiconductor, is called generic array logic or a GAL device, and is particularly popular. A single GAL device type, the G AL16V8, can be configured (via programming and a corresponding fuse pattern) to emulate the AND-OR, flip-flop, and output structure of any of a variety of combinational and sequential PAL devices, including the PAL16L8 introduced previously. Whats more, the GAL device can be erased electrically and reprogrammed. Figure 5-27 shows the logic diagram for a GAL16V8 when it has been configured as a strictly combinational device similar to the PAL16L8. This configuration is achieved by programming two architecture-control fuses, not shown. In this configuration, the device is called a GAL16V8C. The most important thing to note about the GAL16V8C logic diagram, compared to that of a PAL16L8 on page 303, is that an XOR gate has been inserted between each OR output and the three-state output driver. One input of the XOR gate is pulled up to a logic 1 value but connected to ground (0) via a fuse. If this fuse is intact, the XOR gate simply passes the OR-gates output unchanged, but if the fuse is blown the XOR gate inverts the OR -gates output. This fuse is said to control the output polarity of the corresponding output pin. Output-polarity control is a very important feature of modern PLDs, including the GAL16V8. As we discussed in Section 4.6.2, given a logic function to minimize, an ABEL compiler finds minimal sum-of-products expressions for both the function and its complement. If the complement yields fewer product terms, it can be used if the GAL16V8s output polarity fuse is set to invert. Unless overridden, the compiler automatically makes the best selection and sets up the fuse patterns appropriately. Several companies make a part that is equivalent to the GAL16V8, called the PALCE16V8. There is also a 24-pin GAL device, the GAL20V8 or PALCE20V8, that can be configured to emulate the structure of the PAL20L8 or any of a variety of sequential PLDs, as described in \secref{seqGAL}.
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Figure 5-27 Logic diagram of the GAL16V8C.
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VCC
Figure 5-28 A 4 3 PLA built using TTL-like open-collector gates and diode logic.
AND plane
OR plane
fusible link
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I1 I2 I3 I4 I1 I1 I2 I2 I3 I3 I4 I4 P1 P2 P3 P4 P5 P6 VCC O1 O2 O3
*5.3.4 Bipolar PLD Circuits There are several different circuit technologies for building and physically programming a PLD. Early commercial PLAs and PAL devices used bipolar circuits. For example, Figure 5-28 shows how the example 4 3 PLA circuit of the preceding section might be built in a bipolar, TTL-like technology. Each potential connection is made by a diode in series with a metal link that may be present or absent. If the link is present, then the diode connects its input into a diode-AND function. If the link is missing, then the corresponding input has no effect on that AND function. A diode-AND function is performed because each and every horizontal input line that is connected via a diode to a particular vertical AND line must be HIGH in order for that AND line to be HIGH. If an input line is LOW, it pulls LOW all of the AND lines to which it is connected. This first matrix of circuit elements that perform the AND function is called the AND plane. Each AND line is followed by an inverting buffer, so overall a NAND function is obtained. The outputs of the first-level NAND functions are combined by another set of programmable diode AND functions, once again followed by inverters. The result is a two-level NAND-NAND structure that is functionally equivalent to the AND-OR PLA structure described in the preceding section. The matrix of circuit elements that perform the OR function (or the second NAND function, depending on how you look at it) is called the OR plane. A bipolar PLD chip is manufactured with all of its diodes present, but with a tiny fusible link in series with each one (the little squiggles in Figure 5-28). By
* Throughout this book, optional sections are marked with an asterisk.
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applying special input patterns to the device, it is possible to select individual links, apply a high voltage (1030 V), and thereby vaporize selected links. Early bipolar PLDs had reliability problems. Sometimes the stored patterns changed because of incompletely vaporized links that would grow back, and sometimes intermittent failures occurred because of floating shrapnel inside the IC package. However, these problems have been largely worked out, and reliable fusible-link technology is used in todays bipolar PLDs.
*5.3.5 CMOS PLD Circuits Although theyre still available, bipolar PLDs have been largely supplanted by CMOS PLDs with a number of advantages, including reduced power consumption and reprogrammability. Figure 5-29 shows a CMOS design for the 4 3 PLA circuit of Section 5.3.1. Instead of a diode, an n-channel transistor with a programmable connection is placed at each intersection between an input line and a word line. If the input is LOW, then the transistor is off, but if the input is HIGH, then the transistor is on, which pulls the AND line LOW. Overall, an inverted-input AND (i.e., NOR) function is obtained. This is similar in structure and function to a normal CMOS k-input NOR gate, except that the usual series connection of k p-channel pull-up transistors has been replaced with a passive pull-up resistor (in practice, the pull-up is a single p-channel transistor with a constant bias). As shown in color on Figure 5-29, the effects of using an inverted-input AND gate are canceled by using the opposite (complemented) input lines for each input, compared with Figure 5-28. Also notice that the connection between
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I1 I2 I3 I4 /I1 /I1 /I2 /I2 /I3 /I3 /I4 /I4 P1 P2 P3 P4 P5 P6 VCC O1 O2 O3
Figure 5-29 A 4 3 PLA built using CMOS logic.
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erasable programmable logic device (EPLD)
floating-gate MOS transistor
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floating gate nonfloating gate
active-low input lines
Figure 5-30 AND p lane of an EPLD using floatinggate MOS transistors.
active-high AND lines
the AND plane and the OR plane is noninverting, so the AND plane performs a true AND function. The outputs of the first-level AND functions are combined in the OR plane by another set of NOR functions with programmable connections. The output of each NOR function is followed by an inverter, so a true OR function is realized, and overall the PLA performs an AND-OR function as desired. In CMOS PLD technologies, the programmable links shown in Figure 5-29 are not normally fuses. In non-field-programmable devices, such as custom VLSI chips, the presence or absence of each link is simply established as part of the metal mask pattern for the manufacture of the device. By far the most common programming technology, however, is used in CMOS EPLDs, as discussed next. An erasable programmable logic device (EPLD) can be programmed with any desired link configuration, as well as erased to its original state, either electronically or by exposing it to ultraviolet light. No, erasing does not cause links to suddenly appear or disappear! Rather, EPLDs use a different technology, called floating-gate MOS. As shown in Figure 5-30, an EPLD uses floating-gate MOS transistors. Such a transistor has two gates. The floating gate is unconnected and is surrounded by extremely high-impedance insulating material. In the original, manufactured state, the floating gate has no charge on it and has no effect on circuit operation. In this state, all transistors are effectively connected; that is, there is a logical link present at every crosspoint in the AND and OR planes. To program an EPLD, the programmer applies a high voltage to the nonfloating gate at each location where a logical link is not wanted. This causes a
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temporary breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains on the floating gate. During subsequent operations, the negative charge prevents the transistor from turning on when a HIGH signal is applied to the nonfloating gate; the transistor is effectively disconnected from the circuit. EPLD manufacturers claim that a properly programmed bit will retain 70% of its charge for at least 10 years, even if the part is stored at 125C, so for most applications the programming can be considered to be permanent. However, EPLDs can also be erased. Although some early EPLDs were packaged with a transparent lid and used light for erasing, todays devices are popular are electrically erasable PLDs. The floating gates in an electrically erasable PLD are surrounded by an extremely thin insulating layer, and can be erased by applying a voltage of the opposite polarity as the charging voltage to the nonfloating gate. Thus, the same piece of equipment that is normally used to program a PLD can also be used to erase an EPLD before programming it. Larger-scale, complex PLDs (CPLDs), also use floating-gate programming technology. Even larger devices, often called field-programmable gate arrays (FPGAs), use read/write memory cells to control the state of each connection. The read/write memory cells are volatilethey do not retain their state when power is removed. Therefore, when power is first applied to the FPGA, all of its read/write memory must be initialized to a state specified by a separate, external nonvolatile memory. This memory is typically either a programmable read-only memory (PROM) chip attached directly to the FPGA or its part of a microprocessor subsystem that initializes the FPGA as part of overall system initialization. *5.3.6 Device Programming and Testing A special piece of equipment is used to vaporize fuses, charge up floating-gate transistors, or do whatever else is required to program a PLD. This piece of equipment, found nowadays in almost all digital design labs and production facilities, is called a PLD programmer or a PROM programmer. (It can be used
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electrically erasable PLD field-programmable gate array (FPGA) PLD programmer PROM programmer CHANGING HARDWARE ON THE FLY PROMs are normally used to supply the connection pattern for a read/writememory-based FPGA, but there are also applications where the pattern is actually read from a floppy disk. You just received a floppy with a new software version? Guess what, you just got a new hardware version too! This concept leads us to the intriguing idea, already being applied in some applications, of reconfigurable hardware, where a hardware subsystem is redefined, on the fly, to optimize its performance for the particular task at hand. Copying Prohibited
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in-system programmability JTAG port
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with programmable read-only memories, PROMs, as well as for PLDs.) A typical PLD programmer includes a socket or sockets that physically accept the devices to be programmed, and a way to download desired programming patterns into the programmer, typically by connecting the programmer to a PC. PLD programmers typically place a PLD into a special mode of operation in order to program it. For example, a PLD programmer typically programs the PLDs described in this chapter eight fuses at a time as follows: 1. Raise a certain pin to a predetermined, high voltage (such as 14 V) to put the device into programming mode. 2. Select a group of eight fuses by applying a binary address to certain inputs of the device. (For example, the 82S100 has 1920 fuses, and would therefore require 8 inputs to select one of 240 groups of 8 fuses.) 3. Apply an 8-bit value to the outputs of the device to specify the desired programming for each fuse (the outputs are used as inputs in programming mode). 4. Raise a second predetermined pin to the high voltage for a predetermined length of time (such as 100 microseconds) to program the eight fuses. 5. Lower the second predetermined pin to a low voltage (such as 0 V) to read out and verify the programming of the eight fuses. 6. Repeat steps 15 for each group of eight fuses.
Many PLDs, especially larger CPLDs, feature in-system programmability. This means that the device can be programmed after it is already soldered into the system. In this case, the fuse patterns are applied to the device serially using four extra signals and pins, called the JTAG port, defined by IEEE standard 1149.1. These signals are defined so that multiple devices on the same printedcircuit board can be daisy chained and selected and programmed during the board manufacturing process using just one JTAG port on a special connector. No special high-voltage power supply is needed; each device uses a chargepump circuit internally to generate the high voltage needed for programming. As noted in step 5 above, fuse patterns are verified as they are programmed into a device. If a fuse fails to program properly the first time, the operation can be retried; if it fails to program properly after a few tries, the device is discarded (often with great prejudice and malice aforethought). While verifying the fuse pattern of a programmed device proves that its fuses are programmed properly, it does not prove that the device will perform the logic function specified by those fuses. This is true because the device may have unrelated internal defects such as missing connections between the fuses and elements of the AND-OR array. The only way to test for all defects is to put the device into its normal operational mode, apply a set of normal logic inputs, and observe the outputs. The
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required input and output patterns, called test vectors, can be specified by the designer as we showed in Section 4.6.7,or can be generated automatically by a special test-vector-generation program. Regardless of how the test vectors are generated, most PLD programmers have the ability to apply test-vector inputs to a PLD and to check its outputs against the expected results. Most PLDs have a security fuse which, when programmed, disables the ability to read fuse patterns from the device. Manufacturers can program this fuse to prevent others from reading out the PLD fuse patterns in order to copy the product design. Even if the security fuse is programmed, test vectors still work, so the PLD can still be checked.
5.4 Decoders
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is a one-toone mapping from input code words into output code words. In a one-to-one mapping, each input code word produces a different output code word. The general structure of a decoder circuit is shown in Figure 5-31. The enable inputs, if present, must be asserted for the decoder to perform its normal mapping function. Otherwise, the decoder maps all input code words into a single, disabled, output code word. The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n different coded values, normally the integers from 0 through 2n1. Sometimes an n-bit binary code is truncated to represent fewer than 2n values. For example, in the BCD code, the 4-bit combinations 0000 through 1001 represent the decimal digits 09, and combinations 1010 through 1111 are not used. The most commonly used output code is a 1-out-of-m code, which contains m bits, where one bit is asserted at any time. Thus, in a 1-out-of-4 code with active-high outputs, the code words are 0001, 0010, 0100, and 1000. With active-low outputs, the code words are 1110, 1101, 1011, and 0111.
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security fuse decoder one-to-one mapping
Decoder
ma p
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Figure 5-31 Decoder circuit structure.
output code word
enable inputs
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Figure 5-32 A 2-to-4 decoder: (a) inputs and outputs; (b) logic diagram.
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Ta b l e 5 - 4 Truth table for a 2-to-4 binary decoder.
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5.4.1 Binary Decoders The most common decoder circuit is an n-to-2n decoder or binary decoder. Such a decoder has an n-bit binary input code and a 1-out-of-2n output code. A binary decoder is used when you need to activate exactly one of 2n outputs based on an n-bit input value. For example, Figure 5-32(a) shows the inputs and outputs and Table 5-4 is the truth table of a 2-to-4 decoder. The input code word 1,I0 represents an integer in the range 03. The output code word Y3,Y2,Y1,Y0 has Yi equal to 1 if and only if the input code word is the binary representation of i and the enable input EN is 1. If EN is 0, then all of the outputs are 0. A gate-level circuit for the 2-to-4 decoder is shown in Figure 5-32(b). Each AND gate decodes one combination of the input code word I1,I0. The binary decoders truth table introduces a dont-care notation for input combinations. If one or more input values do not affect the output values for some combination of the remaining inputs, they are marked with an x for that input combination. This convention can greatly reduce the number of rows in the truth table, as well as make the functions of the inputs more clear. The input code of an n-bit binary decoder need not represent the integers from 0 through 2n1. For example, Table 5-5 shows the 3-bit Gray-code output
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of a mechanical encoding disk with eight positions. The eight disk positions can be decoded with a 3-bit binary decoder with the appropriate assignment of signals to the decoder outputs, as shown in Figure 5-33. Also, it is not necessary to use all of the outputs of a decoder, or even to decode all possible input combinations. For example, a decimal or BCD decoder decodes only the first ten binary input combinations 00001001 to produce outputs Y0Y9. 5.4.2 Logic Symbols for Larger-Scale Elements Before describing some commercially available 74-series MSI decoders, we need to discuss general guidelines for drawing logic symbols for larger-scale logic elements. The most basic rule is that logic symbols are drawn with inputs on the left and outputs on the right. The top and bottom edges of a logic symbol are not normally used for signal connections. However, explicit power and ground connections are sometimes shown at the top and bottom, especially if these connections are made on nonstandard pins. (Most MSI parts have power and ground connected to the corner pins, e.g., pins 8 and 16 of a 16-pin DIP package.)
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Binary Decoder Output
Y0 Y1 Y3 Y2 Y6 Y7 Y5 Y4
0 45 90 135 180 225 270 315
0 0 0 0 1 1 1 1
0 0 1 1 1 1 0 0
0 1 1 0 0 1 1 0
Ta b l e 5 - 5 Position encoding for a 3-bit mechanical encoding disk.
decimal decoder BCD decoder
3-to-8 decoder
SHAFTI0 SHAFTI1 SHAFTI2 ENABLE
I0 I1
I2 EN
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
DEG0 DEG45 DEG135 DEG90 DEG315 DEG270
Figure 5-33 Using a 3-to-8 binary decoder to decode a Gray code.
DEG180 DEG225
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Figure 5-34 Logic symbol for one-half of a 74x139 dual 2-to-4 decoder: (a) conventional symbol; (b) default signal names associated with external pins.
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LOGIC FAMILIES Most logic gates and larger-scale elements are available in a variety of CMOS and families, many of which we described in Sections 3.8 and 3.11. For example, the 74LS139, 74S139, 74ALS139, 74AS139, 74F139, 74HC139, 74HCT139, 74ACT139, 74AC139, 74FCT139 74AHC139, 74AHCT139, 74LC139, 74LVC139, and 74VHC139 are all dual 2-to-4 decoders with the same logic function, but in electrically different TTL and CMOS families and sometimes in different packages. In addition, macro logic elements with the same pin names and functions as the 139 and other popular 74-series devices are available as building blocks in most FPGA and ASIC design environments. Throughout this text, we use 74x as a generic prefix. And well sometimes omit the prefix and write, for example, 139. In a real schematic diagram for a circuit that you are going to build or simulate, you should include the full part number, since timing, loading, and packaging characteristics depend on the family.
1/2 74x139 1/2 74x139 G A B Y0 Y1 Y2 Y3 G_L G A B A B Y0 Y1 Y2 Y3 Y0_L Y1_L Y2_L Y3_L (a) (b)
Like gate symbols, the logic symbols for larger-scale elements associate an active level with each pin. With respect to active levels, its important to use a consistent convention to naming the internal signals and external pins. Larger-scale elements almost always have their signal names defined in terms of the functions performed inside their symbolic outline, as explained in Section 5.1.4. For example, Figure 5-34(a) shows the logic symbol for one section of a 74x139 dual 2-to-4 decoder, an MSI part that well fully describe in the next subsection. When the G input is asserted, one of the outputs Y0Y3 is asserted, as selected by a 2-bit code applied to the A and B inputs. It is apparent from the symbol that the G input pin and all of the output pins are active low. When the 74x139 symbol appears in the logic diagram for a real application, its inputs and outputs have signals connected to other devices, and each such signal has a name that indicates its function in the application. However, when we describe the 74x139 in isolation, we might still like to have a name for the signal on each external pin. Figure 5-34(b) shows our naming convention in this case. Active-high pins are given the same name as the internal signal, while active-low pins have the internal signal name followed by the suffix _L.
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IEEE STANDARD LOGIC SYMBOLS
5.4.3 The 74x139 Dual 2-to-4 Decoder Two independent and identical 2-to-4 decoders are contained in a single MSI part, the 74x139. The gate-level circuit diagram for this IC is shown in Figure 5-35(a). Notice that the outputs and the enable input of the 139 are active-low. Most MSI decoders were originally designed with active-low outputs, since TTL inverting gates are generally faster than noninverting ones. Also notice that the 139 has extra inverters on its select inputs. Without these inverters, each select input would present three AC or DC loads instead of one, consuming much more of the fanout budget of the device that drives it.
Figure 5-35 The 74x139 dual 2-to-4 decoder: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol; (c) logic symbol for one decoder.
(4)
1G_L
(a)
2G_L
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Throughout this book, we use traditional symbols for larger-scale logic elements. The IEEE standard uses somewhat different symbols for larger-scale logic elements. IEEE standard symbols, as well as the pros and cons of IEEE versus traditional symbols, are discussed in Appendix A. 74x139
1Y0_L 74x139
(1) 1
1G 1A 1B
(5)
1Y1_L
2 3
1Y0 1Y1 1Y2 1Y3
4 5 6 7
(6)
1Y2_L
15
1A 1B
(2)
2G 2A 2B
(7)
14 13
(3)
1Y3_L
2Y0 2Y1 2Y2 2Y3
12
11 10 9
(12)
(b)
2Y0_L
(15)
(11)
2Y1_L
1/2 74x139
G A B
(10)
2Y2_L
2A 2B
(14)
Y0 Y1 Y2 Y3
(9)
(13)
2Y3_L
(c)
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function table
Figure 5-36 More ways to symbolize a 74x139: (a) correct but to be avoided; (b) incorrect because of double negations.
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Ta b l e 5 - 6 Truth table for onehalf of a 74x139 dual 2-to-4 decoder.
Inputs
B
Outputs
G_L
A
Y3_L
Y2_L
Y1_L
Y0_L
1 0 0 0 0
x 0 0 1 1
x 0 1 0 1
1 1 1 1 0
1 1 1 0 1
1 1 0 1 1
1 0 1 1 1
A logic symbol for the 74x139 is shown in Figure 5-35(b). Notice that all of the signal names inside the symbol outline are active-high (no _L), and that inversion bubbles indicate active-low inputs and outputs. Often a schematic may use a generic symbol for just one decoder, one-half of a 139, as shown in (c). In this case, the assignment of the generic function to one half or the other of a particular 139 package can be deferred until the schematic is completed. Table 5-6 is the truth table for a 74x139-type decoder. The truth tables in some manufacturers data books use L and H to denote the input and output signal voltage levels, so there can be no ambiguity about the electrical function of the device; a truth table written this way is sometimes called a function table. However, since we use positive logic throughout this book, we can use 0 and 1 without ambiguity. In any case, the truth table gives the logic function in terms of the external pins of the device. A truth table for the function performed inside the symbol outline would look just like Table 5-4, except that the input signal names would be G, B, A. Some logic designers draw the symbol for 74x139s and other logic functions without inversion bubbles. Instead, they use an overbar on signal names inside the symbol outline to indicate negation, as shown in Figure 5-36(a). This notation is self-consistent, but it is inconsistent with our drawing standards for bubble-to-bubble logic design. The symbol shown in (b) is absolutely incorrect: according to this symbol, a logic 1, not 0, must be applied to the enable pin to enable the decoder.
1/2 74x139
1/2 74x139
G A B
(a)
Y0 Y1 Y2 Y3
G A B
(b)
Y0 Y1 Y2 Y3
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5.4.4 The 74x138 3-to-8 Decoder The 74x138 is a commercially available MSI 3-to-8 decoder whose gate-level circuit diagram and symbol are shown in Figure 5-37; its truth table is given in Table 5-7. Like the 74x139, the 74x138 has active-low outputs, and it has three enable inputs (G1, /G2A, /G2B), all of which must be asserted for the selected output to be asserted. The logic function of the 138 is straightforwardan output is asserted if and only if the decoder is enabled and the output is selected. Thus, we can easily write logic equations for an internal output signal such as Y5 in terms of the internal input signals:
enable
However, because of the inversion bubbles, we have the following relations between internal and external signals:
G2A = G2A_L G2B = G2B_L Y5 = Y5_L
Therefore, if were interested, we can write the following equation for the external output signal Y5_L in terms of external input signals:
Y5_L = Y5 = (G1 G2A_L G2B_L C B A) = G1 + G2A_L + G2B_L + C + B + A
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BAD NAMES Some manufacturers data sheets have inconsistencies similar to Figure 5-36(b). For example, Texas Instruments data sheet for the 74AHC139 uses active low-names like 1G for the enable inputs, with the overbar indicating an active-low pin, but active-high names like 1Y0 for all the active-low output pins. On the other hand, Motorolas data sheet for the 74VHC139 correctly uses overbars on the names for both the enable inputs and the outputs, but the overbars are barely visible in the devices function table due to a typographical problem. Ive also had the personal experience of building a printed-circuit board with many copies of a new device from a vendor whose documentation clearly indicated that a particular input was active low, only to find out upon the first power-on that the input was active high. The moral of the story is that you have to study the description of each device to know whats really going on. And if its a brand-new device, whether from a commercial vendor or your own companys ASIC group, you should double-check all of the signal polarities and pin assignments before committing to a PCB. Be assured, however, that the signal names in this text are consistent and correct. 74x138
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select
Y5 = G1 G2A G2B C B A
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T a b l e 5 - 7 Truth table for a 74x138 3-to-8 decoder.
Inputs Outputs
G1 G2A_L G2B_L C B A Y7_L Y6_L Y5_L Y4_L Y3_L Y2_L Y1_L
Y0_L
0 x x 1 1 1 1 1 1 1 1
x 1 x 0 0 0 0 0 0 0 0
x x 1 0 0 0 0 0 0 0 0
x x x 0 0 0 0 1 1 1 1
x x x 0 0 1 1 0 0 1 1
x x x 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 0 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
On the surface, this equation doesnt resemble what you might expect for a decoder, since it is a logical sum rather than a product. However, if you practice bubble-to-bubble logic design, you dont have to worry about this; you just give the output signal an active-low name and remember that its active low when you connect it to other inputs.
5.4.5 Cascading Binary Decoders Multiple binary decoders can be used to decode larger code words. Figure 5-38 shows how two 3-to-8 decoders can be combined to make a 4-to-16 decoder. The availability of both active-high and active-low enable inputs on the 74x138 makes it possible to enable one or the other directly based on the state of the most significant input bit. The top decoder (U1) is enabled when N3 is 0, and the bottom one (U2) is enabled when N3 is 1. To handle even larger code words, binary decoders can be cascaded hierarchically. Figure 5-39 shows how to use half of a 74x139 to decode the two highorder bits of a 5-bit code word, thereby enabling one of four 74x138s that decode the three low-order bits. 5.4.6 Decoders in ABEL and PLDs Nothing in logic design is much easier than writing the PLD equations for a decoder. Since the logic expression for each output is typically just a single product term, decoders are very easily targeted to PLDs and use few product-term resources.
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(a)
(15)
Decoders
74x138
321
G2A_L G2B_L
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Y0_L (b)
6 (14) 4 5
Y1_L
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13
12 11 10 9
G1
(6) (4) (5)
(13)
1
Y2_L
(12)
A 2 B 3 C
Y3_L
Y4 Y5 Y6 Y7
7
(11)
Y4_L
(10)
A
(1)
Y5_L
(9)
B
(2)
Y6_L
C
(3)
(7)
Y7_L
Figure 5-37 The 74x138 3-to-8 decoder: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.
+5V
74x138
R
6
4 5
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13 12 11 10 9 7
N0 N1 N2 N3 EN_L
1
A 2 B 3 C
Y4 Y5 Y6 Y7
DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L
Figure 5-38 Design of a 4-to-16 decoder using 74x138s.
U1
74x138
6
4 5
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13 12 11 10 9 7
1
A 2 B 3 C
Y4 Y5 Y6 Y7
DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L
U2
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74x138
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6 4 5
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13
12 11 10 9
N0 N1 N2
1
A 2 B 3 C
Y4 Y5 Y6 Y7
7
DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L
U2 74x138 Y0 Y1 Y2 Y3
6
15 14 13 12 11 10 9 7
4 5
G1 G2A G2B
1
1/2 74x139
EN3_L N3 N4
1
1G 1A 1B
2 3
1Y0 1Y1 1Y2 1Y3
4
5 6 7
EN0X7_L EN8X15_L EN16X23_L EN24X31_L
A 2 B 3 C
Y4 Y5 Y6 Y7
DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L
U3 74x138 Y0 Y1 Y2 Y3
U1
6
15 14 13 12 11 10 9 7
4 5
G1 G2A G2B
1
EN1 EN2_L
A 2 B 3 C
Y4 Y5 Y6 Y7
DEC16_L DEC17_L DEC18_L DEC19_L DEC20_L DEC21_L DEC22_L DEC23_L
U4 74x138 Y0 Y1 Y2 Y3
6
15 14 13
4 5
G1 G2A G2B
12 11 10 9
1
A 2 B 3 C
Y4 Y5 Y6 Y7
7
DEC24_L DEC25_L DEC26_L DEC27_L DEC28_L DEC29_L DEC30_L DEC31_L
U5
Figure 5-39 Design of a 5-to-32 decoder using 74x138s and a 74x139.
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module Z74X138 title '74x138 Decoder PLD J. Wakerly, Stanford University' Z74X138 device 'P16L8'; " Input pins A, B, C, !G2A, !G2B, G1 " Output pins !Y0, !Y1, !Y2, !Y3 !Y4, !Y5, !Y6, !Y7
" Constant expression ENB = G1 & G2A & G2B; equations Y0 = ENB & Y1 = ENB & Y2 = ENB & Y3 = ENB & Y4 = ENB & Y5 = ENB & Y6 = ENB & Y7 = ENB &
end Z74X138
For example, Table 5-8 is an ABEL program for a 74x138-like 3-to-8 binary decoder as realized in a PAL16L8. A corresponding logic diagram with signal names is shown in Figure 5-40. In the ABEL program, notice the use of the ! prefix in the pin declarations to specify active-low inputs and outputs, even though the equations are written in terms of active-high signals.
PAL16L8
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Ta b l e 5 - 8 An ABEL program for a 74x138-like 3-to-8 binary decoder.
pin 1, 2, 3, 4, 5, 6; pin 19, 18, 17, 16 istype 'com'; pin 15, 14, 13, 12 istype 'com'; !C !C !C !C C C C C & & & & & & & & !B !B B B !B !B B B & & & & & & & & !A; A; !A; A; !A; A; !A; A;
A B C
1
I1 2 I2
3
O1
19 18
Y0_L Y1_L Y2_L Y3_L Y4_L Y5_L Y6_L Y7_L
G2A_L G2B_L G1_L
I3 4 I4
5
IO2 17 IO3
16
Figure 5-40 Logic diagram for the PAL16L8 used as a 74x138 decoder.
I5 6 I6
7 8
IO4 15 IO5 IO6 13 IO7 12 O8
14
N.C. N.C. N.C. N.C.
I7 I8 9 I9
11
I10
Z74X138
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Y0, Y1, Y2, Y3 Y4, Y5, Y6, Y7 pin 19, 18, 17, 16 istype com; pin 15, 14, 13, 12 istype com; EN1, !EN2 pin 7, 8; ... ENB = G1 & G2A & G2B # EN1 # EN2; Y0 = G1 & G2A & G2B & !C & !B &!A # EN1 & !C & !B & !A # EN2 & !C & !B & !A; !Y0 = C # B # A # !G2B & !EN1 & !EN2 # !G2A & !EN1 & !EN2 # !G1 & !EN1 & !EN2;
Also note that this example defines a constant expression for ENB. Here, ENB is not an input or output signal, but merely a user-defined name. In the equations section, the compiler substitutes the expression (G1 & G2A & G2B) everywhere that ENB appears. Assigning the constant expression to a userdefined name improves the programs readability and maintainability. If all you needed was a 138, youd be better off using a real 138 than a PLD. However, if you need nonstandard functionality, then the PLD can usually achieve it much more cheaply and easily than an MSISSI-based solution. For example, if you need the functionality of a 138 but with active-high outputs, you need only to change two lines in the pin declarations of Table 5-8:
Since each of the equations required a single product of six variables (including the three in the ENB expression), each complemented equation requires a sum of six product terms, less than the seven available in a PAL16L8. If you use a PAL16V8 or other device with output polarity selection, then the compiler selects non-inverted output polarity to use only one product term per output. Another easy change is to provide alternate enable inputs that are ORed with the main enable inputs. To do this, you need only define additional pins and modify the definition of ENB:
This change expands the number of product terms per output to three, each having a form similar to
(Remember that the PAL16L8 has a fixed inverter and the PAL16V8 has a selectable inverter between the AND-OR array and the output of the PLD, so the actual output is active low as desired.) If you add the extra enables to the version of the program with active-high outputs, then the PLD must realize the complement of the sum-of-products expression above. Its not immediately obvious how many product terms this expression will have, and whether it will fit in a PAL16L8, but we can use the ABEL compiler to get the answer for us:
The expression has a total of six product terms, so it fits in a PAL16L8.
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... " Output pins !Y0, !Y1, !Y2, !Y3 !Y4, !Y5, !Y6, ENB
equations ENB = G1 & G2A & G2B # EN1 # EN2; Y0 = POL $ (ENB & !C & !B & !A); ...
As a final tweak, we can add an input to dynamically control whether the output is active high or active low, and modify all of the equations as follows:
POL pin 9; ... Y0 = POL $ (ENB & !C & !B & !A); Y1 = POL $ (ENB & !C & !B & A); ... Y7 = POL $ (ENB & C & B & A);
As a result of the XOR operation, the number of product terms needed per output increases to 9, in either output-pin polarity. Thus, even a PAL16V8 cannot implement the function as written. The function can still be realized if we create a helper output to reduce the product term explosion. As shown in Table 5-9, we allocate an output pin for the ENB expression, and move the ENB equation into the equations section of the program. This reduces the product-term requirement to 5 in either polarity. Besides sacrificing a pin for the helper output, this realization has the disadvantage of being slower. Any changes in the inputs to the helper expression must propagate through the PLD twice before reaching the final output. This is called two-pass logic. Many PLD and FPGA synthesis tools can automatically
Ta b l e 5 - 1 0 Truth table for a customized decoder function.
CS_L RD_L A2 A1 A0
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Ta b l e 5 - 9 ABEL program fragment showing two-pass logic.
pin 19, 18, 17, 16 istype 'com'; pin 15, 14, 13, 12 istype 'com';
helper output
helper output
two-pass logic
Output(s) to Assert
1 x 0 0 0 0 0 0 0 0
x 1 0 0 0 0 0 0 0 0
x x 0 0 0 0 1 1 1 1
x x 0 0 1 1 0 0 1 1
x x 0 1 0 1 0 1 0 1
none none
BILL_L, MARY_L MARY_L, KATE_L JOAN_L PAUL_L ANNA_L FRED_L DAVE_L KATE_L
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74x138 BILL_L
Figure 5-41 Customized decoder circuit.
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+5V R 74x08
6
CS_L RD_L A0 A1 A2
4 5
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13 12 11 10 9 7
1 2
3
MARY_L JOAN_L PAUL_L ANNA_L FRED_L DAVE_L KATE_L
U2
1
A 2 B 3 C
Y4 Y5 Y6 Y7
74x08
4 5
U1
6
U2
generate logic with two or more passes if a required expression cannot be realized in just one pass through the logic array. Decoders can be customized in other ways. A common customization is for a single output to decode more than one input combination. For example, suppose you needed to generate a set of enable signals according to Table 5-10 on the preceding page. A 74x138 MSI decoder can be augmented as shown in Figure 5-41 to perform the required function. This approach, while potentially less expensive than a PLD, has the disadvantages that it requires extra components and delay to create the required outputs, and it is not easily modified.
Ta b l e 5 - 1 1 ABEL equations for a customized decoder.
module CUSTMDEC title 'Customized Decoder PLD J. Wakerly, Stanford University' CUSTMDEC device P16L8; " Input pins !CS, !RD, A0, A1, A2 " Output pins !BILL, !MARY, !JOAN, !PAUL !ANNA, !FRED, !DAVE, !KATE equations BILL = CS MARY = CS KATE = CS JOAN = CS PAUL = CS ANNA = CS FRED = CS DAVE = CS
pin 1, 2, 3, 4, 5;
pin 19, 18, 17, 16 istype 'com'; pin 15, 14, 13, 12 istype 'com';
& & & & & & & &
RD RD RD RD RD RD RD RD
& & & & & & & &
(!A2 (!A2 (!A2 (!A2 (!A2 ( A2 ( A2 ( A2
& & & & & & & &
!A1 !A1 !A1 A1 A1 !A1 !A1 A1
& & & & & & & &
!A0); !A0 # !A2 & !A1 & A0 # A2 & A1 & !A0); A0); !A0); A0); !A0);
A0); A0);
end CUSTMDEC
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A PLD solution to the same problem is shown in Table 5-11. Each of the last six equations uses a single AND gate in the PLD. The ABEL compiler will also minimize the MARY equation to use just one AND gate. Once again, activehigh output signals could be obtained just by changing two lines in the declaration section:
BILL, MARY, JOAN, PAUL ANNA, FRED, DAVE, KATE pin 19, 18, 17, 16 istype com; pin 15, 14, 13, 12 istype com;
Another way of writing the equations is shown in Table 5-12. In most applications, this style is more clear, especially if the select inputs have numeric significance.
Ta b l e 5 - 1 2 Equivalent ABEL equations for a customized decoder.
ADDR = [A2,A1,A0]; equations BILL = CS MARY = CS KATE = CS JOAN = CS PAUL = CS ANNA = CS FRED = CS DAVE = CS
5.4.7 Decoders in VHDL There are several ways to approach the design of decoders in VHDL. The most primitive approach would be to write a structural equivalent of a decoder logic circuit, as Table 5-13 does for the 2-to-4 binary decoder of Figure 5-32 on page 314. Of course, this mechanical conversion of an existing design into the equivalent of a netlist defeats the purpose of using VHDL in the first place. Instead, we would like to write a program that uses VHDL to make our decoder design more understandable and maintainable. Table 5-14 shows one approach to writing code for a 3-to-8 binary decoder equivalent to the 74x138, using the dataflow style of VHDL. The address inputs A(2 downto 0) and the active-low decoded outputs Y_L(0 to 7) are declared using vectors to improve readability. A select statement enumerates the eight decoding cases and assigns the appropriate active-low output pattern to an 8-bit internal signal Y_L_i. This value is assigned to the actual circuit output Y_L only if all of the enable inputs are asserted. This design is a good start, and it works, but it does have a potential pitfall. The adjustments that handle the fact that two inputs and all the outputs are active-low happen to be buried in the final assignment statement. While its true
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& & & & & & & & RD RD RD RD RD RD RD RD & & & & & & & & (ADDR (ADDR (ADDR (ADDR (ADDR (ADDR (ADDR (ADDR == == == == == == == == 0); 0) # (ADDR == 1); 1) # (ADDR == 7); 2); 3); 4); 5); 6);
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Ta b l e 5 - 1 3 VHDL structural program for the decoder in Figure 5-32.
library IEEE; use IEEE.std_logic_1164.all; entity V2to4dec is port (I0, I1, EN: in STD_LOGIC; Y0, Y1, Y2, Y3: out STD_LOGIC ); end V2to4dec;
architecture V2to4dec_s of V2to4dec is signal NOTI0, NOTI1: STD_LOGIC; component inv port (I: in STD_LOGIC; O: out STD_LOGIC ); end component; component and3 port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC ); end component; begin U1: inv port map (I0,NOTI0); U2: inv port map (I1,NOTI1); U3: and3 port map (NOTI0,NOTI1,EN,Y0); U4: and3 port map ( I0,NOTI1,EN,Y1); U5: and3 port map (NOTI0, I1,EN,Y2); U6: and3 port map ( I0, I1,EN,Y3); end V2to4dec_s;
Ta b l e 5 - 1 4 Dataflow-style VHDL program for a 74x138-like 3-to-8 binary decoder.
library IEEE; use IEEE.std_logic_1164.all;
entity V74x138 is port (G1, G2A_L, G2B_L: in STD_LOGIC; A: in STD_LOGIC_VECTOR (2 downto 0); Y_L: out STD_LOGIC_VECTOR (0 to 7) ); end V74x138;
-- enable inputs -- select inputs -- decoded outputs
architecture V74x138_a of V74x138 is signal Y_L_i: STD_LOGIC_VECTOR (0 to 7); begin with A select Y_L_i <= "01111111" when "000", "10111111" when "001", "11011111" when "010", "11101111" when "011", "11110111" when "100", "11111011" when "101", "11111101" when "110", "11111110" when "111", "11111111" when others; Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else "11111111"; end V74x138_a;
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architecture V74x138_b of V74x138 is signal G2A, G2B: STD_LOGIC; -signal Y: STD_LOGIC_VECTOR (0 to 7); -signal Y_s: STD_LOGIC_VECTOR (0 to 7); -begin G2A <= not G2A_L; -- convert inputs G2B <= not G2B_L; -- convert inputs Y_L <= Y; -- convert outputs with A select Y_s <= "10000000" when "000", "01000000" when "001", "00100000" when "010", "00010000" when "011", "00001000" when "100", "00000100" when "101", "00000010" when "110", "00000001" when "111", "00000000" when others; Y <= not Y_s when (G1 and G2A and G2B)='1' end V74x138_b;
that most VHDL programs are written almost entirely with active-high signals, if were defining a device with active-low external pins, we really should handle them in a more systematic and easily maintainable way. Table 5-15 shows such an approach. No changes are made to the entity declarations. However, active-high versions of the active-low external pins are defined within the V74x138_a architecture, and explicit assignment statements are used to convert between the active-high and active-low signals. The decoder function itself is defined in terms of only the active-high signals, probably the biggest advantage of this approach. Another advantage is that the design can be easily modified in just a few well-defined places if changes are required in the external active levels.
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Ta b l e 5 - 1 5 VHDL architecture with a maintainable approach to active-level handling.
active-high version of inputs active-high version of outputs internal signal else "00000000";
OUT-OF-ORDER EXECUTION
In Table 5-15, weve grouped all three of the active-level conversion statements together at the beginning of program, even a value isnt assigned to Y_L until after a value is assigned to Y, later in the program. Remember that this is OK because the assignment statements in the architecture body are executed concurrently. That is, an assignment to any signal causes all the other statements that use that signal to be re-evaluated, regardless of their position in the architecture body. You could put the Y_L <= Y statement at the end of the body if its current position bothers you, but the program is a bit more maintainable in its present form, with all the active-level conversions together.
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Ta b l e 5 - 1 6 Hierarchical definition of 74x138-like decoder with active-level handling.
architecture V74x138_c of V74x138 is signal G2A, G2B: STD_LOGIC; -- active-high version of inputs signal Y: STD_LOGIC_VECTOR (0 to 7); -- active-high version of outputs component V3to8dec port (G1, G2, G3: in STD_LOGIC; A: in STD_LOGIC_VECTOR (2 downto 0); Y: out STD_LOGIC_VECTOR (0 to 7) ); end component; begin G2A <= not G2A_L; -- convert inputs G2B <= not G2B_L; -- convert inputs Y_L <= not Y; -- convert outputs U1: V3to8dec port map (G1, G2A, G2B, A, Y); end V74x138_c;
Active levels can be handled in an even more structured way. As shown in Table 5-16, the V74x138 architecture can be defined hierarchically, using a fully active-high V3to8dec component that has its own dataflow-style definition in Table 5-17. Once again, no changes are required in the top-level definition of the V74x138 entity. Figure 5-42 shows the relationship between the entities. Still another approach to decoder design is shown in Table 5-18, which can replace the V3to8dec_a architecture of Table 5-17. Instead of concurrent stateTa b l e 5 - 1 7 Dataflow definition of an active-high 3-to-8 decoder.
library IEEE; use IEEE.std_logic_1164.all;
entity V3to8dec is port (G1, G2, G3: in STD_LOGIC; A: in STD_LOGIC_VECTOR (2 downto 0); Y: out STD_LOGIC_VECTOR (0 to 7) ); end V3to8dec; architecture V3to8dec_a of V3to8dec is signal Y_s: STD_LOGIC_VECTOR (0 to 7); begin with A select Y_s <= "10000000" when "000", "01000000" when "001", "00100000" when "010", "00010000" when "011", "00001000" when "100", "00000100" when "101", "00000010" when "110", "00000001" when "111", "00000000" when others; Y <= Y_s when (G1 and G2 and G3)='1' else "00000000"; end V3to8dec_a;
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(a)
Figure 5-42 VHDL entity V74x138: (a) top level; (b) internal structure using architecture V74x138_c.
NAME MATCHING
ments, this architecture uses a process and sequential statements to define the decoders operation in a behavioral style. However, a close comparison of the two architectures shows that theyre really not that different except for syntax.
architecture V3to8dec_b of V3to8dec is signal Y_s: STD_LOGIC_VECTOR (0 to 7); begin process(A, G1, G2, G3, Y_s) begin case A is when "000" => Y_s <= "10000000"; when "001" => Y_s <= "01000000"; when "010" => Y_s <= "00100000"; when "011" => Y_s <= "00010000"; when "100" => Y_s <= "00001000"; when "101" => Y_s <= "00000100"; when "110" => Y_s <= "00000010"; when "111" => Y_s <= "00000001"; when others => Y_s <= "00000000"; end case; if (G1 and G2 and G3)='1' then Y <= Y_s; else Y <= "00000000"; end if; end process; end V3to8dec_b;
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entity V74x138 G1 Y_L[0:7] entity V3to8dec G1 G1 G2A_L G2B_L A[2:0] G2A_L G2B_L A[2:0] not not G2A G2B G2 G3 Y[0:7] Y[0:7] not Y_L[0:7] A[2:0] (b)
In Figure 5-42, the port names of an entity are drawn inside the corresponding box. The names of the signals that are connected to the ports when the entity is used are drawn on the signal lines. Notice that the signal names may match, but they dont have to. The VHDL compiler keeps everything straight, associating a scope with each name. The situation is completely analogous to the way variable and parameter names are handled in structured, procedural programming languages like C.
Ta b l e 5 - 1 8 Behavioral-style architecture definition for a 3-to-8 decoder.
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seven-segment display
seven-segment decoder
74x49
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Ta b l e 5 - 1 9 Truly behavioral architecture definition for a 3-to-8 decoder.
a f g b e c d
architecture V3to8dec_c of V3to8dec is begin process (G1, G2, G3, A) variable i: INTEGER range 0 to 7; begin Y <= "00000000"; if (G1 and G2 and G3) = '1' then for i in 0 to 7 loop if i=CONV_INTEGER(A) then Y(i) <= '1'; end if; end loop; end if; end process; end V3to8dec_c;
As a final example, a more truly behavioral, process-based architecture for the 3-to-8 decoder is shown in Table 5-19. (Recall that the CONV_INTEGER function was defined in \secref{VHDLconv}.) Of the examples weve given, this is the only one that describes the decoder function without essentially embedding a truth table in the VHDL program. In that respect, it is more flexible because it can be easily adapted to make a binary decoder of any size. In another respect, it is less flexible in that it does not have a truth table that can be easily modified to make custom decoders like the one we specified in Table 5-10 on page 325. *5.4.8 Seven-Segment Decoders Look at your wrist and youll probably see a seven-segment display. This type of display, which normally uses light-emitting diodes (LEDs) or liquid-crystal display (LCD) elements, is used in watches, calculators, and instruments to display decimal data. A digit is displayed by illuminating a subset of the seven line segments shown in Figure 5-43(a). A seven-segment decoder has 4-bit BCD as its input code and the sevensegment code, which is graphically depicted in Figure 5-43(b), as its output code. Figure 5-44 and Table 5-20 are the logic diagram truth table and for a 74x49 seven-segment decoder. Except for the strange (clever?) connection of the blanking input BI_L, each output of the 74x49 is a minimal product-of-sums
Figure 5-43 Seven-segment display: (a) segment identification; (b) decimal digits.
(a)
(b)
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(b)
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(11)
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3
BI
a 10 b c
9 8
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5
A
1 2 4
B C D
d 6 e
(9)
f 12 g
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c
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(6)
e
A
(5)
(13)
B
(1)
f
C
(2)
(12)
g
D
(4)
Figure 5-44 The 74x49 seven-segment decoder: (a) logic diagram, including pin numbers; (b) traditional logic symbol.
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Ta b l e 5 - 2 0 Truth table for a 74x49 seven-segment decoder.
Inputs
C
Outputs
d
BI_L
D
B
A
a
b
c
e
f
g
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0
0 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0
0 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0
0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0
0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0
0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0
0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0
realization for the corresponding segment, assuming dont-cares for the nondecimal input combinations. The INVERT-OR -AND structure used for each output may seem a little strange, but it is equivalent under the generalized DeMorgans theorem to an AND-OR-INVERT gate, which is a fairly fast and compact structure to build in CMOS or TTL. Most modern seven-segment display elements have decoders built into them, so that a 4-bit BCD word can be applied directly to the device. Many of the older, discrete seven-segment decoders have special high-voltage or highcurrent outputs that are well suited for driving large, high-powered display elements. Table 5-21 is an ABEL program for a seven-segment decoder. Sets are used to define the digit patterns to make the program more readable.
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module Z74X49H title 'Seven-Segment_Decoder J. Wakerly, Micro Design Resources, Inc.' Z74X49H device 'P16L8'; " Input pins A, B, C, D !BI
" Output pins SEGA, SEGB, SEGC, SEGD SEGE, SEGF, SEGG
" Set definitions DIGITIN = [D,C,B,A]; SEGOUT = [SEGA,SEGB,SEGC,SEGD,SEGE,SEGF,SEGG]; " Segment encodings for digits DIG0 = [1,1,1,1,1,1,0]; " 0 DIG1 = [0,1,1,0,0,0,0]; " 1 DIG2 = [1,1,0,1,1,0,1]; " 2 DIG3 = [1,1,1,1,0,0,1]; " 3 DIG4 = [0,1,1,0,0,1,1]; " 4 DIG5 = [1,0,1,1,0,1,1]; " 5 DIG6 = [1,0,1,1,1,1,1]; " 6 'tail' included DIG7 = [1,1,1,0,0,0,0]; " 7 DIG8 = [1,1,1,1,1,1,1]; " 8 DIG9 = [1,1,1,1,0,1,1]; " 9 'tail' included DIGA = [1,1,1,0,1,1,1]; " A DIGB = [0,0,1,1,1,1,1]; " b DIGC = [1,0,0,1,1,1,0]; " C DIGD = [0,1,1,1,1,0,1]; " d DIGE = [1,0,0,1,1,1,1]; " E DIGF = [1,0,0,0,1,1,1]; " F equations
SEGOUT = !BI & ( # # # # # # # end Z74X49H
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Ta b l e 5 - 2 1 ABEL program for a 74x49-like seven-segment decoder.
pin 1, 2, 3, 4; pin 5; pin 19, 18, 17, 16 istype 'com'; pin 15, 14, 13 istype 'com'; (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN == 0) & DIG0 == 2) & DIG2 == 4) & DIG4 == 6) & DIG6 == 8) & DIG8 == 10) & DIGA == 12) & DIGC == 14) & DIGE # # # # # # # # (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN (DIGITIN == 1) & DIG1 == 3) & DIG3 == 5) & DIG5 == 7) & DIG7 == 9) & DIG9 == 11) & DIGB == 13) & DIGD == 15) & DIGF );
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encoder
2n-to-n encoder binary encoder
Figure 5-45 Binary encoder: (a) general structure; (b) 8-to-3 encoder.
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5.5 Encoders
Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7
Binary encoder 2n inputs I0 I1 I2 Y0 Y1
A decoders output code normally has more bits than its input code. If the devices output code has fewer bits than the input code, the device is usually called an encoder. For example, consider a device with eight input bits representing an unsigned binary number, and two output bits indicating whether the number is prime or divisible by 7. We might call such a device a lucky/prime encoder. Probably the simplest encoder to build is a 2n-to-n or binary encoder. As shown in Figure 5-45(a), it has just the opposite function as a binary decoder its input code is the 1-out-of-2n code and its output code is n-bit binary. The equations for an 8-to-3 encoder with inputs I0I7 and outputs Y0Y2 are given below:
The corresponding logic circuit is shown in (b). In general, a 2n-to-n encoder can be built from n 2 n1-input OR gates. Bit i of the input code is connected to OR gate j if bit j in the binary representation of i is 1.
Y0
n outputs
Yn1
I2
n1
(a)
(b)
I0 I1 I2 I3 I4 I5 I6 I7
Y1
Y2
5.5.1 Priority Encoders The 1-out-of-2 n coded outputs of an n-bit binary decoder are generally used to control a set of 2 n devices, where at most one device is supposed to be active at any time. Conversely, consider a system with 2 n inputs, each of which indicates a request for service, as in Figure 5-46. This structure is often found in microprocessor input/output subsystems, where the inputs might be interrupt requests. In this situation, it may seem natural to use a binary encoder of the type shown in Figure 5-45 to observe the inputs and indicate which one is requesting service at any time. However, this encoder works properly only if the inputs are guaranteed to be asserted at most one at a time. If multiple requests can be made
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simultaneously, the encoder gives undesirable results. For example, suppose that inputs I2 and I4 of the 8-to-3 encoder are both 1; then the output is 110, the binary encoding of 6. Either 2 or 4, not 6, would be a useful output in the preceding example, but how can the encoding device decide which? The solution is to assign priority to the input lines, so that when multiple requests are asserted, the encoding device produces the number of the highest-priority requestor. Such a device is called a priority encoder. The logic symbol for an 8-input priority encoder is shown in Figure 5-47. Input I7 has the highest priority. Outputs A2A0 contain the number of the highest-priority asserted input, if any. The IDLE output is asserted if no inputs are asserted. In order to write logic equations for the priority encoders outputs, we first define eight intermediate variables H0H7, such that Hi is 1 if and only if Ii is the highest priority 1 input:
H7 = I7 H5 = H6 = I6 I7
Using these signals, the equations for the A2A0 outputs are similar to the ones for a simple binary encoder:
A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7
The IDLE output is 1 if no inputs are 1:
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Request encoder Requests for service REQ1 REQ2 REQ3 Requestor's number REQN
Figure 5-46 A system with 2n requestors, and a request encoder that indicates which request signal is asserted at any time.
priority
priority encoder
Priority encoder
I7
I5 I6 I7
I6
H0 = I0 I1 I2 I3 I4 I5 I6 I7
I5 I4 I3 I2 I1 I0
A2 A1 A0
IDLE
Figure 5-47 Logic symbol for a generic 8-input priority encoder.
IDLE = (I0 + I1 + I2 + I3 + I4 + I5 + I6 + I7)
= I0 I1 I2 I3 I4 I5 I6 I7
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74x148
5 4 3 2 1
13 12 11 10
Figure 5-48 Logic symbol for the 74x148 8-input priority encoder.
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74x148 EI I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0
6 7 9
GS
14 15
EO
5.5.2 The 74x148 Priority Encoder The 74x148 is a commercially available, MSI 8-input priority encoder. Its logic symbol is shown in Figure 5-48 and its schematic is shown in Figure 5-49. The main difference between this IC and the generic priority encoder of Figure 5-47 is that its inputs and outputs are active low. Also, it has an enable input, EI_L, that must be asserted for any of its outputs to be asserted. The complete truth table is given in Table 5-22. Instead of an IDLE output, the 148 has a GS_L output that is asserted when the device is enabled and one or more of the request inputs is asserted. The manufacturer calls this Group Select, but its easier to remember as Got Something. The EO_L signal is an enable output designed to be connected to the EI_L input of another 148 that handles lower-priority requests. /EO is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority 148 may be enabled. Figure 5-50 shows how four 74x148s can be connected in this way to accept 32 request inputs and produce a 5-bit output, RA4RA0, indicating the highest-priority requestor. Since the A2A0 outputs of at most one 148 will be enabled at any time, the outputs of the individual 148s can be ORed to produce RA2RA0. Likewise, the individual GS_L outputs can be combined in a 4-to-2 encoder to produce RA4 and RA3. The RGS output is asserted if any GS output is asserted.
Ta b l e 5 - 2 2 Truth table for a 74x148 8-input priority encoder.
Inputs
/I3
Outputs
/A0
/EI
/I0
/I1
/I2
/I4
/I5
/I6
/I7
/A2
/A1
/GS
/EO
1 0 0 0 0 0 0 0 0 0
x x x x x x x x 0 1
x x x x x x x 0 1 1
x x x x x x 0 1 1 1
x x x x x 0 1 1 1 1
x x x x 0 1 1 1 1 1
x x x 0 1 1 1 1 1 1
x x 0 1 1 1 1 1 1 1
x 0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 1 1 1 1
1 0 0 1 1 0 0 1 1 1
1 0 1 0 1 0 1 0 1 1
1 0 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 1 0
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I1_L
I2_L
I3_L
I4_L
I5_L
I6_L
I7_L
EI_L
Figure 5-49 Logic diagram for the 74x148 8-input priority encoder, including pin numbers for a standard 16-pin dual in-line package.
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(15)
EO_L
(11)
(14)
GS_L
(12)
(9)
A0_L
(13)
(1)
(2)
(7)
A1_L
(3)
(4)
(6)
A2_L
(5)
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5 4 3 2 1
EI I7
REQ31_L REQ30_L REQ29_L REQ28_L REQ27_L REQ26_L REQ25_L REQ24_L
I6
A2 A1 A0
6 7 9
G3A2_L G3A1_L G3A0_L
I5 I4 I3 I2 I1 I0
13 12 11 10
GS EO
14 15
G3GS_L
G3EO_L
5 4 3 2 1
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74x148
REQ23_L REQ22_L REQ21_L REQ20_L REQ19_L REQ18_L REQ17_L REQ16_L
EI I7
I6
A2 A1 A0
6 7 9
13 12 11 10
I5 I4 I3 I2 I1 I0
G2A2_L G2A1_L G2A0_L
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EI I7
REQ15_L REQ14_L REQ13_L REQ12_L REQ11_L REQ10_L REQ9_L REQ8_L
I6
A2 A1 A0
6 7 9
G1A2_L G1A1_L G1A0_L
1 2 4 5
74x20
13 12 11 10
I5 I4 I3 I2 I1 I0
6
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8
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1 2 4 5
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REQ7_L REQ6_L REQ5_L REQ4_L REQ3_L REQ2_L REQ1_L REQ0_L
EI I7
6
I6
A2 A1 A0
6 7 9
13 12 11 10
I5 I4 I3 I2 I1 I0
G0A2_L G0A1_L G0A0_L
RA0
U7
9
74x20
GS EO
14 15
G0GS_L
10 12 13
8
RGS
U7
U4
Figure 5-50 Four 74x148s cascaded to handle 32 requests.
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Encoders
341
5.5.3 Encoders in ABEL and PLDs Encoders can be designed in ABEL using an explicit equation for each input combinations, as in Table 5-8 on page 323, or using truth tables. However, since the number of inputs is usually large, the number of input combinations is very large, and this method often is not practical. For example, how would we specify a 15-input priority encoder for inputs P0P14? We obviously dont want to deal with all 215 possible input combinations! One way to do it is to decompose the priority function into two parts. First, we write equations for 15 variables Hi (0 i 14) such that Hi is 1 if Pi is the highest-priority asserted input. Since by definition at most one Hi variable is 1 at any time, we can combine the His in a binary encoder to obtain a 4-bit number identifying the highest-priority asserted input. An ABEL program using this approach is shown in Table 5-23, and a logic diagram for the encoder using a single PAL20L8 or GAL20V8 is given in Figure 5-51. Inputs P0P14 are asserted to indicate requests, with P14 having the highest priority. If EN_L (Enable) is asserted, then the Y3_LY0_L outputs give the number (active low) of the highest-priority request, and GS is asserted if any request is present. If EN_L is negated, then the Y3_LY0_L outputs are negated and GS is negated. ENOUT_L is asserted if EN_L is asserted and no request is present. Notice that in the ABEL program, the equations for the Hi variables are written as constant expressions, before the equations declaration. Thus, these signals will not be generated explicitly. Rather, they will be incorporated in the subsequent equations for Y0Y3, which the compiler cranks on to obtain
PAL20L8
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P0 P1 P2 P3 P4 P5 P6 P7 P8 P9
1 2 3 4 5 6 7 8 9
I1 I2 I3 I4 I5 I6 I7 I8 I9
10 11 13
P10 P11 P12 P13
I10 I11
O1 IO2 IO3 IO4 IO5 IO6 IO7 O8
22 21
Figure 5-51 Logic diagram for a PLD-based 15-input priority encoder
20
19 18 17 16 15
ENOUT_L Y0_L Y1_L Y2_L Y3_L
GS
I12 14 I13
23
I14
PRIOR15
P14 EN_L
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module PRIOR15 title '15-Input Priority Encoder J. Wakerly, DAVID Systems, Inc.' PRIOR15 device 'P20L8'; " Input pins P0, P1, P2, P3, P4, P5, P6, P7 P8, P9, P10, P11, P12, P13, P14 !EN " Output pins !Y3, !Y2, !Y1, !Y0 GS, !ENOUT
" Constant expressions H14 = EN&P14; H13 = EN&!P14&P13; H12 = EN&!P14&!P13&P12; H11 = EN&!P14&!P13&!P12&P11; H10 = EN&!P14&!P13&!P12&!P11&P10; H9 = EN&!P14&!P13&!P12&!P11&!P10&P9; H8 = EN&!P14&!P13&!P12&!P11&!P10&!P9&P8; H7 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&P7; H6 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&P6; H5 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&P5; H4 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&P4; H3 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&P3; H2 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&P2; H1 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&!P2&P1; H0 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&!P2&!P1&P0; equations Y3 = H8 # Y2 = H4 # Y1 = H2 # Y0 = H1 #
GS = EN&(P14#P13#P12#P11#P10#P9#P8#P7#P6#P5#P4#P3#P2#P1#P0); ENOUT = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&!P2&!P1&!P0; end PRIOR15
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Ta b l e 5 - 2 3 An ABEL program for a 15-input priority encoder.
pin 1, 2, 3, 4, 5, 6, 7, 8; pin 9, 10, 11, 13, 14, 23, 16; pin 17; pin 18, 19, 20, 21 istype 'com'; pin 15, 22 istype 'com'; H9 H5 H3 H3 # # # # H10 # H11 H6 # H7 # H6 # H7 # H5 # H7 # # H12 # H13 # H14; H12 # H13 # H14; H10 # H11 # H14; H9 # H11 # H13;
minimal sum-of-products expressions. As it turns out, each Yi output has only seven product terms, as you can see from the structure of the equations. The priority encoder can be designed even more intuitively use ABELs WHEN statement. As shown in Table 5-24, a deeply nested series of WHEN statements expresses precisely the logical function of the priority encoder. This program yields exactly the same set of output equations as the previous program.
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Encoders
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module PRIOR15W title '15-Input Priority Encoder' PRIOR15W device 'P20L8'; " Input pins P0, P1, P2, P3, P4, P5, P6, P7 P8, P9, P10, P11, P12, P13, P14 !EN " Output pins !Y3, !Y2, !Y1, !Y0 GS, !ENOUT " Sets Y = [Y3..Y0];
equations WHEN !EN THEN Y = 0; ELSE WHEN P14 THEN Y = 14; ELSE WHEN P13 THEN Y = 13; ELSE WHEN P12 THEN Y = 12; ELSE WHEN P11 THEN Y = 11; ELSE WHEN P10 THEN Y = 10; ELSE WHEN P9 THEN Y = 9; ELSE WHEN P8 THEN Y = 8; ELSE WHEN P7 THEN Y = 7; ELSE WHEN P6 THEN Y = 6; ELSE WHEN P5 THEN Y = 5; ELSE WHEN P4 THEN Y = 4; ELSE WHEN P3 THEN Y = 3; ELSE WHEN P2 THEN Y = 2; ELSE WHEN P1 THEN Y = 1; ELSE WHEN P0 THEN Y = 0; ELSE {Y = 0; ENOUT = 1;};
GS = EN&(P14#P13#P12#P11#P10#P9#P8#P7#P6#P5#P4#P3#P2#P1#P0); end PRIOR15W
5.5.4 Encoders in VHDL The approach to specifying encoders in VHDL is similar to the ABEL approach. We could embed the equivalent of a truth table or explicit equations into the VHDL program, but a behavioral description is far more intuitive. Since VHDLs IF-THEN-ELSE construct best describes prioritization and is available only within a process, we use the process-based behavioral approach. Table 5-25 is a behavioral VHDL program for a priority encoder whose function is equivalent to the 74x148. It uses a FOR loop to look for an asserted
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Ta b l e 5 - 2 4 Alternate ABEL program for the same 15-input priority encoder.
pin 1, 2, 3, 4, 5, 6, 7, 8; pin 9, 10, 11, 13, 14, 23, 16; pin 17; pin 18, 19, 20, 21 istype 'com'; pin 15, 22 istype 'com';
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity V74x148 is port ( EI_L: in STD_LOGIC; I_L: in STD_LOGIC_VECTOR (7 downto 0); A_L: out STD_LOGIC_VECTOR (2 downto 0); EO_L, GS_L: out STD_LOGIC ); end V74x148; architecture V74x148p of V74x148 is signal EI: STD_LOGIC; -- active-high version signal I: STD_LOGIC_VECTOR (7 downto 0); -- active-high version signal EO, GS: STD_LOGIC; -- active-high version signal A: STD_LOGIC_VECTOR (2 downto 0); -- active-high version begin process (EI_L, I_L, EI, EO, GS, I, A) variable j: INTEGER range 7 downto 0; begin EI <= not EI_L; -- convert input I <= not I_L; -- convert inputs EO <= '1'; GS <= '0'; A <= "000"; if (EI)='0' then EO <= '0'; else for j in 7 downto 0 loop if GS = '1' then null; elsif I(j)='1' then GS <= '1'; EO <= '0'; A <= CONV_STD_LOGIC_VECTOR(j,3); end if; end loop; end if; EO_L <= not EO; -- convert output GS_L <= not GS; -- convert output A_L <= not A; -- convert outputs end process; end V74x148p; of of of of
Ta b l e 5 - 2 5 Behavioral VHDL program for a 74x148-like 8-input priority encoder.
input inputs outputs outputs
input, starting with the highest-priority input. Like some of our previous programs, it performs explicit active-level conversion at the beginning and end. Also recall that the CONV_STD_LOGIC_VECTOR(j,n) function was defined in \secref{VHDLconv} to convert from an integer j to a STD_LOGIC_VECTOR of a specified length n. This program is easily modified to use a different priority order or a different number of inputs, or to add more functionality such as finding a second-highest-priority input, as explored in Exercises \exref\exref.
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Three-State Devices
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5.6 Three-State Devices
In Sections 3.7.3 and 3.10.5, we described the electrical design of CMOS and TTL devices whose outputs may be in one of three states0, 1, or Hi-Z. In this section, well show how to use them.
5.6.1 Three-State Buffers The most basic three-state device is a three-state buffer, often called a three-state driver. The logic symbols for four physically different three-state buffers are shown in Figure 5-52. The basic symbol is that of a noninverting buffer (a, b) or an inverter (c, d). The extra signal at the top of the symbol is a three-state enable input, which may be active high (a, c) or active low (b, d). When the enable input is asserted, the device behaves like an ordinary buffer or inverter. When the enable input is negated, the device output floats; that is, it goes to a highimpedance (Hi-Z), disconnected state and functionally behaves as if it werent even there. Three-state devices allow multiple sources to share a single party line, as long as only one device talks on the line at a time. Figure 5-53 gives an example of how this can be done. Three input bits, SSRC2SSRC0, select one of eight sources of data that may drive a single line, SDATA. A 3-to-8 decoder, the 74x138, ensures that only one of the eight SEL lines is asserted at a time, enabling only one three-state buffer to drive SDATA. However, if not all of the EN lines are asserted, then none of the three-state buffers is enabled. The logic value on SDATA is undefined in this case.
Figure 5-52 Various three-state buffers: (a) noninverting, active-high enable; (b) non-inverting, active-low enable; (c) inverting, active-high enable; (d) inverting, active-low enable.
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three-state buffer three-state driver three-state enable
(a) (b) (c) (d)
DEFINING UNDEFINED
The actual voltage level of a floating signal depends on circuit details, such as resistive and capacitive load, and may vary over time. Also, the interpretation of this level by other circuits depends on the input characteristics of those circuits, so its best not to count on a floating signal as being anything other than undefined. Sometimes a pull-up resistor is used on three-state party lines to ensure that a floating value is pulled to a HIGH voltage and interpreted as logic 1. This is especially important on party lines that drive CMOS devices, which may consume excessive current when their input voltage is halfway between logic 0 and 1.
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1-bit party line
Figure 5-53 Eight sources sharing a three-state party line.
fighting
dead time
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P Q 74x138 EN1 5 /EN2 4 /EN3
6
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13 12 11 10 9 7
SSRC0 SSRC1 SSRC2
1
A 2 B 3 C
Y4 Y5 Y6 Y7
/SELP /SELQ /SELR /SELS /SELT /SELU /SELV /SELW
R
SDATA
S
T
U
V
W
Typical three-state devices are designed so that they go into the Hi-Z state faster than they come out of the Hi-Z state. (In terms of the specifications in a data book, tpLZ and tpHZ are both less than tpZL and tpZH; also see Section 3.7.3.) This means that if the outputs of two three-state devices are connected to the same party line, and we simultaneously disable one and enable the other, the first device will get off the party line before the second one gets on. This is important because, if both devices were to drive the party line at the same time, and if both were trying to maintain opposite output values (0 and 1), then excessive current would flow and create noise in the system, as discussed in Section 3.7.7. This is often called fighting. Unfortunately, delays and timing skews in control circuits make it difficult to ensure that the enable inputs of different three-state devices change simultaneously. Even when this is possible, a problem arises if three-state devices from different-speed logic families (or even different ICs manufactured on different days) are connected to the same party line. The turn-on time (tpZL or tpZH) of a fast device may be shorter than the turn-off time (tpLZ or tpHZ) of a slow one, and the outputs may still fight. The only really safe way to use three-state devices is to design control logic that guarantees a dead time on the party line during which no one is driving it.
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347
The dead time must be long enough to account for the worst-case differences between turn-off and turn-on times of the devices and for skews in the three-state control signals. A timing diagram that illustrates this sort of operation for the party line of Figure 5-53 is shown in Figure 5-54. This timing diagram also illustrates a drawing convention for three-state signalswhen in the Hi-Z state, they are shown at an undefined level halfway between 0 and 1.
5.6.2 Standard SSI and MSI Three-State Buffers Like logic gates, several independent three-state buffers may be packaged in a single SSI IC. For example, Figure 5-55 shows the pinouts of 74x125 and 74x126, each of which contains four independent noninverting three-state buffers in a 14-pin package. The three-state enable inputs in the 125 are active low, and in the 126 they are active high. Most party-line applications use a bus with more than one bit of data. For example, in an 8-bit microprocessor system, the data bus is eight bits wide, and peripheral devices normally place data on the bus eight bits at a time. Thus, a peripheral device enables eight three-state drivers to drive the bus, all at the same time. Independent enable inputs, as in the 125 and 126, are not necessary. Thus, to reduce the package size in wide-bus applications, most commonly used MSI parts contain multiple three-state buffers with common enable inputs. For example, Figure 5-56 shows the logic diagram and symbol for a 74x541 octal noninverting three-state buffer. Octal means that the part contains eight
(1) (2) (13) (12) (1) (2) (13) (12)
74x125
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EN1 /EN2, /EN3 SDATA W P Q R S max(tpLZmax, tpHZmax) min(tpZLmin, tpZHmin) dead time
Figure 5-54 Timing diagram for the three-state party line.
74x125 74x126
74x541
(3)
(11)
(3)
(11)
74x126
(4) (5)
(10) (9)
(4) (5)
(10) (9)
Figure 5-55 Pinouts of the 74x125 and 74x126 threestate buffers.
(6)
(8)
(6)
(8)
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74x541
(1)
Figure 5-56 The 74x541 octal three-state buffer: (a) logic diagram, including pin numbers for a standard 20-pin dual in-line package; (b) traditional logic symbol.
Figure 5-57 Using a 74x541 as a microprocessor input port.
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G1_L G2_L
1 19
G1 G2
(19)
2
3 4
A1 A2 A3 A4
Y1 17 Y2 16 Y3
15 14
18
A1
(2)
(18)
Y1
5 6
Y4
A2
(3)
(17)
Y2
A5 7 A6 8 A7
9
Y5 13 Y6 12 Y7 Y8
11
A3
(4)
(16)
Y3
A8
(b)
A4
(5)
(15)
Y4
A5
(6)
(14)
Y5
A6
(7)
(13)
Y6
A7
(8)
(12)
Y7
(a)
A8
(9)
(11)
Y8
Microprocessor
74x541
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
D0 D1 D2 D3 D4 D5 D6 D7
READ INSEL1 INSEL2 INSEL3
1
19
G1 G2
Input Port 1
2
3 4 5 6 7 8 9
User Inputs
A1 A2 A3 A4 A5 A6 A7 A8
Y1 17 Y2 16 Y3
15 14 13 12 11
18
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Y4 Y5 Y6 Y7 Y8
74x541
1
19
G1 G2
Input Port 2
2
A1 A2 A3
3 4 5 6
Y1 17 Y2 Y3
16 15
18
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
User Inputs
A4 A5 7 A6
8 9
Y4 14 Y5 13 Y6 Y7 Y8
12 11
A7 A8
DB[0:7]
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(19) (1)
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A1
A2
A3
A4
A5
A6
A7
A8
individual buffers. Both enable inputs, G1_L and G2_L, must be asserted to enable the devices three-state outputs. The little rectangular symbols inside the buffer symbols indicate hysteresis, an electrical characteristic of the inputs that improves noise immunity, as we explained in Section 3.7.2. The 74x541 inputs typically have 0.4 volts of hysteresis. Figure 5-57 shows part of a microprocessor system with an 8-bit data bus, DB[07], and a 74x541 used as an input port. The microprocessor selects Input Port 1 by asserting INSEL1 and requests a read operation by asserting READ. The selected 74x541 responds by driving the microprocessor data bus with usersupplied input data. Other input ports may be selected when a different INSEL line is asserted along with READ.
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(2) (18)
B1
74x245
19 1
(3)
(17)
G DIR
B2
2
3 4
A1 A2 A3 A4 A5 A6 A7 A8
B1 17 B2 16 B3
15 14 13
18
(4)
(16)
B3
5 6 7 8 9
(5)
(15)
B4
B4 B5 B6 B7 B8
12 11
(b)
(6)
(14)
B5
(7)
(13)
B6
(8)
(12)
B7
(9)
(11)
B8
(a)
Figure 5-58 The 74x245 octal three-state transceiver: (a) logic diagram; (b) traditional logic symbol.
octal
hysteresis
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Figure 5-59 Bidirectional buses and transceiver operation.
74x540 74x240 74x241 bus transceiver
74x245
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Bus A 74x245 ENTFR_L ATOB
19 1
Control Circuits
G DIR A1 A2 A3 A4 A5 A6 A7 A8
2
3 4
5 6 7 8 9
B1 B2 B3 B4 B5 B6 B7 B8
18 17 16 15 14 13
12 11
Bus B
Many other varieties of octal three-state buffers are commercially available. For example, the 74x540 is identical to the 74x541 except that it contains inverting buffers. The 74x240 and 74x241 are similar to the 540 and 541, except that they are split into two 4-bit sections, each with a single enable line. A bus transceiver contains pairs of three-state buffers connected in opposite directions between each pair of pins, so that data can be transferred in either direction. For example, Figure 5-58 on the preceding page shows the logic diagram and symbol for a 74x245 octal three-state transceiver. The DIR input
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ENTFR_L
determines the direction of transfer, from A to B (DIR = 1) or from B to A (DIR = 0). The three-state buffer for the selected direction is enabled only if G_L is asserted. A bus transceiver is typically used between two bidirectional buses, as shown in Figure 5-59. Three different modes of operation are possible, depending on the state of G_L and DIR, as shown in Table 5-26. As usual, it is the designers responsibility to ensure that neither bus is ever driven simultaneously by two devices. However, independent transfers where both buses are driven at the same time may occur when the transceiver is disabled, as indicated in the last row of the table.
5.6.3 Three-State Outputs in ABEL and PLDs The combinational-PLD applications in previous sections have used the bidirectional I/O pins (IO2IO7 on a PAL16L8 or GAL16V8) statically, that is, always output-enabled or always output-disabled. In such applications, the compiler can take care of programming the output-enable gates appropriatelyall fuses blown, or all fuses intact. By default in ABEL, a three-state output pin is programmed to be always enabled if its signal name appears on the left-hand side of an equation, and always disabled otherwise. Three-state output pins can also be controlled dynamically, by a single input, by a product term, or, using two-pass logic, by a more complex logic expression. In ABEL, an attribute suffix .OE is attached to a signal name on the left-hand side of an equation to indicate that the equation applies to the outputenable for the signal. In a PAL16L8 or GAL16V8, the output enable is controlled by a single AND gate, so the right-hand side of the enable equation must reduce to a single product term. Table 5-27 shows a simple PLD program fragment with three-state control. Adapted from the program for a 74x138-like decoder on Table 5-8, this program includes a three-state output control OE for all eight decoder outputs. Notice that a set Y is defined to allow all eight output enables to be specified in a single equation; the .OE suffix is applied to each member of the set. In the preceding example, the output pins Y0Y7 are always either enabled or floating, and are used strictly as output pins. I/O pins (IO2IO7 in a 16L8 or 16V8) can be used as bidirectional pins; that is, they can be used dynamically
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Ta b l e 5 - 2 6 Modes of operation for a pair of bidirectional buses.
ATOB
Operation
0
0
Transfer data from a source on bus B to a destination on bus A. Transfer data from a source on bus A to a destination on bus B. Transfer data on buses A and B independently.
0 1
1 x
bidirectional bus
.OE attribute suffix
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module Z74X138T title '74x138 Decoder with Three-State Output Enable' Z74X138T device 'P16L8'; " Input pins A, B, C, !G2A, !G2B, G1, !OE " Output pins !Y0, !Y1, !Y2, !Y3 !Y4, !Y5, !Y6, !Y7 " Constant expression ENB = G1 & G2A & G2B; Y = [Y0..Y7]; pin 1, 2, 3, 4, 5, 6, 7; pin 19, 18, 17, 16 istype 'com'; pin 15, 14, 13, 12 istype 'com'; equations Y.OE = OE; Y0 = ENB & !C & !B & !A; ... Y7 = ENB & C & B & A; end Z74X138T
Ta b l e 5 - 2 7 ABEL program for a 74x138-like 3-to-8 binary decoder with three-state output control.
as inputs or outputs depending on whether the output-enable gate is producing a 0 or a 1. An example application of I/O pins is a four-way, 2-bit bus transceiver with the following specifications: The transceiver handles four 2-bit bidirectional buses, A[1:2], B[1:2], C[1:2], and D[1:2]. The source of data to drive the buses is selected by three select inputs, S[2:0], according to Table 5-28. If S2 is 0, the buses are driven with a constant value, otherwise they are driven with one of the other buses. However, when the selected source is a bus, the source bus is driven with 00.
Ta b l e 5 - 2 8 Bus selection codes for a four-way bus transceiver.
Source selected
S2
S1
S0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
00 01 10 11 A bus B bus C bus D bus
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module XCVR4X2 title 'Four-way 2-bit Bus Transceiver' XCVR4X2 device 'P16L8'; " Input pins A1I, A2I !AOE, !BOE, !COE, !DOE, !MOE S0, S1, S2 " Output and bidirectional pins A1O, A2O B1, B2, C1, C2, D1, D2 " Set definitions ABUSO = [A1O,A2O]; ABUSI = [A1I,A2I]; BBUS = [B1,B2]; CBUS = [C1,C2]; DBUS = [D1,D2]; SEL = [S2,S1,S0]; CONST = [S1,S0]; " Constants SELA = [1,0,0]; SELB = [1,0,1]; SELC = [1,1,0]; SELD = [1,1,1];
equations ABUSO.OE = AOE & MOE; BBUS.OE = BOE & MOE; CBUS.OE = COE & MOE; DBUS.OE = DOE & MOE; ABUSO = !S2&CONST # (SEL==SELB)&BBUS BBUS = !S2&CONST # (SEL==SELA)&ABUSI CBUS = !S2&CONST # (SEL==SELA)&ABUSI DBUS = !S2&CONST # (SEL==SELA)&ABUSI end XCVR4X2
Each bus has its own output-enable signal, AOE_L, BOE_L, COE_L, or DOE_L. There is also a master output-enable signal, MOE_L. The transceiver drives a particular bus if and only if MOE_L and the output-enable signal for that bus are both asserted. Table 5-29 is an ABEL program that performs the transceiver function. According to the enable (.OE ) equations, each bus is output-enabled if MOE and its own OE are asserted. Each bus is driven with S1 and S0 if S2 is 0, and with
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Ta b l e 5 - 2 9 An ABEL program for four-way, 2-bit bus transceiver.
pin 1, 11; pin 2, 3, 4, 5, 6; pin 7, 8, 9; pin 19, 12 istype 'com'; pin 18, 17, 16, 15, 14, 13 istype 'com'; # # # # (SEL==SELC)&CBUS (SEL==SELC)&CBUS (SEL==SELB)&BBUS (SEL==SELB)&BBUS # # # # (SEL==SELD)&DBUS; (SEL==SELD)&DBUS; (SEL==SELD)&DBUS; (SEL==SELC)&CBUS;
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PAL16L8
PACKAGE std_logic_1164 IS -- logic state system (unresolved) TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care );
-- unconstrained array of std_ulogic TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; -- resolution function FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; -- *** industry standard logic type *** SUBTYPE std_logic IS resolved std_ulogic; ...
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1 2 3 4 5 6 7 8 9
AOE_L BOE_L COE_L DOE_L
Figure 5-60 PLD inputs and outputs for a four-way, 2-bit bus transceiver.
MOE_L S0 S1 S2
11
I1 I2 I3 I4 I5 I6 I7 I8 I9 I10
O1 IO2 IO3 IO4 IO5 IO6 IO7 O8
19 18 17 16 15 14 13 12
A1 B1 B2 C1 C2 D1 D2 A2
XCVR4X2
the selected bus if a different bus is selected. If the bus itself is selected, the output equation evaluates to 0, and the bus is driven with 00 as required. Figure 5-60 is a logic diagram for a PAL16L8 (or GAL16V8) with the required inputs and outputs. Since the device has only six bidirectional pins and the specification requires eight, the A bus uses one pair of pins for input and another for output. This is reflected in the program by the use of separate signals and sets for the A-bus input and output.
T a b l e 5 - 3 0 IEEE 1164 package declarations for STD_ULOGIC and STD_LOGIC.
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PACKAGE BODY std_logic_1164 IS -- local type TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -- resolution function CONSTANT resolution_table : stdlogic_table := ( ----------------------------------------------------------|U X 0 1 Z W L H | | ---------------------------------------------------------( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | );
...
*5.6.4 Three-State Outputs in VHDL VHDL itself does not have built-in types and operators for three-state outputs. However, it does have primitives which can be used to create signals and systems with three-state behavior; the IEEE 1164 package uses these primitives. As a start, as we described in \secref{VHDL1164}, the IEEE 1164 STD_LOGIC type defines 'Z' as one of its nine possible signal values; this value is used for the high-impedance state. You can assign this value to any STD_LOGIC signal, and the definitions of the standard logic functions account for the possibility of 'Z' inputs (generally a 'Z' input will cause a 'U' output).
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Ta b l e 5 - 3 1 IEEE 1164 package body for STD_ULOGIC and STD_LOGIC.
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved;
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subtype STD_ULOGIC unresolved type resolution function
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Given the availability of three-state signals, how do we create three-state buses in VHDL? A three-state bus generally has two or more drivers, although the mechanisms we discuss work fine with just one driver. In VHDL, there is no explicit language construct for joining three-state outputs into a bus. Instead, the compiler automatically joins together signals that are driven in two or more different processes, that is, signals that appear on the left-hand side of a signal assignment statement in two or more processes. However, the signals must have the appropriate type, as explained below. The IEEE 1164 STD_LOGIC type is actually defined as a subtype of an unresolved type, STD_ULOGIC. In VHDL, an unresolved type is used for any signal that may be driven in two or more processes. The definition of an unresolved type includes a resolution function that is called every time an assignment is made to a signal having that type. As the name implies, this function resolves the value of the signal when it has multiple drivers. Tables 5-30 and 5-31 show the IEEE 1164 definitions of STD_ULOGIC, STD_LOGIC and the resolution function resolved. This code uses a two-dimensional array resolution_table to determine the final STD_LOGIC value produced by n processes that drive a signal to n possibly different values passed in the input vector s. If, for example, a signal has four drivers, the VHDL compiler automatically constructs a 4-element vector containing the four driven values, and passes this vector to resolved every time that any one of those values changes. The result is passed back to the simulation. Notice that the order in which the driven signal values appear in s does not affect the result produced by resolved, due to the strong ordering of strengths in the resolution_table: 'U' > 'X' > '0,1' > 'W' > 'L,H' > '-'. That is, once a signal is partially resolved to a particular value, it never further resolves to a weaker value; and 0/1 and L/H conflicts always resolve to a stronger undefined value ('X' or 'W'). So, do you need to know all of this in order to use three-state outputs in VHDL? Well, usually not, but it can help if your simulations dont match up with reality. All thats normally required to use three-state outputs within VHDL is to declare the corresponding signals as type STD_ULOGIC. For example, Table 5-32 describes a system that uses four 8-bit three-state drivers (in four processes) to select one of four 8-bit buses, A, B, C, and D, to drive onto a result bus X. Within each process, the IEEE 1164 standard function To_StdULogicVector is used to convert the input type of STD_LOGIC_VECTOR to STD_ULOGIC_VECTOR as required to make a legal assignment to result bus X. VHDL is flexible enough that you can use it to define other types of bus operation. For example, you could define a subtype and resolution function for open-drain outputs such that a wired-AND function is obtained. However, the definitions for specific output types in PLDs, FPGAs, and ASICs are usually already done for you in libraries provided by the component vendors.
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library IEEE; use IEEE.std_logic_1164.all;
entity V3statex is port ( G_L: in STD_LOGIC; -SEL: in STD_LOGIC_VECTOR (1 downto 0); -A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -X: out STD_ULOGIC_VECTOR (1 to 8) -); end V3statex;
architecture V3states of V3statex is constant ZZZZZZZZ: STD_ULOGIC_VECTOR := ('Z','Z','Z','Z','Z','Z','Z','Z'); begin process (G_L, SEL, A) begin if G_L='0' and SEL = "00" then X <= To_StdULogicVector(A); else X <= ZZZZZZZZ; end if; end process; process (G_L, SEL, B) begin if G_L='0' and SEL = "01" then X <= To_StdULogicVector(B); else X <= ZZZZZZZZ; end if; end process; process (G_L, SEL, C) begin if G_L='0' and SEL = "10" then X <= To_StdULogicVector(C); else X <= ZZZZZZZZ; end if; end process; process (G_L, SEL, D) begin if G_L='0' and SEL = "11" then X <= To_StdULogicVector(D); else X <= ZZZZZZZZ; end if; end process; end V3states;
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Ta b l e 5 - 3 2 VHDL program with four 8-bit three-state drivers.
Global output enable Input select 0,1,2,3 ==> A,B,C,D Input buses Output bus (three-state)
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multiplexer
mux
Figure 5-61 Multiplexer structure: (a) inputs and outputs; (b) functional equivalent.
(a)
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5.7 Multiplexers
n1
A multiplexer is a digital switchit connects data from one of n sources to its output. Figure 5-61(a) shows the inputs and outputs of an n-input, b-bit multiplexer. There are n sources of data, each of which is b bits wide, and there are b output bits. In typical commercially available multiplexers, n = 1, 2, 4, 8, or 16, and b = 1, 2, or 4. There are s inputs that select among the n sources, so s = log2 n. An enable input EN allows the multiplexer to do its thing; when EN = 0, all of the outputs are 0. A multiplexer is often called a mux for short. Figure 5-61(b) shows a switch circuit that is roughly equivalent to the multiplexer. However, unlike a mechanical switch, a multiplexer is a unidirectional device: information flows only from inputs (on the left) to outputs (on the right). We can write a general logic equation for a multiplexer output: iY =
j=0
EN M j iDj
Here, the summation symbol represents a logical sum of product terms. Variable iY is a particular output bit (1 i b), and variable iDj is input bit i of source j (0 j n 1). Mj represents minterm j of the s select inputs. Thus, when the multiplexer is enabled and the value on the select inputs is j, each output iY equals the corresponding bit of the selected input, iDj. Multiplexers are obviously useful devices in any application in which data must be switched from multiple sources to a destination. A common application in computers is the multiplexer between the processors registers and its arithmetic logic unit (ALU). For example, consider a 16-bit processor in which
(b) 1D0 1D1
1Y
1Dn1
multiplexer
enable select
EN
2D0 2D1
s
2Y
SEL
2Dn1
b b
D0
n data sources
D1
b
Y
data output
bD0 bD1
b
bY
Dn1
bDn1
SEL
EN
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each instruction has a 3-bit field that specifies one of eight registers to use. This 3-bit field is connected to the select inputs of an 8-input, 16-bit multiplexer. The multiplexers data inputs are connected to the eight registers, and its data outputs are connected to the ALU to execute the instruction using the selected register. 5.7.1 Standard MSI Multiplexers The sizes of commercially available MSI multiplexers are limited by the number of pins available in an inexpensive IC package. Commonly used muxes come in 16-pin packages. At one extreme is the 74x151, shown in Figure 5-62, which selects among eight 1-bit inputs. The select inputs are named C, B, and A, where C is most significant numerically. The enable input EN_L is active low; both active-high (Y) and active-low (Y_L) versions of the output are provided.
(7)
EN_L
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74x151
D0
(4)
A A B B C C
D1
(3)
Figure 5-62 The 74x151 8-input, 1-bit multiplexer: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.
D2
(2)
D3
(1)
(5) (6)
Y
D4
(15)
Y_L
D5
(14)
74x151
7
D6
(13)
EN
11
A
10 9
D7
(12)
B C 4 D0 3 D1
2 1
Y Y
5
6
D2
A
(11)
B
(10)
D3 D4 14 D5 13 D6
15 12
D7
C
(9)
(a)
(b)
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Ta b l e 5 - 3 3 Truth table for a 74x151 8-input, 1-bit multiplexer.
Inputs
C
Outputs
EN_L
B
A
Y
Y_L
1 0
x 0
x 0
x 0
0
1
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 0 0 0
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
Figure 5-63 The 74x157 2-input, 4-bit multiplexer: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.
(b)
15
(a)
G_L S
(15) (1)
74x157
G
1
2 3 5 6
1A
(2)
11 10 14 13
(4)
1B
(3)
1Y
S 1A 1B 2A 2B 3A 3B 4A 4B
1Y 2Y 3Y 4Y
4
7
9
12
2A
(5)
(7)
2B
(6)
2Y
3A
(11)
(9)
3B
(10)
3Y
4A
(14)
(12)
4B
(13)
4Y
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The 74x151s truth table is shown in Table 5-33. Here we have once again extended our notation for truth tables. Up until now, our truth tables have specified an output of 0 or 1 for each input combination. In the 74x151s table, only a few of the inputs are listed under the Inputs heading. Each output is specified as 0, 1, or a simple logic function of the remaining inputs (e.g., D 0 or D0). This notation saves eight columns and eight rows in the table, and presents the logic function more clearly than a larger table would. At the other extreme of muxes in 16-pin packages, we have the 74x157, shown in Figure 5-63, which selects between two 4-bit inputs. Just to confuse things, the manufacturer has named the select input S and the active-low enable input G_L. Also note that the data sources are named A and B instead of D0 and D1 as in our generic example. Our extended truth-table notation makes the 74x157s description very compact, as shown in Table 5-34. Intermediate between the 74x151 and 74x157 is the 74x153 , a 4-input, 2-bit multiplexer. This device, whose logic symbol is shown in Figure 5-64, has separate enable inputs (1G, 2G) for each bit. As shown in Table 5-35, its function is very straightforward.
Inputs Outputs
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G_L S 1Y 2Y 3Y 4Y
1 0 0
x 0 1
0
0
0
0
Ta b l e 5 - 3 4 Truth table for a 74x157 2-input, 4-bit multiplexer.
1A 1B
2A 2B
3A 3B
4A 4B
74x157
74x153
1G_L
2G_L
B
A
1Y
2Y
0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1 x
0 1 0 1 0 1 0 1 0 1 0 1 x
1C0 1C1 1C2 1C3 1C0 1C1 1C2 1C3
2C0 2C1 2C2 2C3
Ta b l e 5 - 3 5 Truth table for a 74x153 4-input, 2-bit multiplexer.
Figure 5-64 Traditional logic symbol for the 74x153.
74x153
14
A
2
0 0 0 0
1 6
B 1G
5 4
1C0 1C1
0 0 0 0 0
2C0 2C1 2C2 2C3
1C2 3 1C3
1Y
7
15 10
2G 2C0 11 2C1
12
0
2C2 13 2C3
2Y
9
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74x251
74x253 74x257
CONTROL-SIGNAL FANOUT IN ASICS
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Copyright 1999 by John F. Wakerly
Some multiplexers have three-state outputs. The enable input of such a multiplexer, instead of forcing the outputs to zero, forces them to the Hi-Z state. For example, the 74x251 is identical to the 151 in its pinout and its internal logic design, except that Y and Y_L are three-state outputs. When the EN_L input is negated, instead of forcing the outputs to be negated, it forces the outputs into the high-Z state. Similarly, the 74x253 and 74x257 are three-state versions of the 153 and 157. The three-state outputs are especially useful when n-input muxes are combined to form larger muxes, as suggested in the next subsection.
5.7.2 Expanding Multiplexers Seldom does the size of an MSI multiplexer match the characteristics of the problem at hand. For example, we suggested earlier that an 8-input, 16-bit multiplexer might be used in the design of a computer processor. This function could be performed by 16 74x151 8-input, 1-bit multiplexers or equivalent ASIC cells, each handling one bit of all the inputs and the output. The processors 3-bit register-select field would be connected to the A, B, and C inputs of all 16 muxes, so they would all select the same register source at any given time. The device that produces the 3-bit register-select field in this example must have enough fanout to drive 16 loads. With 74LS-series ICs this is possible because typical devices have a fanout of 20 LS-TTL loads. Still, it is fortunate that the 151 was designed so that each of the A, B, and C inputs presents only one LS-TTL load to the circuit driving it. Theoretically, the 151 could have been designed without the first rank of three inverters shown on the select inputs in Figure 5-62, but then each select input would have presented five LS-TTL loads, and the drivers in the register-select application would need a fanout of 80. Another dimension in which multiplexers can be expanded is the number of data sources. For example, suppose we needed a 32-input, 1-bit multiplexer. Figure 5-65 shows one way to build it. Five select bits are required. A 2-to-4 decoder (one-half of a 74x139) decodes the two high-order select bits to enable one of four 74x151 8-input multiplexers. Since only one 151 is enabled at a time, the 151 outputs can simply be ORed to obtain the final output.
Just the sort of fanout consideration that we described above occurs quite frequently in ASIC design. When a set of control signals, such as the register-select field in the example, controls a large number of bits, the required fanout can be enormous. In CMOS chips, the consideration is not DC loading but capacitive load which slows down performance. In such an application, the designer must carefully partition the load and select points at which to buffer the control signals to reduce fanout. While inserting the extra buffers, the designer must be careful not increase the chip area significantly or to put so many buffers in series that their delay is unacceptable.
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XA0 XA1 XA2 X0 X1 X2 X3 X4 X5 X6 X7
XEN_L XA3 XA4
X8 X9 X10 X11 X12 X13 X14 X15
X16 X17 X18 X19 X20 X21 X22 X23
X24 X25 X26 X27 X28 X29 X30 X31
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EN
11
10
9 4 3 2 1
15 14 13 12
A B C D0 D1 D2 D3 D4 D5 D6 D7
Y Y
5
6
XO0_L
1/2 74x139
U2
1
1G 1A 1B
2 3
1Y0 1Y1 1Y2 1Y3
EN0_L 5 EN1_L 6 EN2_L 7 EN3_L
4
74x151
7
EN
11
10
U1
9 4 3 2 1
15 14 13 12
A B C D0 D1 D2 D3 D4 D5 D6 D7
Y Y
5
6
XO1_L
1 2 4 5
1/2 74x20
U3
6
XOUT
74x151
U6
7
EN
11
10
9 4 3 2 1
15 14 13 12
A B C D0 D1 D2 D3 D4 D5 D6 D7
Y Y
5
6
XO2_L
U4
74x151
7
EN
11
10
9 4 3 2 1
A B C D0 D1 D2 D3
Y Y
5
6
XO3_L
15
D4 14 D5 13 D6 12 D7
Figure 5-65 Combining 74x151s to make a 32-to-1 multiplexer.
U5
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Figure 5-66 A multiplexer driving a bus and a demultiplexer receiving the bus: (a) switch equivalent; (b) block diagram symbols.
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TURN ON THE BUBBLE MACHINE The use of bubble-to-bubble logic design should help your understanding of these multiplexer design examples. Since the decoder outputs and the multiplexer enable inputs are all active low, they can be hooked up directly. You can ignore the inversion bubbles when thinking about the logic function that is performedyou just say that when a particular decoder output is asserted, the corresponding multiplexer is enabled. Bubble-to-bubble design also provides two options for the final OR function in Figure 5-65. The most obvious design would have used a 4-input OR gate connected to the Y outputs. However, for faster operation, we used an inverting gate, a 4-input NAND connected to the /Y outputs. This eliminated the delay of two invertersthe one used inside the 151 to generate Y from /Y , and the extra inverter circuit that is used to obtain an OR function from a basic NOR circuit in a CMOS or TTL OR gate.
(a) multiplexer demultiplexer SRCA SRCB DSTA DSTB SRCC BUS DSTC SRCZ DSTZ SRCSEL DSTSEL (b) SRCA SRCB SRCC SRCZ MUX BUS DMUX DSTA DSTB DSTC DSTZ SRCSEL DSTSEL
The 32-to-1 multiplexer can also be built using 74x251s. The circuit is identical to Figure 5-65, except that the output NAND gate is eliminated. Instead, the Y (and, if desired, Y_L) outputs of the four 251s are simply tied together. The 139 decoder ensures that at most one of the 251s has its threestate outputs enabled at any time. If the 139 is disabled (XEN_L is negated), then all of the 251s are disabled, and the XOUT and XOUT_L outputs are undefined. However, if desired, resistors may be connected from each of these signals to +5 volts to pull the output HIGH in this case.
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5.7.3 Multiplexers, Demultiplexers, and Buses A multiplexer can be used to select one of n sources of data to transmit on a bus. At the far end of the bus, a demultiplexer can be used to route the bus data to one of m destinations. Such an application, using a 1-bit bus, is depicted in terms of our switch analogy in Figure 5-66(a). In fact, block diagrams for logic circuits often depict multiplexers and demultiplexers using the wedge-shaped symbols in (b), to suggest visually how a selected one of multiple data sources gets directed onto a bus and routed to a selected one of multiple destinations. The function of a demultiplexer is just the inverse of a multiplexers. For example, a 1-bit, n-output demultiplexer has one data input and s inputs to select one of n = 2s data outputs. In normal operation, all outputs except the selected one are 0; the selected output equals the data input. This definition may be generalized for a b-bit, n-output demultiplexer; such a device has b data inputs, and its s select inputs choose one of n = 2s sets of b data outputs. A binary decoder with an enable input can be used as a demultiplexer, as shown in Figure 5-67. The decoders enable input is connected to the data line, and its select inputs determine which of its output lines is driven with the data bit. The remaining output lines are negated. Thus, the 74x139 can be used as a 2-bit, 4-output demultiplexer with active-low data inputs and outputs, and the 74x138 can be used as a 1-bit, 8-output demultiplexer. In fact, the manufacturers catalog typically lists these ICs as decoders/demultiplexers.
(a) 2-to-4 decoder G A B Y0 Y1 Y2 Y3 (b)
Figure 5-67 Using a 2-to-4 binary decoder as a 1-bit, 4-output demultiplexer: (a) generic decoder; (b) 74x139.
5.7.4 Multiplexers in ABEL and PLDs Multiplexers are very easy to design using ABEL and combinational PLDs. For example, the function of a 74x153 4-input, 2-bit multiplexer can be duplicated in a PAL16L8 as shown in Figure 5-68 and Table 5-36. Several characteristics of the PLD-based design and program are worth noting:
Signal names in the ABEL program are changed slightly from the signal names shown for a 74x153 in Figure 5-64 on page 361, since ABEL does not allow a number to be used as the first character of a signal name. A 74x153 has twelve inputs, while a PAL16L8 has only ten inputs. Therefore, two of the 153 inputs are assigned to 16L8 I/O pins, which are no longer usable as outputs.
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demultiplexer
1/2 74x139 SRCDATA DSTSEL0 DSTSEL1 DST0DATA DST1DATA DST2DATA DST3DATA SRCDATA_L DSTSEL0 DSTSEL1 G A B Y0 Y1 Y2 Y3
DST0DATA_L DST1DATA_L DST2DATA_L DST3DATA_L
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A B
Ta b l e 5 - 3 6 ABEL program for a 74x153-like 4-input, 2-bit multiplexer.
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PAL16L8 G1_L C10 C11 C12 C13
1 2 3 4 5 6 7 8 9
Figure 5-68 Logic diagram for the PAL16L8 used as a 74x153-like multiplexer.
G2_L C20 C21 C22 C23
11
I1 I2 I3 I4 I5 I6 I7 I8 I9 I10
O1 IO2 IO3 IO4 IO5 IO6 IO7 O8
19 18 17 16
Y1
15 14 13
N.C. N.C. N.C. N.C.
12
Y2
Z74X153
The 153 outputs (1Y and 2Y) are assigned to pins 19 and 12 on the 16L8, which are usable only as outputs. This is preferable to assigning them to I/ O pins; given a choice, its better to leave I/O pins than output-only pins as spares. Although the multiplexer equations in the table are written quite naturally in sum-of-products form, they dont map directly onto the 16L8s structure
module Z74X153 title '74x153-like multiplexer PLD J. Wakerly, Stanford University' Z74X153 device 'P16L8'; " Input pins A, B, !G1, !G2 C10, C11, C12, C13 C20, C21, C22, C23 " Output pins Y1, Y2
pin 17, 18, 1, 6; pin 2, 3, 4, 5; pin 7, 8, 9, 11;
pin 19, 12 istype 'com';
equations Y1 = G1 & ( !B & !A & # !B & A & # B & !A & # B& A& Y2 = G2 & ( !B & !A & # !B & A & # B & !A & # B& A& end Z74X153
C10 C11 C12 C13); C20 C21 C22 C23);
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Multiplexer functions are even easier to expression using ABELs sets and relations. For example, Table 5-38 shows the ABEL program for a 4-input, 8-bit multiplexer. No device statement is included, because this function has too many inputs and outputs to fit in any of the PLDs weve described so far. However, its quite obvious that a multiplexer of any size can be specified in just a few lines of code in this way.
module mux4in8b title '4-input, 8-bit wide multiplexer PLD' " Input and output pins !G pin; S1..S0 pin; A1..A8, B1..B8, C1..C8, D1..D8 pin; Y1..Y8 pin istype 'com'; " Sets SEL = [S1..S0]; A = [A1..A8]; B = [B1..B8]; C = [C1..C8]; D = [D1..D8]; Y = [Y1..Y8];
equations Y.OE = G; WHEN (SEL == 0) THEN ELSE WHEN (SEL == 1) ELSE WHEN (SEL == 2) ELSE WHEN (SEL == 3) end mux4in8b
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!Y1 = (!B & !A # !B & A # B & !A # B& A # G1); !Y2 = (!B & !A # !B & A # B & !A # B& A # G2); & & & & & & & & !C10 !C11 !C12 !C13 !C20 !C21 !C22 !C23
Ta b l e 5 - 3 7 Inverted, reduced equations for 74x153like 4-input, 2-bit multiplexer.
because of the inverter between the AND -OR array and the actual output pins. Therefore, the ABEL compiler must complement the equations in the table and then reduce the result to sum-of-products form. With a GAL16V8, either version of the equations could be used.
Ta b l e 5 - 3 8 ABEL program for a 4-input, 8-bit multiplexer.
" " " "
Output enable for Y bus Select inputs, 0-3 ==> A-D 8-bit input buses A, B, C, D 8-bit three-state output bus
Y = A; THEN Y = B; THEN Y = C; THEN Y = D;
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Ta b l e 5 - 3 9 Function table for a specialized 4-input, 18-bit multiplexer.
S2 S1 S0
Input to Select
A B A C A D A B
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Likewise, it is easy to customize multiplexer functions using ABEL. For example, suppose that you needed a circuit that selects one of four 18-bit input buses, A, B, C , or D, to drive a 18-bit output bus F, as specified in Table 5-39 by three control bits. There are more control-bit combinations than multiplexer inputs, so a standard 4-input multiplexer doesnt quite fit the bill (but see Exercise \exref). A 4-input, 3-bit multiplexer with the required behavior can be designed to fit into a single PAL16L8 or GAL16V8 as shown in Figure 5-69 and Table 5-40, and six copies of this device can be used to make the 18-bit mux. Alternatively, a single, larger PLD could be used. In any case, the ABEL program is very easily modified for different selection criteria. Since this function uses all of the available pins on the PAL16L8, we had to make the pin assignment in Figure 5-69 carefully. In particular, we had to assign two output signals to the two output-only pins (O1 and O8), to maximize the number of input pins available.
S0 S1 S2
Figure 5-69 Logic diagram for the PAL16L8 used as a specialized 4-input, 3-bit multiplexer.
PAL16L8
A0 A1 A2 B0 B1 B2 C0 C1 C2 D0 D1 D2
1 2 3 4 5 6 7 8 9
11
I1 I2 I3 I4 I5 I6 I7 I8 I9 I10
O1 IO2 IO3 IO4 IO5 IO6 IO7 O8
19 18 17 16 15 14 13 12
F0
F1
F2
MUX4IN3B
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module mux4in3b title 'Specialized 4-input, 3-bit Multiplexer' mux4in3b device 'P16L8'; " Input and output pins S2..S0 A0..A2, B0..B2, C0..C2, D0..D2 F0..F2 " Sets SEL = [S2..S0]; A = [A0..A2]; B = [B0..B2]; C = [C0..C2]; D = [D0..D2]; F = [F0..F2];
equations WHEN (SEL== 0) # ELSE WHEN (SEL== ELSE WHEN (SEL== ELSE WHEN (SEL== end mux4in3b
5.7.5 Multiplexers in VHDL Multiplexers are very easy to describe in VHDL. In the dataflow style of architecture, the SELECT statement provides the required functionality, as shown in Table 5-41, the VHDL description of 4-input, 8-bit multiplexer. In a behavioral architecture, a CASE statement is used. For example, Table 5-42 shows a process-based architecture for the same mux4in8b entity. As in ABEL, it is very easy to customize the selection criteria in a VHDL multiplexer program. For example, Table 5-43 is a behavioral-style program for a specialized 4-input, 18-bit multiplexer with the selection criteria of Table 5-39. In each example, if the select inputs are not valid (e.g., contain Us or Xs), the output bus is set to unknown to help catch errors during simulation.
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Ta b l e 5 - 4 0 ABEL program for a specialized 4-input, 3-bit multiplexer.
pin 16..18; " Select inputs pin 1..9, 11, 13, 14; " Bus inputs pin 19, 15, 12 istype 'com'; " Bus outputs (SEL== 2) # 1) # (SEL== 3) THEN F = 5) THEN F = (SEL== 4) # (SEL== 6) THEN F = A; 7) THEN F = B; C; D;
EASIEST, BUT NOT CHEAPEST
As youve seen, its very easy to program a PLD to perform decoder and multiplexer functions. Still, if you need the logic function of a standard decoder or multiplexer, its usually less costly to use a standard MSI chip than it is to use a PLD. The PLDbased approach is best if the multiplexer has some nonstandard functional requirements, or if you think you may have to change its function as a result of debugging.
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Exclusive OR (XOR) Exclusive NOR (XNOR) Equivalence
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Ta b l e 5 - 4 1 Dataflow VHDL program for a 4-input, 8-bit multiplexer.
library IEEE; use IEEE.std_logic_1164.all; architecture mux4in8b of mux4in8b is begin with S select Y <= A when "00", B when "01", C when "10", D when "11", (others => 'U') when others; -- this creates an 8-bit vector of 'U' end mux4in8b;
entity mux4in8b is port ( S: in STD_LOGIC_VECTOR (1 downto 0); -- Select inputs, 0-3 ==> A-D A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Data bus input Y: out STD_LOGIC_VECTOR (1 to 8) -- Data bus output ); end mux4in8b;
Ta b l e 5 - 4 2 Behavioral architecture for a 4-input, 8-bit multiplexer.
architecture mux4in8p of mux4in8b is begin process(S, A, B, C, D) begin case S is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when "11" => Y <= D; when others => Y <= (others => 'U'); end case; end process; end mux4in8p;
-- 8-bit vector of 'U'
5.8 EXCLUSIVE OR Gates and Parity Circuits
5.8.1 EXCLUSIVE OR and EXCLUSIVE NOR Gates An Exclusive OR (XOR) gate is a 2-input gate whose output is 1 if exactly one of its inputs is 1. Stated another way, an XOR gate produces a 1 output if its inputs are different. An Exclusive NOR (XNOR) or Equivalence gate is just the oppositeit produces a 1 output if its inputs are the same. A truth table for these
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library IEEE; use IEEE.std_logic_1164.all;
entity mux4in3b is port ( S: in STD_LOGIC_VECTOR (2 downto 0); -- Select inputs, 0-7 ==> ABACADAB A, B, C, D: in STD_LOGIC_VECTOR (1 to 18); -- Data bus inputs Y: out STD_LOGIC_VECTOR (1 to 18) -- Data bus output ); end mux4in3b; architecture mux4in3p of mux4in3b is begin process(S, A, B, C, D) variable i: INTEGER; begin case S is when "000" | "010" | "100" | "110" => Y <= A; when "001" | "111" => Y <= B; when "011" => Y <= C; when "101" => Y <= D; when others => Y <= (others => 'U'); -- 18-bit vector of 'U' end case; end process; end mux4in3p;
functions is shown in Table 5-44. The XOR operation is sometimes denoted by the symbol , that is,
X Y = X Y + X Y
Although EXCLUSIVE OR is not one of the basic functions of switching algebra, discrete XOR gates are fairly commonly used in practice. Most switching technologies cannot perform the XOR function directly; instead, they use multigate designs like the ones shown in Figure 5-70.
XY (XOR) (X Y) (XNOR)
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Ta b l e 5 - 4 3 Behavioral VHDL program for a specialized 4-input, 3-bit multiplexer.
X Y
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
Ta b l e 5 - 4 4 Truth table for XOR and XNOR functions.
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(a) X
Figure 5-70 Multigate designs for the 2-input XOR function: (a) AND-OR; (b) three-level NAND.
74x86
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F =XY Y (b) X F =XY Y (a) (b)
Figure 5-71 Equivalent symbols for (a) XOR gates; (b) XNOR gates.
The logic symbols for XOR and XNOR functions are shown in Figure 5-71. There are four equivalent symbols for each function. All of these alternatives are a consequence of a simple rule: Any two signals (inputs or output) of an XOR or XNOR gate may be complemented without changing the resulting logic function.
In bubble-to-bubble logic design, we choose the symbol that is most expressive of the logic function being performed. Four XOR gates are provided in a single 14-pin SSI IC, the 74x86 shown in Figure 5-72. New SSI logic families do not offer XNOR gates, although they are readily available in FPGA and ASIC libraries and as primitives in HDLs.
1 2 3 9 8
Figure 5-72 Pinouts of the 74x86 quadruple 2-input Exclusive OR gate.
10
4 5
6
12 13
11
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(b)
5.8.2 Parity Circuits As shown in Figure 5-73(a), n XOR gates may be cascaded to form a circuit with n + 1 inputs and a single output. This is called an odd-parity circuit, because its output is 1 if an odd number of its inputs are 1. The circuit in (b) is also an oddparity circuit, but its faster because its gates are arranged in a tree-like structure. If the output of either circuit is inverted, we get an even-parity circuit, whose output is 1 if an even number of its inputs are 1. 5.8.3 The 74x280 9-Bit Parity Generator Rather than build a multibit parity circuit with discrete XOR gates, it is more economical to put all of the XORs in a single MSI package with just the primary inputs and outputs available at the external pins. The 74x280 9-bit parity generator, shown in Figure 5-74, is such a device. It has nine inputs and two outputs that indicate whether an even or odd number of inputs are 1. 5.8.4 Parity-Checking Applications In Section 2.15, we described error-detecting codes that use an extra bit, called a parity bit, to detect errors in the transmission and storage of data. In an evenparity code, the parity bit is chosen so that the total number of 1 bits in a code word is even. Parity circuits like the 74x280 are used both to generate the correct value of the parity bit when a code word is stored or transmitted, and to check the parity bit when a code word is retrieved or received.
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IN ODD I1 I2 I3 I4 ODD IM IN
Figure 5-73 Cascading XOR gates: (a) daisy-chain connection; (b) tree structure.
odd-parity circuit
even-parity circuit
74x280
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74x280
SPEEDING UP THE XOR TREE
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(b)
8 9 10 11 12 13 1 2 4
(a)
A B C
(8) (9)
A B C D E F G H I
EVEN ODD
5
6
(10)
D E F
(11) (12) (13)
(5)
EVEN
G H I
(1) (2) (4)
(6)
ODD
Figure 5-74 The 74x280 9-bit odd/even parity generator: (a) logic diagram, including pin numbers for a standard 16-pin dual in-line package; (b) traditional logic symbol.
Figure 5-75 shows how a parity circuit might be used to detect errors in the memory of a microprocessor system. The memory stores 8-bit bytes, plus a parity bit for each byte. The microprocessor uses a bidirectional bus D[0:7] to transfer data to and from the memory. Two control lines, RD and WR, are used to indicate whether a read or write operation is desired, and an ERROR signal is asserted to indicate parity errors during read operations. Complete details of the memory chips, such as addressing inputs, are not shown; memory chips are described in detail in \chapref{MEMORY}.
If each XOR gate in Figure 5-74 were built using discrete NAND gates as in Figure 5-70(b), the 74x280 would be pretty slow, having a propagation delay equivalent to 4 3 + 1, or 13, NAND gates. Instead, a typical implementation of the 74x280 uses a 4-wide AND-OR-INVERT gate to perform the function of each shaded pair of XOR gates in the figure with about the same delay as a single NAND gate. The AI inputs are buffered through two levels of inverters so that each input presents just one unit load to the circuit driving it. Thus, the total propagation delay through this implementation of the 74x280 is about the same as five inverting gates, not 13.
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D[0:7] RD WR
Figure 5-75 Parity generation and checking for an 8-bit-wide memory system.
To store a byte into the memory chips, we specify an address (not shown), place the byte on D [07], generate its parity bit on PIN, and assert WR. The AND gate on the I input of the 74x280 ensures that I is 0 except during read operations, so that during writes the 280s output depends only on the parity of the D-bus data. The 280s ODD output is connected to PIN , so that the total number of 1s stored is even. To retrieve a byte, we specify an address (not shown) and assert R D; the byte value appears on DOUT[07] and its parity appears on POUT. A 74x541 drives the byte onto the D bus, and the 280 checks its parity. If the parity of the 9-bit word DOUT[07],POUT is odd during a read, the ERROR signal is asserted. Parity circuits are also used with error-correcting codes such as the Hamming codes described in Section 2.15.3. We showed the parity-check matrix for a 7-bit Hamming code in Figure 2-13 on page 59. We can correct errors in this code as shown in Figure 5-76. A 7-bit word, possibly containing an error, is presented on D U[17]. Three 74x280s compute the parity of the three bit-groups defined by the parity-check matrix. The outputs of the 280s form the syndrome, which is the number of the erroneous input bit, if any. A 74x138 is used to decode the syndrome. If the syndrome is zero, the NOERROR_L signal is asserted (this signal also could be named ERROR). Otherwise, the erroneous
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4 5 6
ERROR
U1
74LS04 U3
1
2
RD_L
74x280
Memory Chips
74x541
D0 D1
8 9
1
D2 10 D3 11
D4 12 D5 13 D6 D7 1 2
74x08
1 2
3
RP 4
A B C D E F G H I
D0 D1 D2 D3 D4 D5 D6 D7
EVEN ODD
5
6
PI
U2
U1
READ WRITE DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 PIN
19
G1 G2
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 POUT
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
2
3 4
5 6 7 8 9
A1 A2 A3 A4 A5 A6 A7 A8
Y1 17 D1 Y2 16 D2 Y3
15 14 13 D3 D4 D5 D6 D7
18
D0
Y4 Y5 Y6 Y7 Y8
12 11
U4
PO
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DU7 DU5 8 9 DU3 10 DU1 11 12 13 1 2 4
A B C D E F G H I
EVEN ODD
5
NOERROR_L DC_L[1:7]
6
DU1
74x86
1
E1_L 2
3 DC1_L
U5
U1
74x280
DU2
74x86
4
DU7 DU6
A B DU3 10 C DU2 11 D
9 12 13
8
E2_L 5
6 DC2_L
+5V
U5
EVEN ODD
5
DU3 10
74x86
R
E3_L 9
8 DC3_L
E F 1 G 2 H 4 I
74x138
6
U5
6
4 5
U2
G1 G2A G2B
Y0 Y1 Y2 Y3
15 14 13 12 11 10 9 7
DU4 13
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E4_L 12
11 DC4_L
U5
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DU7
A DU6 9 B DU5 10 C DU4 11 D
12 13 1 2 4
8
SYN0 SYN1 SYN2
1
A B 3 C
2
Y4 Y5 Y6 Y7
DU5
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1
E5_L 2
3 DC5_L
U6
EVEN ODD
5
U4
DU6
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4
E F G H I
E6_L 5
6 DC6_L
6
U6
DU7 10
74x86
E7_L 9
8 DC7_L
U3
U6
Figure 5-76 Error-correcting circuit for a 7-bit Hamming code.
bit is corrected by complementing it. The corrected code word appears on the DC_L bus. Note that the active-low outputs of the 138 led us to use an active-low DC_L bus. If we required an active-high DC bus, we could have put a discrete inverter on each XOR input or output, or used a decoder with active-high outputs, or used XNOR gates.
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5.8.5 Exclusive OR Gates and Parity Circuits in ABEL and PLDs The Exclusive OR function is denoted in ABEL by the $ operator, and its complement, the Exclusive NOR function, is denoted by !$. In principle, these operators may be used freely in ABEL expressions. For example, you could specify a PLD output equivalent to the 74x280s EVEN output using the following ABEL equation:
EVEN = !(A $ B $ C $ D $ E $ F $ G $ H $ I);
However, most PLDs realize expressions using two-level AND-OR logic and have little if any capability of realizing XOR functions directly. Unfortunately, the Karnaugh map of an n-input XOR function is a checkerboard with 2n1 prime implicants. Thus, the sum-of-products realization of the simple equation above requires 256 product terms, well beyond the capability of any PLD. As well see in Section 10.5.2, some PLDs can realize a two-input XOR function directly in a three-level structure combining two independent sums of products. This structure turns out to be useful in the design of counters. To create larger XOR functions, however, a board-level designer must normally use a specialized parity generator/checker component like the 74x280, and an ASIC designer must combine individual XOR gates in a multilevel parity tree similar to Figure 5-73(b) on page 373.
5.8.6 Exclusive OR Gates and Parity Circuits in VHDL Like ABEL, VHDL provides primitive operators, xor and xnor, for specifying XOR and XNOR functions (xnor was introduced in VHDL-93). For example, Table 5-45 is a dataflow-style program for a 3-input XOR device that uses the xor primitive. Its also possible to specify XOR or parity functions behaviorally, as Table 5-46 does for a 9-input parity function similar to the 74x280.
T a b l e 5 - 4 5 Dataflow-style VHDL program for a 3-input XOR device.
library IEEE; use IEEE.std_logic_1164.all;
entity vxor3 is port ( A, B, C: in STD_LOGIC; Y: out STD_LOGIC ); end vxor3; architecture vxor3 of vxor3 is begin Y <= A xor B xor C; end vxor3;
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Ta b l e 5 - 4 6 Behavioral VHDL program for a 9-input parity checker.
library IEEE; use IEEE.std_logic_1164.all; entity parity9 is port ( I: in STD_LOGIC_VECTOR (1 to 9); EVEN, ODD: out STD_LOGIC ); end parity9; architecture parity9p of parity9 is begin process (I) variable p : STD_LOGIC; variable j : INTEGER; begin p := I(1); for j in 2 to 9 loop if I(j) = '1' then p := not p; end if; end loop; ODD <= p; EVEN <= not p; end process; end parity9p;
When a VHDL program containing large XOR functions is synthesized, the synthesis tool will do the best it can to realize the function in the targeted device technology. Theres no magicif we try to target the VHDL program in Table 5-46 to a 16V8 PLD, it still wont fit! Typical ASIC and FPGA libraries contain two- and three-input XOR and XNOR functions as primitives. In CMOS ASICs, these primitives are usually realized quite efficiently at the transistor level using transmission gates as shown in Exercises 5.73 and 5.75. Fast and compact XOR trees can be built using these primitives. However, typical VHDL synthesis tools are not be smart enough to create an efficient tree structure from a behavioral program like Table 5-46. Instead, we can use a structural program to get exactly what we want. For example, Table 5-47 is a structural VHDL program for a 9-input XOR function that is equivalent to the 74x280 of Figure 5-74(a) in structure as well as function. In this example, weve used the previously defined vxor3 component as the basic building block of the XOR tree. In an ASIC, we would replace the vxor3 w ith a 3-input XOR primitive from the ASIC library. Also, if a 3-input XNOR were available, we could eliminate the explicit inversion for Y3N and instead use the XNOR for U5, using the noninverted Y3 signal as its last input.
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Comparators
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library IEEE; use IEEE.std_logic_1164.all;
entity V74x280 is port ( I: in STD_LOGIC_VECTOR (1 to 9); EVEN, ODD: out STD_LOGIC ); end V74x280;
architecture V74x280s of V74x280 is component vxor3 port (A, B, C: in STD_LOGIC; Y: out STD_LOGIC); end component; signal Y1, Y2, Y3, Y3N: STD_LOGIC; begin U1: vxor3 port map (I(1), I(2), I(3), Y1); U2: vxor3 port map (I(4), I(5), I(6), Y2); U3: vxor3 port map (I(7), I(8), I(9), Y3); Y3N <= not Y3; U4: vxor3 port map (Y1, Y2, Y3, ODD); U5: vxor3 port map (Y1, Y2, Y3N, EVEN); end V74x280s;
Our final example is a VHDL version of the Hamming decoder circuit of Figure 5-76. A function syndrome(DU) is defined to return the 3-bit syndrome of a 7-bit uncorrected data input vector DU. In the main process, the corrected data output vector DC is initially set equal to DU. The CONV_INTEGER function, introduced in \secref{VHDLconv}, is used to convert the 3-bit syndrome to an integer. If the syndrome is nonzero, the corresponding bit of DC is complemented to correct the assumed 1-bit error. If the syndrome is zero, either no error or an undetectable error has occurred; the output NOERROR is set accordingly.
5.9 Comparators
Comparing two binary words for equality is a commonly used operation in computer systems and device interfaces. For example, in Figure 2-7(a) on page 52, we showed a system structure in which devices are enabled by comparing a device select word with a predetermined device ID. A circuit that compares two binary words and indicates whether they are equal is called a comparator. Some comparators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship (greater or less than) between the words. These devices are often called magnitude comparators.
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Ta b l e 5 - 4 7 Structural VHDL program for a 74x280-like parity checker. comparator Copying Prohibited
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity hamcorr is port ( DU: IN STD_LOGIC_VECTOR (1 to 7); DC: OUT STD_LOGIC_VECTOR (1 to 7); NOERROR: OUT STD_LOGIC ); end hamcorr; architecture hamcorr of hamcorr is function syndrome (D: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is variable SYN: STD_LOGIC_VECTOR (2 downto 0); begin SYN(0) := D(1) xor D(3) xor D(5) xor D(7); SYN(1) := D(2) xor D(3) xor D(6) xor D(7); SYN(2) := D(4) xor D(5) xor D(6) xor D(7); return(SYN); end syndrome; begin process (DU) variable SYN: STD_LOGIC_VECTOR (2 downto 0); variable i: INTEGER; begin DC <= DU; i := CONV_INTEGER(syndrome(DU)); if i = 0 then NOERROR <= '1'; else NOERROR <= '0'; DC(i) <= not DU(i); end if; end process; end hamcorr;
T a b l e 5 - 4 8 Behavioral VHDL program for Hamming error correction.
5.9.1 Comparator Structure EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit comparators. Figure 5-77(a) shows an interpretation of the 74x86 XOR gate as a 1-bit comparator. The active-high output, DIFF, is asserted if the inputs are different. The outputs of four XOR gates are ORed to create a 4-bit comparator in (b). The DIFF output is asserted if any of the input-bit pairs are different. Given enough XOR gates and wide enough OR gates, comparators with any number of input bits can be built.
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(a)
A0 B0
Figure 5-77 Comparators using the 74x86: (a) 1-bit comparator; (b) 4-bit comparator.
5.9.2 Iterative Circuits An iterative circuit is a special type of combinational circuit, with the structure shown in Figure 5-78. The circuit contains n identical modules, each of which has both primary inputs and outputs and cascading inputs and outputs. The leftmost cascading inputs are called boundary inputs and are connected to fixed logic values in most iterative circuits. The rightmost cascading outputs are called boundary outputs and usually provide important information. Iterative circuits are well suited to problems that can be solved by a simple iterative algorithm: 1. 2. 3. 4. Set C0 to its initial value and set i to 0. Use Ci and PIi to determine the values of POi and Ci+1. Increment i. If i < n, go to step 2.
In an iterative circuit, the loop of steps 24 is unwound by providing a separate combinational circuit that performs step 2 for each value of i.
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(b) A0 B0
1 2 3
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AN ITERATIVE COMPARATOR
The n-bit comparators in the preceding subsection might be called parallel comparators because they look at each pair of input bits simultaneously and deliver the 1-bit comparison results in parallel to an n-input OR or AND function. It is also possible to design an iterative comparator that looks at its bits one at a time using a small, fixed amount of logic per bit. Before looking at the iterative comparator design, you should understand the general class of iterative circuits described in the next subsection.
iterative circuit primary inputs and outputs
cascading inputs and outputs boundary outputs
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primary inputs
boundary inputs
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PI0 cascading input PI1 cascading output PIn1 C0 PI CI C1 PI module CO PO CI C2 Cn1 PI Cn module CO PO CI module CO PO PO0 PO1 POn1 primary outputs
boundary outputs
Figure 5-78 General structure of an iterative combinational circuit.
Examples of iterative circuits are the comparator circuit in the next subsection and the ripple adder in Section 5.10.2. The 74x85 4-bit comparator and the 74x283 4-bit adder are examples of MSI circuits that can be used as the individual modules in a larger iterative circuit. In \secref{itvsseq} well explore the relationship between iterative circuits and corresponding sequential circuits that execute the 4-step algorithm above in discrete time steps.
5.9.3 An Iterative Comparator Circuit Two n-bit values X and Y can be compared one bit at a time using a single bit EQi at each step to keep track of whether all of the bit-pairs have been equal so far: 1. 2. 3. 4. Set EQ0 to 1 and set i to 0. If EQi is 1 and Xi and Yi are equal, set EQi + 1 to 1. Else set EQi+1 to 0. Increment i. If i < n, go to step 2.
Figure 5-79 shows a corresponding iterative circuit. Note that this circuit has no primary outputs; the boundary output is all that interests us. Other iterative circuits, such as the ripple adder of Section 5.10.2, have primary outputs of interest. Given a choice between the iterative comparator circuit in this subsection and one of the parallel comparators shown previously, you would probably prefer the parallel comparator. The iterative comparator saves little if any cost, and its very slow because the cascading signals need time to ripple from the leftmost to the rightmost module. Iterative circuits that process more than one bit
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Comparators
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1
at a time, using modules like the 74x85 4-bit comparator and 74x283 4-bit adder, are much more likely to be used in practical designs.
5.9.4 Standard MSI Comparators Comparator applications are common enough that several MSI comparators have been developed commercially. The 74x85 is a 4-bit comparator with the logic symbol shown in Figure 5-80. It provides a greater-than output (AGTBOUT) and a less-than output (ALTBOUT) as well as an equal output (AEQBOUT). The 85 also has cascading inputs (AGTBIN, ALTBIN, AEQBIN) for combining multiple 85s to create comparators for more than four bits. Both the cascading inputs and the outputs are arranged in a 1-out-of-3 code, since in normal operation exactly one input and one output should be asserted. The cascading inputs are defined so the outputs of an 85 that compares less-significant bits are connected to the inputs of an 85 that compares more74x85
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Y CMP EQI EQO X EQ1 Y CMP EQI EQO X EQ2 Y CMP EQI EQO X EQ3 EQ(N1) Y CMP EQI EQO X EQN (a) X Y CMP EQO EQI
Figure 5-79 An iterative comparator circuit: (a) module for one bit; (b) complete circuit.
74x85
cascading inputs
ALTBIN ALTBOUT 3 6 AEQBIN AEQBOUT 5 4 AGTBIN AGTBOUT 10 A0
9
2
7
Figure 5-80 Traditional logic symbol for the 74x85 4-bit comparator.
12 11 13 14 15 1
B0 A1 B1 A2 B2 A3 B3
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2 3 4 5 6 7 8 9 11 12 13 14 15
Q5 P6 16 Q6
17
P7 18 Q7
Figure 5-82 Traditional logic symbol for the 74x682 8-bit comparator.
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R 74x85 74x85 74x85
XD0 YD0 XD1 YD1 XD2 YD2 XD3 YD3
ALTBIN ALTBOUT 6 AEQBIN AEQBOUT 5 4 AGTBIN AGTBOUT 10 A0
3 9 12 11 13 14 15 1
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XLTY4 XEQY4 XGTY4
XD4 YD4 XD5 YD5 XD6 YD6 XD7 YD7
ALTBIN ALTBOUT 6 AEQBIN AEQBOUT 5 4 AGTBIN AGTBOUT 10 A0
3 9 12 11 13 14 15 1
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XLTY8 XEQY8 XGTY8
XD8 YD8 XD9 YD9
7 XLTY ALTBIN ALTBOUT 6 XEQY AEQBIN AEQBOUT 5 XGTY 4 AGTBIN AGTBOUT 10 A0 2 3 9 12 11 13 14 15 1
B0 A1 B1 A2 B2 A3 B3
B0 A1 B1 A2 B2 A3 B3
B0 A1 B1 A2 B2 A3 B3
XD10 YD10 XD11 YD11
XD[011] YD[011]
Figure 5-81 A 12-bit comparator using 74x85s.
significant bits, as shown in Figure 5-81 for a 12-bit comparator. This is an iterative circuit according to the definition in Section 5.9.2. Each 85 develops its cascading outputs roughly according to the following pseudo-logic equations:
AGTBOUT = (A > B) + (A = B) AGTBIN ALTBOUT = (A < B) + (A = B) ALTBIN AEQBOUT = (A = B) AEQBIN
74x682
P0
Q0 P1 Q1 P2 Q2 P3 Q3 P4 Q4 P5
P EQ Q
19
P GT Q
1
The parenthesized subexpressions above are not normal logic expressions, but indicate an arithmetic comparison that occurs between the A3A0 and B3B0 inputs. In other words, AGTBOUT is asserted if A > B or if A = B and AGTBIN is asserted (if the higher-order bits are equal, we have to look at the lower-order bits for the answer). Well see this kind of expression again when we look at ABEL comparator design in Section 5.9.5. The arithmetic comparisons can be expressed using normal logic expressions, for example, (A > B) = A3 B3+ (A3 B3) A2 B2 +
(A3 B3) (A2 B2) A1 B1 +
(A3 B3) (A2 B2) (A1 B1) A0 B0
Such expressions must be substituted into the pseudo-logic equations above to obtain genuine logic equations for the comparator outputs. Several 8-bit MSI comparators are also available. The simplest of these is the 74x682, whose logic symbol is shown in Figure 5-82 and whose internal
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Q0 P0
Q1 P1
Q2 P2
Q3 P3
Q4 P4
Q5 P5
Q6 P6
Q7 P7
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(19) (3) (2) (5) (4) (7) (6) (9) (8) (1) (12) (11) (14) (13) (16) (15) (18) (17)
Figure 5-83 Logic diagram for the 74x682 8-bit comparator, including pin numbers for a standard 20-pin dual in-line package.
PEQQ_L
PGTQ_L
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Figure 5-84 Arithmetic conditions derived from 74x682 outputs.
PNEQ 74x04
1 2
logic diagram is shown in Figure 5-83. The top half of the circuit checks the two 8-bit input words for equality. Each XNOR-gate output is asserted if its inputs are equal, and the PEQQ_L output is asserted if all eight input-bit pairs are equal. The bottom half of the circuit compares the input words arithmetically, and asserts /PGTQ if P[70] > Q[70]. Unlike the 74x85, the 74x682 does not have cascading inputs. Also unlike the 85, the 682 does not provide a less than output. However, any desired condition, including and , can be formulated as a function of the PEQQ_L and PGTQ_L outputs, as shown in Figure 5-84.
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COMPARING COMPARATORS
The individual 1-bit comparators (XNOR gates) in the 682 are drawn in the opposite sense as the examples of the preceding subsectionoutputs are asserted for equal inputs and then ANDed, rather than asserted for different inputs and then ORed. We can look at a comparators function either way, as long as were consistent.
5.9.5 Comparators in ABEL and PLDs Comparing two sets for equality or inequality is very easy to do in ABEL using the == or != operator in a relational expression. The only restriction is that the two sets must have an equal number of elements. Thus, given the relational expression A!=B where A and B are sets each with n elements, the compiler generates the logic expression
(A1 $ B1) # (A2 $ B2) # ... # (An $ Bn)
The logic expression for A==Bis just the complement of the one above.
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In the preceding logic expression, it takes one 2-input XOR function to compare each bit. Since a 2-input XOR function can be realized as a sum of two product terms, the complete expression can be realized in a PLD as a relatively modest sum of 2n product terms:
(A1&!B1 # !A1 &B1) # (A2 &!B2 # !A2&&B2) # ... # (An&!Bn # !An&&Bn)
Although ABEL has relational operators for less-than and greater-than comparisons, the resulting logic expressions are not so small or easy to derive. For example, consider the relational expression A<B, where [An..A1] and [Bn..B1] are sets with n elements. To construct the corresponding logic expression, ABEL first constructs n equations of the form
Li = (!Ai & (Bi # Li-1) # (Ai & Bi & Li-1)
for i = 1 to n and L0 = 0 by definition. This is, in effect, an iterative definition of the less-than function, starting with the least-significant bit. Each Li equation says that, as of bit i, A is less than B if Ai is 0 and Bi is 1 or A was less than B as of the previous bit, or if Ai and Bi are both 1 and A was less than B as of the previous bit. The logic expression for A<B is simply the equation for Ln. So, after creating the n equations above, ABEL collapses them into a single equation for Ln involving only elements of A and B. It does this by substituting the Ln-1 equation into the right-hand side of the Ln equation, then substituting the Ln-2 equation into this result, and so on, until substituting 0 for L0. Finally, it derives a minimal sum-of-products expression from the result. Collapsing an iterative circuit into a two-level sum-of-products realization usually creates an exponential expansion of product terms. The < comparison function follows this pattern, requiring 2 n1 product terms for an n-bit comparator. Thus, comparators larger than a few bits cannot be realized practically in one pass through a PLD. The results for > comparators are identical, of course, and logic expressions for >=and <= are at least as bad, being the complements of the expressions for < and >. If we use a PLD with output polarity control, the inversion is free and the number of product terms is the same; otherwise, the minimal number of product terms after inverting is 2n+2n11. 5.9.6 Comparators in VHDL VHDL has comparison operators for all of its built-in types. Equality (=) and inequality (/=) operators apply to all types; for array and record types, the operands must have equal size and structure, and the operands are compared component by component. We have used the equality operator to compare a signal or signal vector with a constant value in many examples in this chapter. If we compare two signals or variables, the synthesis engine generates equations similar to ABELs in the preceding subsection.
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Ta b l e 5 - 4 9 Behavioral VHDL program for comparing 8-bit unsigned integers.
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library IEEE; use IEEE.std_logic_1164.all; entity vcompare is port ( A, B: in STD_LOGIC_VECTOR (7 downto 0); EQ, NE, GT, GE, LT, LE: out STD_LOGIC ); end vcompare;
VHDLs other comparison operators, >, <, >=, and <=, apply only to integer types, enumerated types (such as STD_LOGIC), and one-dimensional arrays of enumeration or integer types. Integer order from smallest to largest is the natural ordering, from minus infinity to plus infinity, and enumerated types use the ordering in which the elements of the type were defined, from first to last (unless you explicitly change the enumeration encoding using a command specific to the synthesis engine, in which case the ordering is that of your encoding). The ordering for array types is defined iteratively, starting with the leftmost element in each array. Arrays are always compared from left to right, regardless of the order of their index range (to or downto). The order of the leftmost pair of unequal elements is the order of the array. If the arrays have unequal lengths and all the elements of the shorter array match the corresponding elements of the longer one, then the shorter array is considered to be the smaller. The result of all this is that the built-in comparison operators compare equal-length arrays of type BIT_VECTOR or STD_LOGIC_VECTOR as if they represented unsigned integers. If the arrays have different lengths, then the operators do not yield a valid arithmetic comparison, what youd get by extending the shorter array with zeroes on the left; more on this in a moment. Table 5-49 is a VHDL program that produces all of the comparison outputs for comparing two 8-bit unsigned integers. Since the two input vectors A and B have equal lengths, the program produces the desired results.
architecture vcompare_arch of vcompare is begin process (A, B) begin EQ <= '0'; NE <= '0'; GT <= '0'; GE <= '0'; LT <= '0'; LE <= '0'; if A = B then EQ <= '1'; end if; if A /= B then NE <= '1'; end if; if A > B then GT <= '1'; end if; if A >= B then GE <= '1'; end if; if A < B then LT <= '1'; end if; if A <= B then LE <= '1'; end if; end process; end vcompare_arch
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To allow more flexible comparisons and arithmetic operations, the IEEE has created a standard package, IEEE_std_logic_arith, which defines two important new types and a host of comparison and arithmetic functions that operate on them. The two new types are SIGNED and UNSIGNED:
type SIGNED is array (NATURAL range <> of STD_LOGIC; type UNSIGNED is array (NATURAL range <> of STD_LOGIC;
As you can see, both types are defined just indeterminate-length arrays of STD_LOGIC, no different from STD_LOGIC_VECTOR. The important thing is that the package also defines new comparison functions that are invoked when either or both comparison operands have one of the new types. For example, it defines eight new less-than functions with the following combinations of parameters:
function function function function function function function function "<" "<" "<" "<" "<" "<" "<" "<" (L: (L: (L: (L: (L: (L: (L: (L: UNSIGNED; R: UNSIGNED) return BOOLEAN; SIGNED; R: SIGNED) return BOOLEAN; UNSIGNED; R: SIGNED) return BOOLEAN; SIGNED; R: UNSIGNED) return BOOLEAN; UNSIGNED; R: INTEGER) return BOOLEAN; INTEGER; R: UNSIGNED) return BOOLEAN; SIGNED; R: INTEGER) return BOOLEAN; INTEGER; R: SIGNED) return BOOLEAN;
Thus, the < operator can be used with any combination of SIGNED, UNSIGNED, and INTEGER operands; the compiler selects the function whose parameter types match the actual operands. Each of the functions is defined in the package to do the right thing, including making the appropriate extensions and conversions when operands of different sizes or types are used. Similar functions are provided for the other five relational operators, =, /=, <=, >, and >=. Using the IEEE_std_logic_arith package, you can write programs like the one in Table 5-50. Its 8-bit input vectors, A, B, C, and D, have three different types. In the comparisons involving A, B, and C, the compiler automatically selects the correct version of the comparison function; for example, for A<B it selects the first < function above, because both operands have type UNSIGNED. In the comparisons involving D, explicit type conversions are used. The assumption is that the designer wants this particular STD_LOGIC_VECTOR to be interpreted as UNSIGNED in one case and SIGNED in another. The important thing to understand here is that the IEEE_std_logic_arith package does not make any assumptions about how STD_LOGIC_VECTORs are to be interpreted; the user must specify the conversion. Two other packages, STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED, do make assumptions and are useful if all STD_LOGIC_VECTORs are to be interpreted the same way. Each package contains three versions of each comparison function so that STD_LOGIC_VECTORs are interpreted as SIGNED or UNSIGNED, respectively, when compared with each other or with integers.
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity vcompa is port ( A, B: in UNSIGNED (7 downto 0); C: in SIGNED (7 downto 0); D: in STD_LOGIC_VECTOR (7 downto 0); A_LT_B, B_GE_C, A_EQ_C, C_NEG, D_BIG, D_NEG: out STD_LOGIC ); end vcompa;
architecture vcompa_arch of vcompa is begin process (A, B, C, D) begin A_LT_B <= '0'; B_GE_C <= '0'; A_EQ_C <= '0'; C_NEG <= '0'; D_BIG <= '0'; D_NEG <= '0'; if A < B then A_LT_B <= '1'; end if; if B >= C then B_GE_C <= '1'; end if; if A = C then A_EQ_C <= '1'; end if; if C < 0 then C_NEG <= '1'; end if; if UNSIGNED(D) > 200 then D_BIG <= '1'; end if; if SIGNED(D) < 0 then D_NEG <= '1'; end if; end process; end vcompa_arch;
adder
subtractor
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Ta b l e 5 - 5 0 Behavioral VHDL program for comparing 8-bit integers of various types.
When a comparison function is specified in VHDL, it takes just as many product terms as in ABEL to realize the function as a two-level sum of products. However, most VHDL synthesis engines will realize the comparator as an iterative circuit with far fewer gates, albeit more levels of logic. Also, better synthesis engines can detect opportunities to eliminate entire comparator circuits. For example, in the program of Table 5-49 on page 388, the NE, GE, and LE outputs could be realized with one inverter each, as the complements of the EQ, LT, and GT outputs, respectively.
*5.10 Adders, Subtractors, and ALUs
Addition is the most commonly performed arithmetic operation in digital systems. An adder combines two arithmetic operands using the addition rules described in Chapter 2. As we showed in Section 2.6, the same addition rules and therefore the same adders are used for both unsigned and twos-complement numbers. An adder can perform subtraction as the addition of the minuend and the complemented (negated) subtrahend, but you can also build subtractor
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circuits that perform subtraction directly. MSI devices called ALUs, described in Section 5.10.6, perform addition, subtraction, or any of several other operations according to an operation code supplied to the device.
*5.10.1 Half Adders and Full Adders The simplest adder, called a half adder, adds two 1-bit operands X and Y, producing a 2-bit sum. The sum can range from 0 to 2, which requires two bits to express. The low-order bit of the sum may be named HS (half sum), and the high-order bit may be named CO (carry out). We can write the following equations for HS and CO: HS = X Y = X Y + X Y CO = X Y
To add operands with more than one bit, we must provide for carries between bit positions. The building block for this operation is called a full adder. Besides the addend-bit inputs X and Y, a full adder has a carry-bit input, CIN. The sum of the three inputs can range from 0 to 3, which can still be expressed with just two output bits, S and COUT, having the following equations:
S = X Y CIN
Here, S is 1 if an odd number of the inputs are 1, and COUT is 1 if two or more of the inputs are 1. These equations represent the same operation that was specified by the binary addition table in Table 2-3 on page 28. One possible circuit that performs the full-adder equations is shown in Figure 5-85(a). The corresponding logic symbol is shown in (b). Sometimes the symbol is drawn as shown in (c), so that cascaded full adders can be drawn more neatly, as in the next subsection.
full adder X Y CIN
(a)
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half adder full adder
= X Y CIN + X Y CIN + X Y CIN + X Y CIN
COUT = X Y + X CIN + Y CIN
S
X Y CIN
S
COUT
(b)
Figure 5-85 Full adder: (a) gatelevel circuit diagram; (b) logic symbol; (c) alternate logic symbol suitable for cascading.
COUT
X
Y
COUT
CIN
(c)
S
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ripple adder
full subtractor
Figure 5-86 A 4-bit ripple adder.
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tADD = tXYCout + (n 2) tCinCout + tCinS
x3 X y3 Y x2 X y2 Y x1 X y1 Y x0 X y0 Y c4 COUT CIN c3 COUT CIN c2 COUT CIN c1 COUT CIN S S S S s3 s2 s1 s0
*5.10.2 Ripple Adders Two binary words, each with n bits, can be added using a ripple addera cascade of n full-adder stages, each of which handles one bit. Figure 5-86 shows the circuit for a 4-bit ripple adder. The carry input to the least significant bit (c0) is normally set to 0, and the carry output of each full adder is connected to the carry input of the next most significant full adder. The ripple adder is a classic example of an iterative circuit as defined in Section 5.9.2. A ripple adder is slow, since in the worst case a carry must propagate from the least significant full adder to the most significant one. This occurs if, for example, one addend is 11 11 and the other is 00 01. Assuming that all of the addend bits are presented simultaneously, the total worst-case delay is
where tXYCout is the delay from X or Y to COUT in the least significant stage, tCinCout is the delay from CIN to COUT in the middle stages, and tCinS is the delay from CIN to S in the most significant stage. A faster adder can be built by obtaining each sum output si with just two levels of logic. This can be accomplished by writing an equation for si in terms of x0xi, y0yi, and c0, multiplying out or adding out to obtain a sum-ofproducts or product-of-sums expression, and building the corresponding ANDOR or OR-AND circuit. Unfortunately, beyond s2, the resulting expressions have too many terms, requiring too many first-level gates and more inputs than typically possible on the second-level gate. For example, even assuming that c0 = 0, a two-level AND-OR circuit for s2 requires fourteen 4-input ANDs, four 5-input ANDs, and an 18-input OR gate; higher-order sum bits are even worse. Nevertheless, it is possible to build adders with just a few levels of delay using a more reasonable number of gates, as well see in Section 5.10.4. *5.10.3 Subtractors A binary subtraction operation analogous to binary addition was also specified in Table 2-3 on page 28. A full subtractor handles one bit of the binary subtraction algorithm, having input bits X (minuend), Y (subtrahend), and BIN (borrow
c0
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Section *5.10
Adders, Subtractors, and ALUs
393
in), and output bits D (difference) and BOUT (borrow out). We can write logic equations corresponding to the binary subtraction table as follows:
D = X Y BIN BOUT = X Y + X BIN + Y BIN
These equations are very similar to equations for a full adder, which should not be surprising. We showed in Section 2.6 that a twos-complement subtraction operation, X Y, can be performed by an addition operation, namely, by adding the twos complement of Y to X. The twos complement of Y is Y + 1, where Y is the bit-by-bit complement of Y. We also showed in Exercise 2.26 that a binary adder can be used to perform an unsigned subtraction operation X Y, by performing the operation X + Y + 1. We can now confirm that these statements are true by manipulating the logic equations above:
BOUT = X Y + X BIN + Y BIN
BOUT = (X + Y) (X + BIN) (Y + BIN)(generalized DeMorgans theorem)
For the last manipulation, recall that we can complement the two inputs of an
XOR gate without changing the function performed.
Comparing with the equations for a full adder, the above equations tell us that we can build a full subtractor from a full adder as shown in Figure 5-87. Just to keep things straight, weve given the full adder circuit in (a) a fictitious name, the 74x999. As shown in (c), we can interpret the function of this same physical circuit to be a full subtractor by giving it a new symbol with active-low borrow in, borrow out, and subtrahend signals. Thus, to build a ripple subtractor for two n-bit active-high operands, we can use n 74x999s and inverters, as shown in (d). Note that for the subtraction operation, the borrow input of the least significant bit should be negated (no borrow), which for an active-low input means that the physical pin must be 1 or HIGH . This is just the opposite as in addition, where the same input pin is an active-high carry-in that is 0 or LOW. By going back to the math in Chapter 2, we can show that this sort of manipulation works for all adder and subtractor circuits, not just ripple adders and subtractors. That is, any n-bit adder circuit can be made to function as a subtractor by complementing the subtrahend and treating the carry-in and carryout signals as borrows with the opposite active level. The rest of this section discusses addition circuits only, with the understanding that they can easily be made to perform subtraction.
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= X Y + X BIN + Y BIN (multiply out)
D = X Y BIN
= X Y BIN
(complementing XOR inputs)
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(a)
Chapter 5
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(b) (c)
(d)
b_Ln
carry lookahead
carry generate
carry propagate
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1 2 1 2 5
X Y 74x999
X
Y
COUT CIN S
4
3
BOUT BIN D
5
X Y 74x999
BOUT BIN D
4
3
xn1
yn1
xn2
yn2
x0
y0
1
3
13
74x04
74x04
74x04
2
4
12
1
2
1
2
1
2
5
X Y 74x999
BOUT BIN D
4
3
b_Ln1 5
X Y 74x999
BOUT BIN D
4
3
b_Ln2
b_L1 5
X Y 74x999
BOUT BIN D
4
3
b_L0 1
dn1
dn2
d0
Figure 5-87 Designing subtractors using adders: (a) full adder; (b) full subtractor; (c) interpreting the device in (a) as a full subtractor; (d) ripple subtractor.
*5.10.4 Carry Lookahead Adders The logic equation for sum bit i of a binary adder can actually be written quite simply: si = xi yi ci
More complexity is introduced when we expand ci above in terms of x0 xi1, y0 yi1, and c0, and we get a real mess expanding the XORs. However, if were willing to forego the XOR expansion, we can at least streamline the design of ci logic using ideas of carry lookahead discussed in this subsection. Figure 5-88 shows the basic idea. The block labeled Carry Lookahead Logic calculates ci in a fixed, small number of logic levels for any reasonable value of i. Two definitions are the key to carry lookahead logic: For a particular combination of inputs xi and yi, adder stage i is said to generate a carry if it produces a carry-out of 1 (ci+1 = 1) independent of the inputs on x0 xi1, y0 yi1, and c0. For a particular combination of inputs xi and yi, adder stage i is said to propagate carries if it produces a carry-out of 1 (ci+1 = 1) in the presence of an input combination of x0 xi1, y0 yi1, and c0 that causes a carry-in of 1 (ci = 1).
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Section *5.10
xi yi hsi ci
Adders, Subtractors, and ALUs
395
x i1 x0
yi1 y0 c0
Corresponding to these definitions, we can write logic equations for a carrygenerate signal, gi, and a carry-propagate signal, pi, for each stage of a carry lookahead adder:
g i = xi yi p i = xi + yi
That is, a stage unconditionally generates a carry if both of its addend bits are 1, and it propagates carries if at least one of its addend bits is 1. The carry output of a stage can now be written in terms of the generate and propagate signals:
ci+1
To eliminate carry ripple, we recursively expand the ci term for each stage, and multiply out to obtain a 2-level AND -OR expression. Using this technique, we can obtain the following carry equations for the first four adder stages:
c 1 = g0 + p0 c 0 c 2 = g1 + p1 c 1
Each equation corresponds to a circuit with just three levels of delayone for the generate and propagate signals, and two for the sum-of-products shown. A carry lookahead adder uses three-level equations such as these in each adder stage for the block labeled carry lookahead in Figure 5-88. The sum output for
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si Carry Lookahead Logic
Figure 5-88 Structure of one stage of a carry lookahead adder.
= gi + p i c i
= g1 + p1 (g0 + p0 c0)
= g1 + p1 g0 + p1 p0 c 0
c 3 = g2 + p2 c 2
= g2 + p2 (g1 + p1 g0 + p1 p0 c0)
= g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 c 0
c 4 = g3 + p3 c 3 = g 3 + p 3 ( g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0)
= g3 + p3 g 2 + p3 p 2 g1 + p3 p2 p1 g0 + p3 p 2 p1 p0 c 0
carry lookahead adder
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74x283 74x83
14 15 12 11
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74x283 C0 A0 6 B0
5 3 2 7
a stage is produced by combining the carry bit with the two addend bits for the stage as we showed in the figure. In the next subsection, well study some commercial MSI adders and ALUs that use carry lookahead.
S0 S1
4
A1 B1 A2 B2 A3 B3
1
*5.10.5 MSI Adders The 74x283 is a 4-bit binary adder that forms its sum and carry outputs with just a few levels of logic, using the carry lookahead technique. Figure 5-89 is a logic symbol for the 74x283. The older 74x83 is identical except for its pinout, which has nonstandard locations for power and ground. The logic diagram for the 283, shown in Figure 5-90, has just a few differences from the general carry-lookahead design that we described in the preceding subsection. First of all, its addends are named A and B instead of X and Y; no big deal. Second, it produces active-low versions of the carry-generate (gi ) and carry-propagate (pi ) signals, since inverting gates are generally faster than noninverting ones. Third, it takes advantage of the fact that we can algebraically manipulate the half-sum equation as follows:
hs i = x i y i = xi yi + xi yi
S2 S3
13
10
C4
9
= xi yi + xi xi + xi yi + yi yi = (xi + yi) (xi + yi) = pi gi
Figure 5-89 Traditional logic symbol for the 74x283 4-bit binary adder.
= (xi + yi) (xi yi)
Thus, an AND gate with an inverted input can be used instead of an XOR gate to create each half-sum bit. Finally, the 283 creates the carry signals using an INVERT-OR-AND structure (the DeMorgan equivalent of an AND-OR-INVERT), which has about the same delay as a single CMOS or TTL inverting gate. This requires some explaining, since the carry equations that we derived in the preceding subsection are used in a slightly modified form. In particular, the ci+1 equation uses the term pi gi instead of gi. This has no effect on the output, since pi is always 1 when gi is 1. However, it allows the equation to be factored as follows:
ci+1 = pi gi + pi ci = pi (gi + ci)
This leads to the following carry equations, which are used by the circuit :
c1 = p0 (g0 + c0) c2 = p1 (g1 + c1)
= p1 (g1 + p0 (g0 + c0))
= p1 (g1 + p0) (g1 + g0 + c0)
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Adders, Subtractors, and ALUs
397
B3 A3
B2 A2
B1 A1
B0 A0
C0
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(9)
C4
(11) (12)
g3
hs3
(10)
p3
S3
c3
(15) (14)
g2 p2
hs2
(13)
S2
c2
(2)
g1 p1
(3)
hs1
(1)
S1
c1
(6)
g0 p0 c 0
(5)
hs0 c0
(4)
S0
(7)
Figure 5-90 Logic diagram for the 74x283 4-bit binary adder.
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Combinational Logic Design Practices
group-ripple adder
Figure 5-91 A 16-bit group-ripple adder.
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c4 = p3 (g3 + c3) = p3 (g3 + p2 (g2 + p1) (g2 + g1 + p0) (g2 + g1 + g0 + c0))
X[15:0] Y[15:0] 74x283 74x283 C0
7 X0 Y0 X1
c3 = p2 (g2 + c2) = p2 (g2 + p1 (g1 + p0) (g1 + g0 + c0)) = p2 (g2 + p1) (g2 + g1 + p0) (g2 + g1 + g0 + c0)
= p3 (g3 + p2) (g3 + g2 + p1) (g3 + g2 + g1 + p0) (g3 + g2 + g1 + g0 + c0)
If youve followed the derivation of these equations and can obtain the same ones by reading the 283 logic diagram, then congratulations, youre up to speed on switching algebra! If not, you may want to review Sections 4.1 and 4.2. The propagation delay from the C0 input to the C4 output of the 283 is very short, about the same as two inverting gates. As a result, fairly fast groupripple adders with more than four bits can be made simply by cascading the carry outputs and inputs of 283s, as shown in Figure 5-91 for a 16-bit adder. The total propagation delay from C0 to C16 in this circuit is about the same as that of eight inverting gates.
C0 A0 6 B0
5
7
S0 S1
4
S0
X8
Y8
3 2
Y1
X2
A1 B1 A2 B2 A3 B3
1
S1
X9
C0 A0 6 B0
5
S0 S1
4
S8
3 2
Y9
14 15 12 11
Y2
S2 S3
13
S2
X10
A1 B1 A2 B2 A3 B3
1
S9
14 15 12 11
Y10
S2 S3
13
S10
X3
10
S3
X11
10
S11
Y3
Y11
C4
9
C4
9
U1
U3
C4
C12
74x283
74x283
7
X4 Y4 X5 Y5 X6 Y6 X7 Y7
C0 A0 6 B0
5 3 2
7
S0 S1
4
S4
X12 Y12 X13 Y13 X14 Y14 X15 Y15
14 15 12 11
A1 B1 A2 B2 A3 B3
1
S5
C0 A0 6 B0
5 3 2
S0 S1
4
S12
S2 S3
13
S6
14 15 12 11
10
S7
C4
9
C8
A1 B1 A2 B2 A3 B3
1
S13
S2 S3
13
S14
10
S15
C4
9
C16
U2
U4
S[15:0]
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Adders, Subtractors, and ALUs
399
*5.10.6 MSI Arithmetic and Logic Units An arithmetic and logic unit (ALU) is a combinational circuit that can perform any of a number of different arithmetic and logical operations on a pair of b-bit operands. The operation to be performed is specified by a set of function-select inputs. Typical MSI ALUs have 4-bit operands and three to five function select inputs, allowing up to 32 different functions to be performed. Figure 5-92 is a logic symbol for the 74x181 4-bit ALU. The operation performed by the 181 is selected by the M and S3S0 inputs, as detailed in Table 5-51. Note that the identifiers A, B, and F in the table refer to the 4-bit words A3A0, B3B0, and F3F0; and the symbols and + refer to logical AND and OR operations. The 181s M input selects between arithmetic and logical operations. When M = 1, logical operations are selected, and each output Fi is a function only of the corresponding data inputs, Ai and Bi. No carries propagate between stages, and the CIN input is ignored. The S3S0 inputs select a particular logical operation; any of the 16 different combinational logic functions on two variables may be selected.
T a b l e 5 - 5 1 Functions performed by the 74x181 4-bit ALU.
Inputs Function
S3
0 0 0
0
0 0 0 1
0
1 1 1
1 1 1 1
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arithmetic and logic unit (ALU) 74x181
S2 S1 S0
Figure 5-92 Logic symbol for the 74x181 4-bit ALU.
74x181
M = 0 (arithmetic)
M = 1 (logic)
0
0
0
F = A minus 1 plus CIN
F = A
6 5
0
0
1
F = A B minus 1 plus CIN F = 1111 plus CIN
F = A + B F = A + B F = 1111
0 0
1 1
0 1
F = A B minus 1 plus CIN
S0 S1 4 S2 3 S3
8 7
G P
17 15
1
0
0
F = A plus (A + B) plus CIN
F = A B F = B
M CIN A0 B0 A1 B1 A2 B2 A3 B3
A=B F0 F1 F2 F3
14
2
9
1
0
1
F = A B plus ( A + B) plus CIN F = A + B plus CIN
1
1
1
0
F = A minus B minus 1 plus CIN F = A plus (A + B) plus CIN F = A plus B plus CIN F = A + B plus CIN
F = A B F = A B
23 22
10
1
1
1
F = A + B F=AB F=B
21 20 19 18
11
0
0
0
0
0
1
13
0
1
0
F = A B plus (A + B) plus CIN F = A plus A plus CIN
COUT
16
0
1
1
F=A+B F = 0000 F = A B
1
0
0
1
0
1
F = A B plus A plus CIN F = A plus CIN
1
1
0
F = A B plus A plus CIN
F=AB F=A
1
1
1
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Chapter 5
Combinational Logic Design Practices
74x381 74x382
Figure 5-93 Logic symbols for 4-bit ALUs: (a) 74x381; (b) 74x382.
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(a) 74x381 (b) 74x382 S0 S1 7 S2 15 CIN
6 3 4 5
When M = 0, arithmetic operations are selected, carries propagate between the stages, and CIN is used as a carry input to the least significant stage. For operations larger than four bits, multiple 181 ALUs may be cascaded like the group-ripple adder in the Figure 5-91, with the carry-out (COUT) of each ALU connected to the carry-in (CIN ) of the next most significant stage. The same function-select signals (M, S3S0) are applied to all the 181s in the cascade. To perform twos-complement addition, we use S3S0 to select the operation A plus B plus CIN . The CIN input of the least-significant ALU is normally set to 0 during addition operations. To perform twos-complement subtraction, we use S3S0 to select the operation A minus B minus plus CIN. In this case, the CIN input of the least significant ALU is normally set to 1, since CIN acts as the complement of the borrow during subtraction. The 181 provides other arithmetic operations, such as A minus 1 plus CIN, that are useful in some applications (e.g., decrement by 1). It also provides a bunch of weird arithmetic operations, such as A B plus (A + B) plus CIN , that are almost never used in practice, but that fall out of the circuit for free. Notice that the operand inputs A3_LA0_L and B3_LB0_L and the function outputs F3_LF0_L of the 181 are active low. The 181 can also be used with active-high operand inputs and function outputs. In this case, a different version of the function table must be constructed. When M = 1, logical operations are still performed, but for a given input combination on S3S0, the function obtained is precisely the dual of the one listed in Table 5-51. When M = 0, arithmetic operations are performed, but the function table is once again different. Refer to a 181 data sheet for more details. Two other MSI ALUs, the 74x381 and 74x382 shown in Figure 5-93, encode their select inputs more compactly, and provide only eight different but useful functions, as detailed in Table 5-52. The only difference between the 381 and 382 is that one provides group-carry lookahead outputs (which we explain next), while the other provides ripple carry and overflow outputs.
G P
13 14
A0 B0 1 A1 2 B1
F0 F1 F2 F3
8
9
S0 S1 7 S2 OVR 15 CIN COUT 3 A0 F0 4 B0 1 A1 F1 2 B1
6
5
13 14
8
9
19 18
A2 B2 17 A3 16 B3
11
19 18
12
A2 B2 17 A3 16 B3
F2 F3
11
12
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Section *5.10
Inputs
S1
Adders, Subtractors, and ALUs
401
S2
0 0 0 0 1 1 1 1
*5.10.7 Group-Carry Lookahead The 181 and 381 provide group-carry lookahead outputs that allow multiple ALUs to be cascaded without rippling carries between 4-bit groups. Like the 74x283, the ALUs use carry lookahead to produce carries internally. However, they also provide G_L and P_L outputs that are carry lookahead signals for the entire 4-bit group. The G_L output is asserted if the ALU generates a carry, that is, if it will produce a carry-out (COUT = 1) whether or not there is a carry-in (CIN = 1): G_L = (g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0)
The P_L output is asserted if the ALU propagates a carry, that is, if it will produce a carry-out if there is a carry-in:
P_L = (p3 p2 p1 p0)
When ALUs are cascaded, the group-carry lookahead outputs may be combined in just two levels of logic to produce the carry input to each ALU. A lookahead carry circuit, the 74x182 shown in Figure 5-94, performs this operation. The 182 inputs are C0, the carry input to the least significant ALU (ALU 0), and G0G3 and P0P3, the generate and propagate outputs of ALUs 03. Using these inputs, the 182 produces carry inputs C1C3 for ALUs 13. Figure 5-95 shows the connections for a 16-bit ALU using four 381s and a 182. The 182s carry equations are obtained by adding out the basic carry lookahead equation of Section 5.10.4: ci+1 = gi + pi ci = (gi + pi) (gi + ci)
Expanding for the first three values of i, we obtain the following equations:
C1 = (G0 + P0) (G0 +C0) C2 = (G1 +P1) (G1 + G0 +P0) (G1 +G0 +C0) C3 = (G2 +P2) (G2 + G1 +P1) (G2 +G1 +G0 +P0) (G2 +G1 +G0 +C0) Copyright 1999 by John F. Wakerly
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S0
Function
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
F = 0000 F = B minus A minus 1 plus C IN F = A minus B minus 1 plus C IN F = A plus B plus CIN F=AB F=A+B F=AB F = 1111
Ta b l e 5 - 5 2 Functions performed by the 74x381 and 74x382 4-bit ALUs.
group-carry lookahead
lookahead carry circuit 74x182
74x182
13
3 4 1 2
14 15 5 6
C0 G0 P0 G1 P1 G2 P2 G3 P3
C1 C2 C3 G P
12
11
9
10 7
Figure 5-94 Logic symbol for the 74x182 lookahead carry circuit.
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Combinational Logic Design Practices
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74x182
Figure 5-95 A 16-bit ALU using group-carry lookahead.
13
3 4 1 2
C0 G0 P0 G1 P1 G2 P2 G3 P3
C1 C2 C3 G P
12
C4
11
C8
14 15 5 6
9
C12
10 7
GALL_L PALL_L
U5
C0 S[2:0] A[15:0] B[15:0]
74x381
74x381
S0 S1 S2
S0 S1 7 S2 15 CIN
6 3
5
S0 S1 S2
G P
13 14
G0_L P0_L
F0
S0 S1 7 S2 15 CIN
6 3
5
G P
13 14
G2_L P2_L
F8
A0 B0 A1 B1 A2 B2 A3 B3
A0 4 B0 1 A1 2 B1
F0 F1 F2 F3
8
A8 B8 A9 B9
9
F1
A0 4 B0 1 A1 2 B1
F0 F1 F2 F3
8
9
F9
19 18
A2 B2 17 A3 16 B3
11
F2
A10 B10 A11 B11
19 18
12
F3
A2 B2 17 A3 16 B3
11
F10
12
F11
U1
U3
ALU0
ALU2
74x381
74x381
S0 S1 S2
5 6 7
S0 S1
S0 S1 S2
5 6 7
15 3 4
S2 CIN
G P
13
G1_L P1_L
S0 S1
14
15 3 4
S2 CIN
G P
13 14
G3_L P3_L
A4 B4 A5 B5 A6 B6 A7 B7
A0 B0 1 A1
2
F0 F1 F2 F3
8
F4
A12 B12 A13 B13 A14 B14 A15 B15
9
F5
A0 B0 1 A1
2
F0 F1 F2 F3
8
F12
9
F13
B1 A2
B1 A2
19 18
11
F6
19 18
11
F14
B2 17 A3 16 B3
12
F7
B2 17 A3 16 B3
12
F15
U2
U4
ALU1
ALU3
F[15:0]
Copyright 1999 by John F. Wakerly
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Section *5.10
Adders, Subtractors, and ALUs
403
The 182 realizes each of these equations with just one level of delayan INVERT-OR-AND gate. When more than four ALUs are cascaded, they may be partitioned into supergroups, each with its own 182. For example, a 64-bit adder would have four supergroups, each containing four ALUs and a 182. The G_L and P_L outputs of each 182 can be combined in a next-level 182, since they indicate whether the supergroup generates or propagates carries:
G_L = ((G3 +P3) (G3 +G2 +P2) (G3 +G2 + G1 +P1) (G3 +G2 +G1 +G0)) P_L = (P0 P1 P2 P3)
*5.10.8 Adders in ABEL and PLDs ABEL supports addition (+) and subtraction (-) operators which can be applied to sets. Sets are interpreted as unsigned integers; for example, a set with n bits represents an integer in the range of 0 to 2n1. Subtraction is performed by negating the subtrahend and adding. Negation is performed in twos complement; that is, the operand is complemented bit-by-bit and then 1 is added. Table 5-53 shows an example of addition in ABEL. The set definition for SUM was made one bit wider than the addends to accommodate the carry out of the MSB; otherwise this carry would be discarded. The set definitions for the addends were extended on the left with a 0 bit to match the size of SUM. Even though the adder program is extremely small, it takes a long time to compile and it generates a huge number of terms in the minimal two level sum of products. While SUM0 has only two product terms, subsequent terms SUMi have 5 2i4 terms, or 636 terms for SUM7! And the carry out (SUM8) has 281=255 product terms. Obviously, adders with more than a few bits cannot be practically realized using two levels of logic.
module add title 'Adder Exercise'
" Input and output pins A7..A0, B7..B0 pin; SUM8..SUM0 pin istype 'com'; " Set definitions A = [0, A7..A0]; B = [0, B7..B0]; SUM = [SUM8..SUM0]; equations SUM = A + B; end add
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Ta b l e 5 - 5 3 ABEL program for an 8-bit adder. Copying Prohibited
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@CARRY directive
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CARRYING ON The carry out (SUM8) in our adder example has the exactly same number of product terms (255) as the less-than or greater-than output of an 8-bit comparator. This is less surprising once you realize that the carry out from the addition A+B is functionally equivalent to the expression A>B. Copyright 1999 by John F. Wakerly
Recognizing that larger adders and comparators are still needed in PLDs from time to time, ABEL provides an @CARRY directive which tells the compiler to synthesize group-ripple adder with n bits per group. For example, if the statement @CARRY 1; were included in Table 5-53, the compiler would create eight new signals for the carries out of bit positions 0 through 7. The equations for SUM1 through SUM8 would use these internal carries, essentially creating an 8-stage ripple adder with a worst-case delay of eight passes through the PLD. If the statement @CARRY 2; were used, the compiler would compute carries two bits at a time, creating four new signals for carries out of bit positions 1, 3, 5, and 7. In this case, the maximum number of product terms needed for any output is still reasonable, only 7, and the worst-case delay path has just four passes through the PLD. With three bits per group (@CARRY 3;), the maximum number of product terms balloons to 28, which is impractical. A special case that is often used in ABEL and PLDs is adding or subtracting a constant 1. This operation is used in the definition of counters, where the next state of the counter is just the current state plus 1 for an up counter or minus 1 for a down counter. The equation for bit i of an up counter can be stated very simply in words: Complement bit i if counting is enabled and all of the bits lower than i are 1. This requires just i+2 product terms for any value of i, and can be further reduced to just one product term and an XOR gate in some PLDs, as shown in Sections 10.5.1 and 10.5.3. *5.10.9 Adders in VHDL Although VHDL has addition (+) and subtraction (-) operators built in, they only work with the integer, real, and physical types. They specifically do not work with BIT_VECTOR types or the IEEE standard type STD_LOGIC_VECTOR. Instead, standard packages define these operators. As we explained in Section 5.9.6, the IEEE_std_logic_arith package defines two new array types, SIGNED and UNSIGNED, and a set of comparison functions for operands of type INTEGER, SIGNED, or UNSIGNED. The package also defines addition and subtraction operations for the same kinds of operands as well as STD_LOGIC and STD_ULOGIC for 1-bit operands. The large number of overlaid addition and subtraction functions may make it less than obvious what type an addition or subtraction result will have. Normally, if any of the operands is type SIGNED, the result is SIGNED, else the result is UNSIGNED. However, if the result is assigned to a signal or variable of
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity vadd is port ( A, B: in UNSIGNED (7 downto 0); C: in SIGNED (7 downto 0); D: in STD_LOGIC_VECTOR (7 downto 0); S: out UNSIGNED (8 downto 0); T: out SIGNED (8 downto 0); U: out SIGNED (7 downto 0); V: out STD_LOGIC_VECTOR (8 downto 0) ); end vadd; architecture vadd_arch of vadd is begin S <= ('0' & A) + ('0' & B); T <= A + C; U <= C + SIGNED(D); V <= C - UNSIGNED(D); end vadd_arch;
type STD_LOGIC_VECTOR, then the SIGNED or UNSIGNED result is converted to that type. The length of any result is normally the length of the longest operand. However, when an UNSIGNED operand is combined with a SIGNED or INTEGER operand, its length is increased by 1 to accommodate a sign bit of 0, and then the results length is determined. Incorporating these considerations, the VHDL program in Table 5-54 shows 8-bit additions for various operand and result types. The first result, S, is declared to be 9 bits long assuming the designer is interested in the carry from the 8-bit addition of UNSIGNED operands A and B. The concatenation operator & is used to extend A and B so that the addition function will return the carry bit in the MSB of the result. The next result, T, is also 9 bits long, since the addition function extends the UNSIGNED operand A when combining it with the SIGNED operand C. In the third addition, an 8-bit STD_LOGIC_VECTOR D is type-converted to SIGNED and combined with C to obtain an 8-bit SIGNED result U. In the last statement, D is converted to UNSIGNED, automatically extended by one bit, and subtracted from C to produce a 9-bit result V. Since addition and subtraction are fairly expensive in terms of the number of gates required, many VHDL synthesis engines will attempt to reuse adder blocks whenever possible. For example, Table 5-55 is a VHDL program that includes two different additions. Rather than building two adders and selecting
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Ta b l e 5 - 5 4 VHDL program for adding and subtracting 8-bit integers of various types.
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combinational multiplier
product component
Figure 5-96 Partial products in an 8 8 multiplier.
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Ta b l e 5 - 5 5 VHDL program that allows adder sharing.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity vaddshr is port ( A, B, C, D: in SIGNED (7 downto 0); SEL: in STD_LOGIC; S: out SIGNED (7 downto 0) ); end vaddshr; architecture vaddshr_arch of vaddshr is begin S <= A + B when SEL = '1' else C + D; end vaddshr_arch;
ones output with a multiplexer, the synthesis engine can build just one adder and select its inputs using multiplexers, potentially creating a smaller overall circuit.
*5.11 Combinational Multipliers
*5.11.1 Combinational Multiplier Structures In Section 2.8, we outlined an algorithm that uses n shifts and adds to multiply n-bit binary numbers. Although the shift-and-add algorithm emulates the way that we do paper-and-pencil multiplication of decimal numbers, there is nothing inherently sequential or time dependent about multiplication. That is, given two n-bit input words X and Y, it is possible to write a truth table that expresses the 2n-bit product P = X Y as a combinational function of X and Y. A combinational multiplier is a logic circuit with such a truth table. Most approaches to combinational multiplication are based on the paperand-pencil shift-and-add algorithm. Figure 5-96 illustrates the basic idea for an 8 8 multiplier for two unsigned integers, multiplicand X = x7x6x5x4x3x2x1x0 and multiplier Y = y7y6y5y4y3y2y1y0. We call each row a product component, a shifted
y0x7 y0x6 y0x5 y0x4 y0x3 y0x2 y0x1 y0x0
y1x7 y1x6 y1x5 y1x4 y1x3 y1x2 y1x1 y1x0
y2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2x1 y2x0
y3x7 y3x6 y3x5 y3x4 y3x3 y3x2 y3x1 y3x0
y4x7 y4x6 y4x5 y4x4 y4x3 y4x2 y4x1 y4x0
y5x7 y5x6 y5x5 y5x4 y5x3 y5x2 y5x1 y5x0
y6x7 y6x6 y6x5 y6x4 y6x3 y6x2 y6x1 y6x0
y7x7 y7x6 y7x5 y7x4 y7x3 y7x2 y7x1 y7x0 p14 p13 p12 p11 p10 p9 p8 p7
p15
p6
p5
p4
p3
p2
p1
p0
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y0x0
Figure 5-97 Interconnections for an 8 8 combinational multiplier.
p15
multiplicand that is multiplied by 0 or 1 depending on the corresponding multiplier bit. Each small box represents one product-component bit yixj, the logical AND of multiplier bit yi and multiplicand bit xj. The product P = p15p14 . .. p2p1p0 has 16 bits and is obtained by adding together all the product components. Figure 5-97 shows one way to add up the product components. Here, the product-component bits have been spread out to make space, and each + box is a full adder equivalent to Figure 5-85(c) on page 391. The carries in each row of full adders are connected to make an 8-bit ripple adder. Thus, the first ripple adder combines the first two product components to product the first partial product, as defined in Section 2.8. Subsequent adders combine each partial product with the next product component. It is interesting to study the propagation delay of the circuit in Figure 5-97. In the worst case, the inputs to the least significant adder (y0x1 and y1x0) can affect the MSB of the product (p15). If we assume for simplicity that the delays from any input to any output of a full adder are equal, say tpd, then the worst case
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y1x7 y1x3 0 y2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2 x1 y2x0 0 y3x7 y3x6 y3x5 y3x4 y3x3 y3x2 y3x1 y3x0 0 y4 x7 y4x6 y4x5 y4x4 y4x3 y4x2 y4x1 y4x0 0 y 5x 7 y5 x6 y5x5 y5x4 y5x3 y5x2 y5x1 y5x0 0 y6x7 y 6x 6 y6 x5 y6 x4 y6x3 y6x2 y6x1 y6x0 0 y7 x7 y7x6 y 7x 5 y7x4 y7x3 y7x2 y7x1 y7x0 0 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1
p0
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y0x7 y1x6 y0x6 y1x5 y0x5 y1x4 y0x4 y0 x3 y1 x2 y0x2 y1x1 y0 x1 y1 x0 y0x0
Figure 5-98 Interconnections for a faster 8 8 combinational multiplier.
p15
sequential multiplier
carry-save addition
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y1x7 y1x3 0 0 0 0 0 0 0 y2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2 x1 y2x0 y3x7 y3x6 y3x5 y3x4 y3x3 y3x2 y3x1 y3x0 y4 x7 y4x6 y4x5 y4x4 y4x3 y4x2 y4x1 y4x0 y 5x 7 y5 x6 y5x5 y5x4 y5x3 y5x2 y5x1 y5x0 y6x7 y 6x 6 y6 x5 y6 x4 y6x3 y6x2 y6x1 y6x0 y7 x7 y7x6 y 7x 5 y7x4 y7x3 y7x2 y7x1 y7x0 0 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1
p0
path goes through 20 adders and its delay is 20tpd. If the delays are different, then the answer depends on the relative delays; see Exercise \exref{xxxx}. Sequential multipliers use a single adder and a register to accumulate the partial products. The partial-product register is initialized to the first product component, and for an n n-bit multiplication, n1 steps are taken and the adder is used n1 times, once for each of the remaining n1 product components to be added to the partial-product register. Some sequential multipliers use a trick called carry-save addition to speed up multiplication. The idea is to break the carry chain of the ripple adder to shorten the delay of each addition. This is done by applying the carry output from bit i during step j to the carry input for bit i+1 during the next step, j+1. After the last product component is added, one more step is needed in which the
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carries are hooked up in the usual way and allowed to ripple from the least to the most significant bit. The combinational equivalent of an 8 8 multiplier using carry-save addition is shown in Figure 5-98. Notice that the carry out of each full adder in the first seven rows is connected to an input of an adder below it. Carries in the eighth row of full adders are connected to create a conventional ripple adder. Although this adder uses exactly the same amount of logic as the previous one (64 2-input AND gates and 56 full adders), its propagation delay is substantially shorter. Its worst-case delay path goes through only 14 full adders. The delay can be further improved by using a carry lookahead adder for the last row. The regular structure of combinational multipliers make them ideal for VLSI and ASIC realization. The importance of fast multiplication in microprocessors, digital video, and many other applications has led to much study and development of even better structures and circuits for combinational multipliers; see the References. *5.11.2 Multiplication in ABEL and PLDs ABEL provides a multiplication operator *, but it can be used only with individual signals, numbers, or special constants, not with sets. Thus, ABEL cannot synthesize a multiplier circuit from a single equation like P = X*Y. Still, you can use ABEL to specify a combinational multiplier if you break it down into smaller pieces. For example, Table 5-56 shows the design of a 4 4 unsigned multiplier following the same general structure as Figure 5-96 on page page 406. Expressions are used to define the four product components, PC1, PC2, PC3, and PC4, which are then added in the equations section of the program. This does not generate an array of full adders as in Figure 5-97 or 5-98. Rather, the ABEL compiler will dutifully crunch the addition equation to promodule mul4x4 title '4x4 Combinational Multiplier'
X3..X0, Y3..Y0 pin; " multiplicand, multiplier P7..P0 pin istype 'com'; " product P= PC1 PC2 PC3 PC4 [P7..P0]; = Y0 & [0, 0, 0, 0,X3,X2,X1,X0]; = Y1 & [0, 0, 0,X3,X2,X1,X0, 0]; = Y2 & [0, 0,X3,X2,X1,X0, 0, 0]; = Y3 & [0,X3,X2,X1,X0, 0, 0, 0];
equations P = PC1 + PC2 + PC3 + PC4; end mul4x4
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Ta b l e 5 - 5 6 ABEL program for a 44 combinational multiplier. Copying Prohibited
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Figure 5-99 VHDL variable names for the 8 8 multiplier.
PCS(6)(7)
PCS(7)(7)
p15
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PCS(0)(j) y0x7 y1x6 y0x6 y1x5 y0x5 y1x4 y0x4 y0 x3 y1 x2 y0x2 y1x1 y0 x1 y1 x0 y1x7 y1x3 PCS(1)(7) PCC(1)(6) PCS(1)(6) 0 0 0 0 0 0 0 y2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2 x1 y2x0 PCC (0)(0) y6x7 PCS(2)(7) PCC PCS (1)(0) (2)(0) y7 x7 y7x6 y 7x 5 y7x4 y3x7 y7x3 y3x6 y7x2 y3x5 y7x1 y3x4 y7x0 y3x3 y3x2 y3x1 y3x0 0 PCS (7)(0) PCS (3)(0) PCS (2)(0) p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 RAC(7) RAC(6) RAC(5) RAS(3) RAS(2) RAS(1) RAC(1) RAC(0)
duce a minimal sum for each of the eight product output bits. Surprisingly, the worst-case output, P4, has only 36 product terms, a little high but certainly realizable in two passes through a PLD.
*5.11.3 Multiplication in VHDL VHDL is rich enough to express multiplication in a number of different ways; well save the best for last. Table 5-57 is a behavioral VHDL program that mimics the multiplier structure of Figure 5-98. In order to represent the internal signals in the figure, the program defines a new data type, array8x8, which is a two-dimensional array of STD_LOGIC (recall that STD_LOGIC_VECTOR is a one-dimensional array of STD_LOGIC). Variable PC is declared as a such an array to hold the productcomponent bits, and variables PCS and PCC are similar arrays to hold the sum and carry outputs of the main array of full adders. One-dimensional arrays RAS and RAC hold the sum and carry outputs of the ripple adder. Figure 5-99 shows the variable naming and numbering scheme. Integer variables i and j are used as loop indices for rows and columns, respectively. The program attempts to illustrate the logic gates that would be used in a faithful realization of Figure 5-98, even though a synthesizer could legitimately create quite a different structure from this behavioral program. If you want to control the structure, then you must use structural VHDL, as well show later. In the program, the first, nested for statement performs 64 AND operations to obtain the product-component bits. The next for loop initializes boundary conditions at the top of the multiplier, using the notion of row-0 virtual full adders, not shown in the figure, whose sum outputs equal the first row of PC bits
y0x0
PCS (0)(0)
p0
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library IEEE; use IEEE.std_logic_1164.all;
entity vmul8x8p is port ( X: in STD_LOGIC_VECTOR (7 downto 0); Y: in STD_LOGIC_VECTOR (7 downto 0); P: out STD_LOGIC_VECTOR (15 downto 0) ); end vmul8x8p;
architecture vmul8x8p_arch of vmul8x8p is function MAJ (I1, I2, I3: STD_LOGIC) return STD_LOGIC is begin return ((I1 and I2) or (I1 and I3) or (I2 and I3)); end MAJ; begin process (X, Y) type array8x8 is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0); variable PC: array8x8; -- product component bits variable PCS: array8x8; -- full-adder sum bits variable PCC: array8x8; -- full-adder carry output bits variable RAS, RAC: STD_LOGIC_VECTOR (7 downto 0); -- ripple adder sum begin -and carry bits for i in 0 to 7 loop for j in 0 to 7 loop PC(i)(j) := Y(i) and X(j); -- compute product component bits end loop; end loop; for j in 0 to 7 loop PCS(0)(j) := PC(0)(j); -- initialize first-row "virtual" PCC(0)(j) := '0'; -adders (not shown in figure) end loop; for i in 1 to 7 loop -- do all full adders except last row for j in 0 to 6 loop PCS(i)(j) := PC(i)(j) xor PCS(i-1)(j+1) xor PCC(i-1)(j); PCC(i)(j) := MAJ(PC(i)(j), PCS(i-1)(j+1), PCC(i-1)(j)); PCS(i)(7) := PC(i)(7); -- leftmost "virtual" adder sum output end loop; end loop; RAC(0) := '0'; for i in 0 to 6 loop -- final ripple adder RAS(i) := PCS(7)(i+1) xor PCC(7)(i) xor RAC(i); RAC(i+1) := MAJ(PCS(7)(i+1), PCC(7)(i), RAC(i)); end loop; for i in 0 to 7 loop P(i) <= PCS(i)(0); -- first 8 product bits from full-adder sums end loop; for i in 8 to 14 loop P(i) <= RAS(i-8); -- next 7 bits from ripple-adder sums end loop; P(15) <= RAC(7); -- last bit from ripple-adder carry end process; end vmul8x8p_arch;
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Ta b l e 5 - 5 7 Behavioral VHDL program for an 8 8 combinational multiplier.
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ON THE THRESHOLD OF A DREAM
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SIGNALS VS. VARIABLES Variables are used rather than signals in the process in Table 5-57 to make simulation run faster. Variables are faster because the simulator keeps track of their values only when the process is running. Because variable values are assigned sequentially, the process in Table 5-57 is carefully written to compute values in the proper order. That is, a variable cannot be used until a value has been assigned to it. Signals, on the other hand, have a value at all times. When a signal value is changed in a process, the simulator schedules a future event in its event list for the value change. If the signal appears on the right-hand side of an assignment statement in the process, then the signal must also be included in the process sensitivity list. If a signal value changes, the process will then execute again, and keep repeating until all of the signals in the sensitivity list are stable. In Table 5-57, if you wanted to observe internal values or timing during simulation, you could change all the variables (except i and j) to signals and include them in the sensitivity list. To make the program syntactically correct, you would also have to move the type and signal declarations to just after the architecture statement, and change all of the := assignments to <=. Suppose that after making the changes above, you also reversed the order of the indices in the for loops (e.g., 7 downto 0 instead of 0 to 7). The program would still work. However, dozens of repetitions of the process would be required for each input change in X or Y, because the signal changes in this circuit propagate from the lowest index to the highest. While the choice of signals vs. variables affects the speed of simulation, with most VHDL synthesis engines it does not affect the results of synthesis. A three-input majority function, MAJ, is defined at the beginning of Table 5-57 and is subsequently used to compute carry outputs. An n-input majority function produces a 1 output if the majority of its inputs are 1, two out of three in the case of a 3-input majority function. (If n is even, n/2+1 inputs must be 1.) Over thirty years ago, there was substantial academic interest in a more general class of n-input threshold functions which produce a 1 output if k or more of their inputs are 1. Besides providing full employment for logic theoreticians, threshold functions could realize many logic functions with a smaller number of elements than could a conventional AND/OR realization. For example, an adders carry function requires three AND gates and one OR gate, but just one three-input threshold gate. (Un)fortunately, an economical technology never emerged for threshold gates, and they remain, for now, an academic curiosity. Copyright 1999 by John F. Wakerly
and whose carry outputs are 0. The third, nested for loop corresponds to the main array of adders in Figure 5-98, all except the last row, which is handled by the fourth for loop. The last two for loops assign the appropriate adder outputs to the multiplier output signals.
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architecture vmul8x8s_arch of vmul8x8s is component AND2 port( I0, I1: in STD_LOGIC; O: out STD_LOGIC ); end component; component XOR3 port( I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC ); end component; component MAJ -- Majority function, O = I0*I1 + I0*I2 + I1*I2 port( I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC ); end component;
type array8x8 is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0); signal PC: array8x8; -- product-component bits signal PCS: array8x8; -- full-adder sum bits signal PCC: array8x8; -- full-adder carry output bits signal RAS, RAC: STD_LOGIC_VECTOR (7 downto 0); -- sum, carry begin g1: for i in 0 to 7 generate -- product-component bits g2: for j in 0 to 7 generate U1: AND2 port map (Y(i), X(j), PC(i)(j)); end generate; end generate; g3: for j in 0 to 7 generate PCS(0)(j) <= PC(0)(j); -- initialize first-row "virtual" adders PCC(0)(j) <= '0'; end generate; g4: for i in 1 to 7 generate -- do full adders except the last row g5: for j in 0 to 6 generate U2: XOR3 port map (PC(i)(j),PCS(i-1)(j+1),PCC(i-1)(j),PCS(i)(j)); U3: MAJ port map (PC(i)(j),PCS(i-1)(j+1),PCC(i-1)(j),PCC(i)(j)); PCS(i)(7) <= PC(i)(7); -- leftmost "virtual" adder sum output end generate; end generate; RAC(0) <= '0'; g6: for i in 0 to 6 generate -- final ripple adder U7: XOR3 port map (PCS(7)(i+1), PCC(7)(i), RAC(i), RAS(i)); U3: MAJ port map (PCS(7)(i+1), PCC(7)(i), RAC(i), RAC(i+1)); end generate; g7: for i in 0 to 7 generate P(i) <= PCS(i)(0); -- get first 8 product bits from full-adder sums end generate; g8: for i in 8 to 14 generate P(i) <= RAS(i-8); -- get next 7 bits from ripple-adder sums end generate; P(15) <= RAC(7); -- get last bit from ripple-adder carry end vmul8x8s_arch;
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Ta b l e 5 - 5 8 Structural VHDL architecture for an 88 combinational multiplier.
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generate statement
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Ta b l e 5 - 5 9 Truly behavioral VHDL program for an 88 combinational multiplier.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity vmul8x8i is port ( X: in UNSIGNED (7 downto 0); Y: in UNSIGNED (7 downto 0); P: out UNSIGNED (15 downto 0) ); end vmul8x8i; architecture vmul8x8i_arch of vmul8x8i is begin P <= X * Y; end vmul8x8i_arch;
The program in Table 5-57 can be modified to use structural VHDL as shown in Table 5-58. This approach gives the designer complete control over the circuit structure that is synthesized, as might be desired in an ASIC realization. The program assumes that the architectures for AND2, XOR3, and MAJ3 have been defined elsewhere, for example, in an ASIC library. This program makes good use of the generate statement to create the arrays of components used in the multiplier. The generate statement must have a label, and similar to a for-loop statement, it specifies an iteration scheme to control the repetition of the enclosed statements. Within for-generate, the enclosed statements can include any concurrent statements, IF-THEN-ELSE statements, and additional levels of looping constructs. Sometimes generate statements are combined with IF-THEN-ELSE to produce a kind of conditional compilation capability Well, we said wed save the best for last, and here it is. The IEEE std_logic_arith library that we introduced in Section 5.9.6 defines multiplication functions for SIGNED and UNSIGNED types, and overlays these functions onto the * operator. Thus, the program in Table 5-59 can multiply unsigned numbers with a simple one-line assignment statement. Within the IEEE library, the multiplication function is defined behaviorally, using the shift-and-add algorithm. We could have showed you this approach at the beginning of this subsection, but then you wouldnt have read the rest of it, would you?
References
Digital designers who want to write better should start by reading the classic Elements of Style, 3rd ed., by William Strunk, Jr. and E. B. White (Allyn & Bacon, 1979). Another book on writing style, especially for nerds, is Effective
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Writing for Engineers, Managers, and Scientists, 2nd ed., by H. J. Tichy (Wiley, 1988). Plus two new books from Amazon. The ANSIIEEE standard for logic symbols is Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions. Another standard of interest to logic designers is ANSI/IEEE 991-1986, Logic Circuit Diagrams. These two standards and ten others, including standard symbols for 10-inch gongs and maidssignal plugs, can be found in one handy, five-pound reference, Electrical and Electronics Graphic and Letter Symbols and Reference Designations Standards Collection Electrical and Electronics Graphics Symbols and Reference Designations published by the IEEE in 1996 (www.ieee.org). Real logic devices are described in data sheets and data books published by the manufacturers. Updated editions of data books used to be published every few years, but in recent years the trend has been to minimize or eliminate the hardcopy editions and instead to publish up-to-date information on the web. Two of the largest suppliers with the most comprehensive sites are Texas Instruments (www.ti.com) and Motorola (www.mot.com). For a given logic family such as 74ALS, all manufacturers list generally equivalent specifications, so you can get by with just one data book per family. Some specifications, especially timing, may vary slightly between manufacturers, so when timing is tight its best to check a couple of different sources and use the worst case. Thats a lot easier than convincing your manufacturing department to buy a component only from a single supplier. The first PAL devices were invented in 1978 by John Birkner at Monolithic Memories, Inc. (MMI). Birkner earned U.S. patent number 4,124,899 for his invention, and MMI rewarded him by buying him a brand new Porsche! Seeing the value in this technology (PALs, not Porsches), Advanced Micro Devices (AMD) acquired MMI in the early 1980s and remained a leading developer and supplier of new PLDs and CPLDs. In 1997, AMD spun off its PLD operations to form Vantis Corporation.
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SYNTHESIS OF BEHAVIORAL DESIGNS Youve probably heard that compilers for high-level programming languages like C usually generate better code than people do writing in assembly language, even with hand-tweaking. Most digital designers hope that compilers for behavioral HDLs will also some day produce results superior to a typical hand-tweaked design, be it a schematic or structural VHDL. Better compilers wont put the designers out of work, they will simply allow them to tackle bigger designs. Were not quite there yet. However, the more advanced synthesis engines do include some nice optimizations for commonly used behavioral structures. For example, I have to admit that the FPGA synthesis engine that I used to test the VHDL programs in this subsection produced just as fast a multiplier from Table 5-59 as it did from any of the more detailed architectures! Copying Prohibited
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5.1 5.2 5.3 5.4 5.5 5.6 5.7 Copyright 1999 by John F. Wakerly
Some of the best resources for learning about PLD-based design are provided the PLD manufacturers. For example, Vantis publishes the 1999 Vantis Data Book (Sunnyvale, CA 94088, 1999), which contains information on their PLDs, CPLDs, and FPGAs. Individual data sheets and application notes are readily downloadable from their web site (www.vantis.com). Similarly, GAL inventor Lattice Semiconductor has a comprehensive Lattice Data Book (Hillsboro, OR 97124, 1999) and web site (www.latticesemi.com). A much more detailed discussion of the internal operation of LSI and VLSI devices, including PLDs, ROMs, and RAMs, can be found in electronics texts such as M icroelectronics, 2nd ed., by J.Millman and A.Grabel (McGraw-Hill, 1987) and VLSI Engineering by Thomas E. Dillinger (Prentice Hall, 1988). Additional PLD references are cited at the end of \chapref{SeqPLDs}. On the technical side of digital design, lots of textbooks cover digital design principles, but only a few cover practical aspects of design. A classic is Digital Design with Standard MSI and LSI by Thomas R. Blakeslee, 2nd ed. (Wiley, 1979), which includes chapters on everything from structured combinational design with MSI and LSI to the social consequences of engineering. A more recent, excellent short book focusing on digital design practices is The Well-Tempered Digital Design by Robert B. Seidensticker (Addison-Wesley, 1986). It contains hundreds of readily accessible digital-design proverbs in areas ranging from high-level design philosophy to manufacturability. Another easy-reading, practical, and fun book on analog and digital design is Clive Maxfields Bebop to the Boolean Boogie (LLH Technology Publishing, 1997; for a good time, also visit www.maxmon.com).
Give three examples of combinational logic circuits that require billions and billions of rows to describe in a truth table. For each circuit, describe the circuits inputs and output(s), and indicate exactly how many rows the truth table contains; you need not write out the truth table. (Hint: You can find several such circuits right in this chapter.) Draw the DeMorgan equivalent symbol for a 74x30 8-input NAND gate. Draw the DeMorgan equivalent symbol for a 74x27 3-input NOR gate. Whats wrong with the signal name READY ? You may find it annoying to have to keep track of the active levels of all the signals in a logic circuit. Why not use only noninverting gates, so all signals are active high? True or false: In bubble-to-bubble logic design, outputs with a bubble can be connected only to inputs with a bubble. A digital communication system is being designed with twelve identical network ports. Which type of schematic structure is probably most appropriate for the design? Copying Prohibited
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5.8
IN
5.9 Repeat Drill 5.8, substituting 74HCT00s for the 74LS00s. 5.10 Repeat Drill 5.8, substituting 74LS08s for the 74LS00s. 5.11 Repeat Drill 5.8, substituting 74AHCT02s for the 74LS00s, using constant 0 instead of constant 1 inputs, and using typical rather than maximum timing. 5.12 Estimate the minimum propagation delay from IN to OUT for the circuit shown in Figure X5.12. Justify your answer.
74LS86 74LS86 74LS86 74LS86
4
5.13 Determine the exact maximum propagation delay from IN to OUT of the circuit in Figure X5.12 for both LOW-to-HIGH and HIGH-to-LOW transitions, using the timing information given in Table 5-2. Repeat, using a single worst-case delay number for each gate and compare and comment on your results. 5.14 Repeat Drill 5.13, substituting 74HCT86s for the 74LS86s. 5.15 Which would expect to be faster, a decoder with active-high outputs or one with active-low outputs? 5.16 Using the information in Table 5-3 for 74LS components, determine the maximum propagation delay from any input to any output in the 5-to-32 decoder circuit of Figure 5-39. You may use the worst-case analysis method. 5.17 Repeat Drill 5.16, performing a detailed analysis for each transition direction, and compare your results. 5.18 Show how to build each of the following single- or multiple-output logic functions using one or more 74x138 or 74x139 binary decoders and NAND gates. (Hint: Each realization should be equivalent to a sum of minterms.) (a) F = X,Y,Z(2,4,7) (b) F = A,B,C(3,4,5,6,7) (c) F = A,B,C,D(2,4,6,14) (d) F = W,X,Y,Z(0,1,2,3,5,7,11,13) (f) F = A,B,C(0,4,6)
G = C,D,E(1,2) G = W,X,Y(2,3,4,7)
5.19 Draw the digits created by a 74x49 seven-segment decoder for the nondecimal inputs 1010 through 1111. Copyright 1999 by John F. Wakerly
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Determine the exact maximum propagation delay from IN to OUT of the circuit in Figure X5.8 for both LOW-to-HIGH and HIGH-to-LOW transitions, using the timing information given in Table 5-2. Repeat, using a single worst-case delay number for each gate and compare and comment on your results.
74LS00 74LS00 74LS00 74LS00
12 13
74LS00
74LS00
1
1 2
1
4 5
1
9
1
1
1 2
1
4 5
3
6
10
8
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3
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OUT
U1
U1
U1
U1
U2
U2
Figure X5.8
1
1 2
0
0
9
1
12 13
3
6
8
11
OUT
5
10
IN
U1
U1
U1
U1
Figure X5.12
(e) F = W,X,Y(1,3,5,6)
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74x139 EN_L
1
5.20 Starting with the logic diagram for the 74x148 priority encoder, write logic equations for its A2_L, A1_L, and A0_L outputs. How do they differ from the generic equations given in Section 5.5.1? 5.21 Whats terribly wrong with the circuit in Figure X5.21? Suggest a change that eliminates the terrible problem.
1G 1A 1B 1Y0 1Y1 1Y2 1Y3
4 5 6 7
SELP_L SELQ_L SELR_L SELS_L SELT_L SELU_L
1-bit party-line
ASRC0 ASRC1
2 3
P
15
2G 2A 2B
BSRC0 BSRC1
14 13
2Y0 2Y1 2Y2 2Y3
12 11 10 9
Q
SELV_L SELW_L
R
S
T
Figure X5.21
U
V
W
SDATA
5.22 Using the information in Tables 5-2 and 5-3 for 74LS components, determine the maximum propagation delay from any input to any output in the 32-to-1 multiplexer circuit of Figure 5-65. You may use the worst-case analysis method. 5.23 Repeat Exercise 5.22 using 74HCT components. 5.24 An n-input parity tree can be built with XOR gates in the style of Figure 5-73(a). Under what circumstances does a similar n-input parity tree built using XNOR gates perform exactly the same function? 5.25 Using the information in Tables 5-2 and 5-3 for 74LS components, determine the maximum propagation delay from the DU bus to the DC bus in the error-correction circuit of Figure 5-76. You may use the worst-case analysis method. 5.26 Repeat Exercise 5.25 using 74HCT components. 5.27 Starting with the equations given in Section 5.9.4, write a complete logic expression for the ALTBOUT output of the 74x85. 5.28 Starting with the logic diagram for the 74x682, write a logic expression for the PGTQ_L output in terms of the inputs.
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5.29 Write an algebraic expression for s2, the third sum bit of a binary adder, as a function of inputs x0, x1, x2, y0, y1, and y2. Assume that c0 = 0, and do not attempt to multiply out or minimize the expression. 5.30 Using the information in Table 5-3 for 74LS components, determine the maximum propagation delay from any input to any output of the 16-bit group ripple adder of Figure 5-91. You may use the worst-case analysis method.
Exercises
5.31 A possible definition of a BUT gate (Exercise 4.45) is Y1 is 1 if A1 and B1 are 1 but either A2 or B2 is 0; Y2 is defined symmetrically. Write the truth table and find minimal sum-of-products expressions for the BUT-gate outputs. Draw the logic diagram for a NAND-NAND circuit for the expressions, assuming that only uncomplemented inputs are available. You may use gates from 74HCT00, 04, 10, 20, and 30 packages. 5.32 Find a gate-level design for the BUT gate defined in Exercise 5.31 that uses a minimum number of transistors when realized in CMOS. You may use gates from 74HCT00, 02, 04, 10, 20, and 30 packages. Write the output expressions (which need not be two-level sums-of-products), and draw the logic diagram. 5.33 For each circuit in the two preceding exercises, compute the worst-case delay from input to output, using the delay numbers for 74HCT components in Table 5-2. Compare the cost (number of transistors), speed, and input loading of the two designs. Which is better? 5.34 Butify the function F = W,X,Y,Z(3,7,11,12,13,14). That is, show how to perform F with a single BUT gate as defined in Exercise 5.31 and a single 2-input OR gate. 5.35 Design a 1-out-of-4 checker with four inputs, A, B, C, D, and a single output ERR. The output should be 1 if two or more of the inputs are 1, and 0 if no input or one input is 1. Use SSI parts from Figure 5-18, and try to minimize the number of gates required. (Hint: It can be done with seven two-input inverting gates.) 5.36 Suppose that a 74LS138 decoder is connected so that all enable inputs are asserted and C B A = 101. Using the information in Table 5-3 and the 138 internal logic diagram, determine the propagation delay from input to all relevant outputs for each possible single-input change. (Hint: There are a total of nine delay numbers, since a change on A, B, or C affects two outputs, and a change on any of the three enable inputs affects one output.) 5.37 Suppose that you are asked to design a new component, a decimal decoder that is optimized for applications in which only decimal input combinations are expected to occur. How can the cost of such a decoder be minimized compared to one that is simply a 4-to-16 decoder with six outputs removed? Write the logic equations for all ten outputs of the minimized decoder, assuming active-high inputs and outputs and no enable inputs. 5.38 How many Karnaugh maps would be required to work Exercise 5.37 using the formal multiple-output minimization procedure described in Section 4.3.8? 5.39 Suppose that a system requires a 5-to-32 binary decoder with a single active-low enable input, a design similar to Figure 5-39. With the EN1 input pulled HIGH, Copyright 1999 by John F. Wakerly
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Figure X5.41 5-44 5-45 5-46 5-47
either the EN2_L or the EN3_L input in the figure could be used as the enable, with the other input grounded. Discuss the pros and cons of using EN2_L versus EN3_L. 5.40 Determine whether the circuits driving the a, b, and c outputs of the 74x49 sevensegment decoder correspond to minimal product-of-sums expressions for these segments, assuming that the nondecimal input combinations are dont cares and BI = 1. 5.41 Redesign the MSI 74x49 seven-segment decoder so that the digits 6 and 9 have tails as shown in Figure X5.41. Are any of the digit patterns for nondecimal inputs 1010 through 1111 affected by your redesign?
5.42 Starting with the ABEL program in Table 5-21, write a program for a seven-segment decoder with the following enhancements:
The outputs are all active low. Two new inputs, ENHEX and ERRDET, control the decoding of the segment outputs. If ENHEX = 0, the outputs match the behavior of a 74x49. If ENHEX = 1, then the outputs for digits 6 and 9 have tails, and the outputs for digits AF are controlled by ERRDET. If ENHEX = 1 and ERRDET = 0, then the outputs for digits AF look like the letters AF, as in the original program. If ENHEX = 1 and ERRDET = 1, then the output for digits AF looks like the letter S.
5.43 A famous logic designer decided to quit teaching and make a fortune by fabricating huge quantities of the MSI circuit shown in Figure X5.47.
(a)Label the inputs and outputs of the circuit with appropriate signal names, including active-level indications. (b)What does the circuit do? Be specific and account for all inputs and outputs. (c)Draw the MSI logic symbol that would go on the data sheet of this wonderful device. (d)With what standard MSI parts does the new part compete? Do you think it would be successful in the MSI marketplace?
5.48 An FCT three-state buffer drives ten FCT inputs and a 4.7-K pull-up resistor to 5.0 V. When the output changes from LOW to Hi-Z, estimate how long it takes for the FCT inputs to see the output as HIGH . State any assumptions that you make. 5.49 On a three-state bus, ten FCT three-state buffers are driving ten FCT inputs and a 4.7-K pull-up resistor to 5.0 V. Assuming that no other devices are driving the bus, estimate how long the bus signal remains at a valid logic level when an active output enters the Hi-Z state. State any assumptions that you make. 5.50 Design a 10-to-4 encoder with inputs in the 1-out-of-10 code and outputs in BCD. 5.51 Draw the logic diagram for a 16-to-4 encoder using just four 8-input NAND gates. What are the active levels of the inputs and outputs in your design?
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5.52 Draw the logic diagram for a circuit that uses the 74x148 to resolve priority among eight active-high inputs, I0I7, where I7 has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If no input is asserted, then A2A0 should be 111 and an IDLE output should be asserted. You may use discrete gates in addition to the 148. Be sure to name all signals with the proper active levels. 5.53 Draw the logic diagram for a circuit that resolves priority among eight active-low inputs, I0_LI7_L, where I0_L has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If at least one input is asserted, then an AVALID output should be asserted. Be sure to name all signals with the proper active levels. This circuit can be built with a single 74x148 and no other gates. 5.54 A purpose of Exercise 5.53 was to demonstrate that it is not always possible to maintain consistency in active-level notation unless you are willing to define alternate logic symbols for MSI parts that can be used in different ways. Define an alternate symbol for the 74x148 that provides this consistency in Exercise 5.53. 5.55 Design a combinational circuit with eight active-low request inputs, R0_LR7_L, and eight outputs, A2A0, AVALID, B2B0, and BVALID . The R0_LR7_L inputs and A2A0 and AVALID outputs are defined as in Exercise 5.53. The B2B0 and BVALID outputs identify the second-highest priority request input that is asserted. Copyright 1999 by John F. Wakerly
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Figure X5.47
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barrel shifter
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Figure X5.59
Z
B
S
5.56 5.57 5.58
5.59
5.60
5-61
You should be able to design this circuit with no more than six SSI and MSI packages, but dont use more than 10 in any case. Repeat Exercise 5.55 using ABEL. Does the design fit into a single GAL20V8? Repeat Exercise 5.55 using VHDL. Design a 3-input, 5-bit multiplexer that fits in a 24-pin IC package. Write the truth table and draw a logic diagram and logic symbol for your multiplexer. Write the truth table and a logic diagram for the logic function performed by the CMOS circuit in Figure X5.59. (The circuit contains transmission gates, which were introduced in Section 3.7.1.) A famous logic designer decided to quit teaching and make a fortune by fabricating huge quantities of the MSI circuit shown in Figure X5.64.
(a)Label the inputs and outputs of the circuit with appropriate signal names, including active-level indications. (b)What does the circuit do? Be specific and account for all inputs and outputs. (c)Draw the MSI logic symbol that would go on the data sheet of this wonderful device. (d)With what standard MSI parts does the new part compete? Do you think it would be successful in the MSI marketplace?
5-62 5-63 5-64
5.65 A 16-bit barrel shifter is a combinational logic circuit with 16 data inputs, 16 data outputs, and 4 control inputs. The output word equals the input word, rotated by a number of bit positions specified by the control inputs. For example, if the input word equals ABCDEFGHIJKLMNOP (each letter represents one bit), and the control inputs are 0101 (5), then the output word is FGHIJKLMNOPABCDE. Design a 16-bit barrel shifter using combinational MSI parts discussed in this chapter. Your design should contain 20 or fewer ICs. Do not draw a complete schematic, but sketch and describe your design in general terms and indicate the types and total number of ICs required. 5.66 Write an ABEL program for the barrel shifter in Exercise 5.65. 5.67 Write a VHDL program for the barrel shifter in Exercise 5.65. 5.68 Show how to realize the 4-input, 18-bit multiplexer with the functionality described in Table 5-39 using 18 74x151s.
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5.69 Show how to realize the 4-input, 18-bit multiplexer with the functionality of Table 5-39 using 9 74x153s and a code converter with inputs S2S0 and outputs C1,C0 such that [C1,C0] = 0011 when S2S0 selects AD , respectively. 5.70 Design a 3-input, 2-output combinational circuit that performs the code conversion specified in the previous exercise, using discrete gates. 5.71 Add a three-state-output control input OE to the VHDL multiplexer program in Table 5-42. Your solution should have only one process. 5.72 A digital designer who built the circuit in Figure 5-75 accidentally used 74x00s instead of 08s in the circuit, and found that the circuit still worked, except for a change in the active level of the ERROR signal. How was this possible? 5.73 What logic function is performed by the CMOS circuit shown in Figure X5.73?
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Figure X5.64
A
Figure X5.73
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Figure X5.75
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A Z B C
5.74 An odd-parity circuit with 2n inputs can be built with 2n-1 XOR gates. Describe two different structures for this circuit, one of which gives a minimum worst-case input to output propagation delay and the other of which gives a maximum. For each structure, state the worst-case number of XOR-gate delays, and describe a situation where that structure might be preferred over the other. 5.75 Write the truth table and a logic diagram for the logic function performed by the CMOS circuit in Figure X5.75. 5.76 Write a 4-step iterative algorithm corresponding to the iterative comparator circuit of Figure 5-79. 5.77 Design a 16-bit comparator using five 74x85s in a tree-like structure, such that the maximum delay for a comparison equals twice the delay of one 74x85. 5.78 Starting with a manufacturers logic diagram for the 74x85, write a logic expression for the ALTBOUT output, and prove that it algebraically equals the expression derived in Drill 5.27. 5.79 Design a comparator similar to the 74x85 that uses the opposite cascading order. That is, to perform a 12-bit comparison, the cascading outputs of the high-order comparator would drive the cascading inputs of the mid-order comparator, and the mid-order outputs would drive the low-order inputs. You neednt do a complete logic design and schematic; a truth table and an application note showing the interconnection for a 12-bit comparison are sufficient.
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5.80 Design a 24-bit comparator using three 74x682s and additional gates as required. Your circuit should compare two 24-bit unsigned numbers P and Q and produce two output bits that indicate whether P = Q or P > Q. 5.81 Draw a 6-variable Karnaugh map for the s2 function of Drill 5.29, and find all of its prime implicants. Using the 6-variable map format of Exercise 4.66, label the variables in the order x0, y0, x2, y2, x1, y1 instead of U, V, W, X, Y, Z. You need not write out the algebraic product corresponding to each prime implicant; simply identify each one with a number (1, 2, 3, ) on the map. Then make a list that shows for each prime implicant whether or not it is essential and how many inputs are needed on the corresponding AND gate. 5.82 Starting with the logic diagram for the 74x283 in Figure 5-90, write a logic expression for the S2 output in terms of the inputs, and prove that it does indeed equal the third sum bit in a binary addition as advertised. You may assume that c0 = 0 (i.e., ignore c0). 5.83 Using the information in Table 5-3, determine the maximum propagation delay from any A or B bus input to any F bus output of the 16-bit carry lookahead adder of Figure 5-95. You may use the worst-case analysis method. 5.84 Referring to the data sheet of a 74S182 carry lookahead circuit, determine whether or not its outputs match the equations given in Section 5.10.7. 5.85 Estimate the number of product terms in a minimal sum-of-products expression for the c32 output of a 32-bit binary adder. Be more specific than billions and billions, and justify your answer. 5.86 Draw the logic diagram for a 64-bit ALU using sixteen 74x181s and five 74S182s for full carry lookahead (two levels of 182s). For the 181s, you need only show the CIN inputs and G_L and P_L outputs. 5.87 Show how to build all four of the following functions using one SSI package and one 74x138.
F 1 = X Y Z + X Y Z F3 = X Y Z + X Y Z F2 = X Y Z + X Y Z F4 = X Y Z + X Y Z
5.88 Design a customized decoder with the function table in Table X5.88 using MSI and SSI parts. Minimize the number of IC packages in your design.
CS_L A2 A1 A0
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Ta b l e X 5 . 8 8
1 0 0 0 0 0 0 0 0
x 0 0 0 0 1 1 1 1
x 0 x 1 x 0 x 1 x
x x 0 x 1 x 0 x 1
none
BILL_L MARY_L JOAN_L PAUL_L ANNA_L FRED_L DAVE_L KATE_L
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Ta b l e X 5 . 9 1
S2 S1 S0
5.89 Repeat Exercise 5.88 using ABEL and a single GAL16V8. 5.90 Repeat Exercise 5.88 using VHDL. 5.91 Using ABEL and a single GAL16V8, design a customized multiplexer with four 3-bit input buses P, Q, R, T, and three select inputs S2S0 that choose one of the buses to drive a 3-bit output bus Y according to Table X5.91.
Input to select
P P P Q P P R T
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
5.92 Design a customized multiplexer with four 8-bit input buses P, Q, R, and T, selecting one of the buses to drive a 8-bit output bus Y according to Table X5.91. Use two 74x153s and a code converter that maps the eight possible values on S2S0 to four select codes for the 153. Choose a code that minimizes the size and propagation delay of the code converter. 5.93 Design a customized multiplexer with five 4-bit input buses A, B, C, D, and E, selecting one of the buses to drive a 4-bit output bus T according to Table X5.93. You may use no more than three MSI and SSI ICs.
S2 S1 S0
Input to select
A B A C A D A E
Ta b l e X 5 . 9 3
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
5.94 Repeat Exercise 5.93 using ABEL and one or more PAL/GAL devices from this chapter. Minimize the number and size of the GAL devices. 5.95 Design a 3-bit equality checker with six inputs, SLOT[20] and GRANT[20], and one active-low output, MATCH_L. The SLOT inputs are connected to fixed values when the circuit installed in the system, but the GRANT values are changed on a cycle-by-cycle basis during normal operation of the system. Using only SSI and MSI parts that appear in Tables 5-2 and 5-3, design a comparator with the shortest possible maximum propagation delay from GRANT[20] to MATCH_L. (Note:
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The author had to solve this problem in real life to shave 2 ns off the criticalpath delay in a 25-MHz system design.) 5.96 Design a combinational circuit whose inputs are two 8-bit unsigned binary integers, X and Y, and a control signal MIN/MAX . The output of the circuit is an 8-bit unsigned binary integer Z such that Z = 0 if X = Y; otherwise, Z = min(X,Y) if MIN/ MAX = 1, and Z = m ax(X,Y) if MIN/MAX = 0. 5.97 Design a combinational circuit whose inputs are two 8-bit unsigned binary integers, X and Y, and whose output is an 8-bit unsigned binary integer Z = max(X,Y). For this exercise, you may use any of the 74x SSI and MSI components introduced in this chapter except the 74x682.
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comparator X >Y
max (X, Y) mux
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o far, we have looked at basic principles in several areasnumber systems, digital circuits, and combinational logicand we have described many of the basic building blocks of combinational designdecoders, multiplexers, and the like. All of that is a needed foundation, but the ultimate goal of studying digital design is eventually to be able to solve real problems by designing digital systems (well, duh). That usually requires experience beyond what you can get by reading a textbook. Well try to get you started by presenting a number of larger combinational design examples in this chapter. The chapter is divided into three sections. The first section gives design examples using combinational building blocks. While the examples are written in terms of MSI functions, the same functions are widely used in ASIC and schematic-based FPGA design. The idea of these examples is to show that you can often express a combinational function using a collection of smaller building blocks. This is important for a couple of reasons: a hierarchical approach usually simplifies the overall design task, and the smaller building blocks often have a more efficient, optimized realization in FPGA and ASIC cells than what youd get if you wrote a larger, monolithic description in an HDL and then just hit the synthesize button. The second section gives design examples using ABEL. These designs are all targeted to small PLDs such as 16V8s and 20V8s. Besides the general use of the ABEL language, some of the examples illustrate the partitioning
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barrel shifter
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decisions that a designer must make when an entire circuit does not fit into a single component. A VHDL-based approach is especially appropriate for larger designs that will be realized in a single CPLD, FPGA or ASIC, as described in the third section. You may notice that these examples do not target a specific CPLD or FPGA. Indeed, this is one of the benefits of HDL-based design; most or all of the design effort is portable and can be targeted to any of a variety of technologies. The only prerequisites for this chapter are the chapters that precede it. The three sections are written to be pretty much independent of each other, so you dont have to read about ABEL if youre only interested in VHDL, or vice versa. Also, the rest of the book is written so that you can read this chapter now or skip it and come back later.
6.1.1 Barrel Shifter A barrel shifter is a combinational logic circuit with n data inputs, n data outputs, and a set of control inputs that specify how to shift the data between input and output. A barrel shifter that is part of a microprocessor CPU can typically specify the direction of shift (left or right), the type of shift (circular, arithmetic, or logical), and the amount of shift (typically 0 to n1 bits, but sometimes 1 to n bits). In this subsection, well look at the design of a simple 16-bit barrel shifter that does left circular shifts only, using a 4-bit control input S[3:0] to specify the amount of shift. For example, if the input word is ABCDEFGHGIHKLMNOP (where each letter represents one bit), and the control input is 0101 (5), then the output word is FGHGIHKLMNOPABCDE. From one point of view, this problem is deceptively simple. Each output bit can be obtained from a 16-input multiplexer controlled by the shift-control inputs, which each multiplexer data input connected to the appropriate On the other hand, when you look at the details of the design, youll see that there are trade-offs in the speed and size of the circuit. Let us first consider a design that uses off-the-shelf MSI multiplexers. A 16-input, one-bit multiplexer can be built using two 74x151s, by applying S3 and its complement to the EN_L inputs and combining the Y_L data outputs with a NAND gate, as we showed in Figure 5-66 for a 32-input multiplexer. The loworder shift-control inputs, S2S0. connect to the like-named select inputs of the 151s. We complete the design by replicating this 16-input multiplexer 16 times and hooking up the data inputs appropriately, as shown in Figure 6-1. The top 151 of each pair is enabled by S3_L, and the bottom one by S3; the remaining select bits are connected to all 32 151s. Data inputs D 0D7 of each 151 are connected to the DIN inputs in the listed order from left to right.
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The first row of Table 6-1 shows the characteristics of this first approach. About 36 chips (32 74x151s, 4 74x00s, and 1/6 74x04) are used in the MSI/SSI realization. We can reduce this to 32 chips by replacing the 74x151s with 74x251s and tying their three-state Y outputs together, as tabulated in the second row. Both of these designs have very heavy loading on the control inputs; each of the control bits S[2:0] must be connected to the like-named select input of all 32 multiplexers. The data inputs are also fairly heavily loaded; each data bit must connect to 16 different multiplexer data inputs, corresponding to the 16 possible shift amounts. However, assuming that the heavy control and data loads dont slow things down too much, the 74x251-based approach yields the shortest data delay, with each data bit passing through just one multiplexer. Alternatively, we could build the barrel shifter using 16 74x157 2-input, 4-bit multiplexers, as tabulated in the last row of the table. We start by using four 74x157s to make a 2-input, 16-bit multiplexer. Then, we can hook up a first set
Multiplexer Component Data Loading Data Delay Control Loading Total ICs
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DOUT[15] DIN[14:7] DOUT[14] DIN[6:0,15] DIN[13:6] DOUT[13] DIN[5:0,15:14] DIN[1:0,15:10] DIN[9:2]
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DOUT[1]
DIN[0,15:9] DIN[8:1]
DOUT[0]
DIN[15:0]
S3_L
DOUT[15:0]
Figure 6-1 One approach to building a 16-bit barrel shifter.
S[3:0]
S3
S[2-0]
74x151 74x251 74x153 74x157
16 16 4 2
2 1 2 4
32 32 8 4
36 32 16 16
Ta b l e 6 - 1 Properties of four different barrel-shifter design approaches.
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X[15:12] X[13:10] Y[15:12] Y[11:8] Z[15:12] Z[7:4]
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74x157 X[15:12] 74x157 Y[15:12] 74x157 Z[15:12] 74x157 DOUT[15:12] DIN[11:8] DIN[10:7] X[11:8] X[9:6] Y[11:8] Y[7:4] Z[11:8] Z[3:0] 74x157 X[11:8] 74x157 Y[11:8] 74x157 Z[11:8] 74x157 DOUT[11:8] DIN[7:4] DIN[6:3] X[7:4] X[5:2] Y[7:4] Y[3:0] Z[7:4] 74x157 X[7:4] 74x157 Y[7:4] 74x157 Z[7:4] Z[15:12] 74x157 DOUT[7:4] DIN[3:0] X[3:0] Y[3:0] Z[3:0] DIN[2:0,15] 74x157 X[3:0] X[1:0,15:14] 74x157 Y[3:0] Y[15:12] 74x157 Z[3:0] Z[11:8] 74x157 DOUT[3:0]
DIN[15:0] S[3:0]
S0
S1
S2
S3
DOUT[15:0]
Figure 6-2 A second approach to building a 16-bit barrel shifter.
of four 157s controlled by S0 to shift the input word left by 0 or 1 bit. The data outputs of this set are connected to the inputs of a second set, controlled by S1, which shifts its input word left by 0 or 2 bits. Continuing the cascade, a third and fourth set are controlled by S2 and S3 to shift selectively by 4 and 8 bits, as shown in Figure 6-2. Here, the 1A-4A and 1B-4B inputs and the 1Y-4Y outputs of each 157 are connected to the indicated signals in the listed order from left to right. The 157-based approach requires only half as many MSI packages and has far less loading on the control and data inputs. On the other hand, it has the longest data-path delay, since each data bit must pass through four 74x157s. Halfway between the two approaches, we can use eight 74x153 4-input, 2-bit multiplexers two build a 4-input, 16-bit multiplexer. Cascading two sets of these, we can use S[3:2] to shift selectively by 0, 4, 8, or 12 bits, and S[1:0] to shift by 03 bits. This approach has the performance characteristics shown in the third row of Table 6-1, and would appear to be the best compromise if you dont need to have the absolutely shortest possible data delay. The same kind of considerations would apply if you were building the barrel shifter out of ASIC cells instead of MSI parts, except youd be counting chip area instead of MSI/SSI packages. Typical ASIC cell libraries have 1-bit-wide multiplexers, usually realized with CMOS transmission gates, with 2 to 8 inputs. To build a larger multiplexer, you have to put together the appropriate combination of smaller cells. Besides the kind of choices we encountered in the MSI example, you have the further complication that CMOS delays are highly dependent on loading. Thus, depending on the approach, you must decide where to add buffers to the control lines, the data lines, or both to minimize loading-related delays. An approach that looks good on paper, before analyzing these delays and adding buffers, may actually turn out to have poorer delay or more chip area than another approach.
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6.1.2 Simple Floating-Point Encoder The previous example used multiple copies of a single building block, a multiplexer, and it was pretty obvious from the problem statement that a multiplexer was the appropriate building block. The next example shows that you sometimes have to look a little harder to see the solution in terms of known building blocks. Now lets look at a design problem whose MSI solution is not quite so obvious, a fixed-point to floating-point encoder. An unsigned binary integer B in the range 0 B < 211 can be represented by 11 bits in fixed-point format, B = b10b9b1b0. We can represent numbers in the same range with less precision using only 7 bits in a floating-point notation, F = M 2E, where M is a 4-bit mantissa m3m2m1m0 and E is a 3-bit exponent e2e1e0. The smallest integer in this format is 0 20 and the largest is (241) 27. Given an 11-bit fixed-point integer B, we can convert it to our 7-bit floating-point notation by picking off four high-order bits beginning with the most significant 1, for example, 11010110100 = 1101 27 + 0110100 00100101111 = 1001 25 + 01111 00000111110 = 1111 22 + 10 00000001011 = 1011 20 + 0 00000000010 = 0010 20 + 0
The last term in each equation is a truncation error that results from the loss of precision in the conversion. Corresponding to this conversion operation, we can write the specification for a fixed-point to floating-point encoder circuit:
A combinational circuit is to convert an 11-bit unsigned binary integer B into a 7-bit floating-point number M,E, where M and E have 4 and 3 bits, respectively. The numbers have the relationship B = M 2E + T, where T is the truncation error, 0 T < 2E. Starting with a problem statement like the one above, it takes some creativity to come up with an efficient circuit designthe specification gives no clue. However, we can get some ideas by looking at how we converted numbers by hand earlier. We basically scanned each input number from left to right to find the first position containing a 1, stopping at the b3 position if no 1 was found. We picked off four bits starting at that position to use as the mantissa, and the starting position number determined the exponent. These operations are beginning to sound like MSI building blocks. Scanning for the first 1 is what a generic priority encoder does. The output of the priority encoder is a number that tells us the position of the first 1. The position number determines the exponent; first-1 positions of b10 b3 imply exponents of 70, and positions of b2 b0 or no-1-found imply an exponent of 0. Therefore, we can scan for the first 1 with an 8-input priority encoder with inputs
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E2_L E1_L E0_L M3_L
Figure 6-3 A combinational fixed-point to floatingpoint encoder.
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M0_L
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I7 (highest priority) through I0 connected to b10 b3. We can use the priority encoders A2 A0 outputs directly as the exponent, as long as the no-1-found case produces A2 A0 = 000. Picking off four bits sounds like a selecting or multiplexing operation. The 3-bit exponent determines which four bits of B we pick off, so we can use the exponent bits to control an 8-input, 4-bit multiplexer that selects the appropriate four bits of B to form M. An MSI circuit that results from these ideas is shown in Figure 6-3. It contains several optimizations: Since the available MSI priority encoder, the 74x148, has active-low inputs, the input number B is assumed to be available on an active-low bus B_L[10:0]. If only an active-high version of B is available, then eight inverters can be used to obtain the active-low version. If you think about the conversion operation a while, youll realize that the most significant bit of the mantissa, m3, is always 1, except in the no-1found case. The 148 has a GS_L output that indicates this case, allowing us to eliminate the multiplexer for m3. The 148 has active-low outputs, so the exponent bits (E0_LE2_L) are produced in active-low form. Naturally, three inverters could be used to produce an active-high version. Since everything else is active-low, active-low mantissa bits are used too. Active-high bits are also readily available on the 148 EO_L and the 151 Y_L outputs. Strictly speaking, the multiplexers in Figure 6-3 are drawn incorrectly. The 74x151 symbol can be drawn alternatively as shown in Figure 6-4. In words, if the multiplexers data inputs are active low, then the data outputs have an active level opposite that shown in the original symbol. The active-low-data symbol
74x151
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EN
A B 9 C 4 D0 3 D1 2 D2 1 D3 15 D4 14 D5 13 D6 12 D7
10
11
Figure 6-4 Alternate logic symbol for the 74x151 8-input multiplexer.
Y Y
5 6
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should be preferred in Figure 6-3, since the active levels of the 151 inputs and outputs would then match their signal names. However, in data transfer and storage applications, designers (and the book) dont always go by the book. It is usually clear from the context that a multiplexer (or a multibit register, in Section 8.2.5) does not alter the active level of its data. 6.1.3 Dual-Priority Encoder Quite often MSI building blocks need a little help from their friendsordinary gates to get the job done. In this example, wed like to build a priority encoder that identifies not only the highest but also the second-highest priority asserted signal among a set of eight request inputs. Well assume for this example that the request inputs are active low and are named R0_LR7_L, where R0_L has the highest priority. Well use A2A0 and AVALID to identify the highest-priority request, where AVALID is asserted only if at least one request input is asserted. Well use B2B0 and BVALID to identify the second-highest-priority request, where BVALID is asserted only if at least two request inputs are asserted. Finding the highest-priority request is easy enough, we can just use a 74x148. To find the second highest-priority request, we can use another 148, but only if we first knock out the highest-priority request before applying the request inputs. This can be done using a decoder to select a signal to knock out, based on A2A0 and AVALID from the first 148. These ideas are combined in the solution shown in Figure 6-6. A 74x138 decoder asserts at most one of its eight outputs, corresponding to the highest-priority request input. The outputs are fed to a rank of NAND gates to turn off the highest-priority request. A trick is used in this solution is to get active-high outputs from the 148s, as shown in Figure 6-5. We can rename the address outputs A2_LA0_L to be active high if we also change the name of the request input that is associated with each output combination. In particular, we complement the bits of the request number. In the redrawn symbol, request input I0 has the highest priority.
Figure 6-5 Alternate logic symbols for the 74x148 8-input priority encoder.
5 4 3 2 1 5
EI I7
4 3 2 1
DI I0
13 12 11 10
I6 I5 I4 I3 I2 I1 I0
A2 A1 A0
6 7 9
13 12 11 10
GS
14 15
EO
A2 I1 I2 A1 I3 A0 I4 I5 IDLE I6 AVALID I7
6 7 9
14 15
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R0_L R1_L R2_L R3_L
R4_L 13 R5_L 12 R6_L 11 R7_L 10
R0_L
R1_L
R2_L
R3_L
R4_L 11
R5_L 13
R6_L
R7_L
Figure 6-6 First-and second-highest priority encoder circuit.
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5 4 3 2 1
EI I7
I6
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11 RD7_L
U5
U7
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PEQQ = EQ2 EQ1 EQ0 PGTQ = GT2 + EQ2 GT1 + EQ2 EQ1 GT0 Copyright 1999 by John F. Wakerly
6.1.4 Cascading Comparators In Section 5.9.4, we showed how 74x85 4-bit comparators can be cascaded to create larger comparators. Since the 74x85 uses a serial cascading scheme, it can be used to build arbitrarily large comparators. The 74x682 8-bit comparator, on the other hand, doesnt have any cascading inputs and outputs at all. Thus, at first glance, you might think that it cant be used to build larger comparators. But thats not true. If you think about the nature of a large comparison, it is clear that two wide inputs, say 32 bits (four bytes) each, are equal only if their corresponding bytes are equal. If were trying to do a greater-than or less-than comparison, then the corresponding most-significant that are not equal determine the result of the comparison. Using these ideas, Figure 6-7 uses three 74x682 8-bit comparators to do equality and greater-than comparison on two 24-bit operands. The 24-bit results are derived from the individual 8-bit results using combinational logic for the following equations:
This parallel expansion approach is actually faster than the 74x85s serial cascading scheme, because it does not suffer the delay of propagating the cascading signals through a cascade of comparators. The parallel approach can be used to build very wide comparators using two-level AND-OR logic to combine the 8-bit results, limited only by the fan-in constraints of the AND-OR logic. Arbitrary large comparators can be made if you use additional levels of logic to do the combining. 6.1.5 Mode-Dependent Comparator Quite often, the requirements for a digital-circuit application are specified in a way that makes an MSI or other building-block solution obvious. For example, consider the following problem: Design a combinational circuit whose inputs are two 8-bit unsigned binary integers, X and Y, and a control signal MIN/MAX. The output of the circuit is an 8-bit unsigned binary integer Z such that Z = min(X,Y) if MIN/MAX = 1, and Z = max(X,Y) if MIN/MAX = 0.
This circuit is fairly easy to visualize in terms of MSI functions. Clearly, we can use a comparator to determine whether X > Y. We can use the comparators output to control multiplexers that produce min(X,Y) and max(X,Y), and we can use another multiplexer to select one of these results depending on MIN/MAX. Figure 6-8(a) is the block diagram of a circuit corresponding to this approach. Our first solution approach works, but its more expensive than it needs to be. Although it has three two-input multiplexers, there are only two input words,
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X and Y, that may ultimately be selected and produced at the output of the circuit. Therefore, we should be able to use just a single two-input mux, and use some other logic to figure out which input to tell it to select. This approach is shown in Figure 6-8(b) and (c). The other logic is very simple indeed, just a single XOR gate.
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Figure 6-7 24-bit comparator circuit.
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Figure 6-8 Mode-dependent comparator circuit: (a) block diagram of a first-cut solution; (b) block diagram of a more cost-effective solution; (c) logic diagram for the second solution.
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6.2 Design Examples Using ABEL and PLDs
6.2.1 Barrel Shifter A barrel shifter, defined on page 464, is good example of something not to design using PLDs. However, we can put ABEL to good use to describe a barrel shifters function, and well also see why a typical barrel shifter is not a good fit for a PLD. Table 6-2 shows the equations for a 16-bit barrel shifter with the same functionality as the example on page 464it does left circular shifts only, using a 4-bit control input S[3..0] to specify the amount of shift. ABEL makes it easy to specify the functionality of the overall circuit without worrying about how the circuit might be partitioned into multiple chips. Also, ABEL dutifully generates a minimal sum-of-products expression for each output bit. In this case, each output requires 16 product terms. Partitioning the 16-bit barrel shifter into multiple PLDs is a difficult task in two different ways. First, it should be obvious that the nature of the function is such that every output bit depends on every input bit. A PLD that produces, say, the DOUT0 output must have all 16 DIN inputs and all four S inputs available to it. So, a GAL16V8 definitely cannot be used; it has only 16 inputs. The GAL20V8 is similar to the GAL16V8, with the addition of four inputonly pins. If we use all 20 available inputs, we are left with two output-only pins (corresponding to the top and bottom outputs in Figure 5-27 on page 341). Thus, it seems possible that we could realize the barrel shifter using eight 20V8 chips, producing two output bits per chip. No, we still have a problem. The second dimension of difficulty in a PLDbased barrel shifter is the number of product terms per output. The barrel shifter requires 16, and the 20V8 provides only 7. Were stuckany realization of the barrel shifter in 20V8s is going to require multiple-pass logic. At this point, we would be best advised to look at partitioning options along the lines that we did in Section 6.1.1.
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DONT BE A BLOCKHEAD The wastefulness of our original design approach in Figure 6-8(a) may have been obvious to you from the beginning, but it demonstrates an important approach to designing with building blocks:
Use standard building blocks to handle data, and look for ways that a single
block can perform different functions at different times or in different modes. Design control circuits to select the appropriate functions as needed, to reduce the total parts count of the design. As Figure 6-8(c) dramatically shows, this approach can save a lot of chips. When designing with IC chips, you should not heed the slogan, Have all you want, well make more!
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Ta b l e 6 - 2 ABEL program for a 16-bit barrel shifter.
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module barrel16 title '16-bit Barrel Shifter' " Inputs and Outputs DIN15..DIN0, S3..S0 DOUT15..DOUT0 S = [S3..S0]; equations pin; pin istype 'com'; [DOUT15..DOUT0] = (S==0) & [DIN15..DIN0] # (S==1) & [DIN14..DIN0,DIN15] # (S==2) & [DIN13..DIN0,DIN15..DIN14] # (S==3) & [DIN12..DIN0,DIN15..DIN13] ... # (S==12) & [DIN3..DIN0,DIN15..DIN4] # (S==13) & [DIN2..DIN0,DIN15..DIN3] # (S==14) & [DIN1..DIN0,DIN15..DIN2] # (S==15) & [DIN0,DIN15..DIN1]; end barrel16
The 16-bit barrel shifter can be realized without much difficulty in a larger programmable device, that is, in a CPLD or an FPGA with enough I/O pins. However, imagine that we were trying to design a 32-bit or 64-bit barrel shifter. Clearly, we would need to use a device with even more I/O pins, but thats not all. The number of product terms and the large amount of connectivity (all the inputs connect to all the outputs) would still be challenging. Indeed, a typical CPLD or FPGA fitter could have difficulty realizing a large barrel shifter with small delay or even at all. There is a critical resource that we took for granted in the partitioned, building-block barrel-shifter designs of Section 6.1.1wires! An FPGA is somewhat limited in its internal connectivity, and a CPLD is even more so. Thus, even with modern FPGA and CPLD design tools, you may still have to use your head to partition the design in a way that helps the tools do their job. Barrel shifters can be even more complex than what weve shown so far. Just for fun, Table 6-3 shows the design for a barrel shifter that supports six different kinds of shifting. This requires even more product terms, up to 40 per output! Although youd never build this device in a PLD, CPLD, or small FPGA, the minimized ABEL equations are useful because they can help you understand the effects of some of your design choices. For example, by changing the coding of SLA and SRA to [1,.X.,0] and [1,.X.,1], you can reduce the total number of product terms in the design from 624 to 608. You can save more product terms by changing the coding of the shift amount for some shifts Exercise (see 6.3). The savings from these changes may carry over to other design approaches.
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module barrl16f Title 'Multi-mode 16-bit Barrel Shifter' " Inputs and Outputs DIN15..DIN0, S3..S0, C2..C0 DOUT15..DOUT0
S = [S3..S0]; C = [C2..C0]; " Shift amount and mode L = DIN15; R = DIN0; " MSB and LSB ROL ROR SLL SRL SLA SRA = = = = = = (C (C (C (C (C (C == == == == == == [0,0,0]); [0,0,1]); [0,1,0]); [0,1,1]); [1,0,0]); [1,0,1]); " " " " " "
equations
[DOUT15..DOUT0] = ROL # ROL # ROL ... # ROL # ROR # ROR ... # ROR # ROR # SLL # SLL ... # SLL # SLL # SRL # SRL ... # SRL # SRL # SLA # SLA ... # SLA # SLA # SRA # SRA ... # SRA # SRA end barrl16f
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Ta b l e 6 - 3 ABEL program for a multi-mode 16-bit barrel shifter.
pin; pin istype 'com'; Rotate (circular shift) left Rotate (circular shift) right Shift logical left (shift in 0s) Shift logical right (shift in 0s) Shift left arithmetic (replicate LSB) Shift right arithmetic (replicate MSB) & (S==0) & [DIN15..DIN0] & (S==1) & [DIN14..DIN0,DIN15] & (S==2) & [DIN13..DIN0,DIN15..DIN14] & (S==15) & [DIN0,DIN15..DIN1] & (S==0) & [DIN15..DIN0] & (S==1) & [DIN0,DIN15..DIN1] & & & & & & & & & & & & & & & & (S==14) & [DIN13..DIN0,DIN15..DIN14] (S==15) & [DIN14..DIN0,DIN15] (S==0) & [DIN15..DIN0] (S==1) & [DIN14..DIN0,0] (S==14) & [DIN1..DIN0,0,0,0,0,0,0,0,0,0,0,0,0,0,0] (S==15) & [DIN0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0] (S==0) & [DIN15..DIN0] (S==1) & [0,DIN15..DIN1] (S==14) & [0,0,0,0,0,0,0,0,0,0,0,0,0,0,DIN15..DIN14] (S==15) & [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,DIN15] (S==0) & [DIN15..DIN0] (S==1) & [DIN14..DIN0,R] (S==14) & [DIN1..DIN0,R,R,R,R,R,R,R,R,R,R,R,R,R,R] (S==15) & [DIN0,R,R,R,R,R,R,R,R,R,R,R,R,R,R,R] (S==0) & [DIN15..DIN0] (S==1) & [L,DIN15..DIN1] & (S==14) & [L,L,L,L,L,L,L,L,L,L,L,L,L,L,DIN15..DIN14] & (S==15) & [L,L,L,L,L,L,L,L,L,L,L,L,L,L,L,DIN15];
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Ta b l e 6 - 4 An ABEL program for the fixed-point to floating-point PLD.
" B E M Constant expressions = [B10..B0]; = [E2..E0]; = [M3..M0]; equations WHEN ELSE ELSE ELSE ELSE ELSE ELSE ELSE M= # # # # # # # B < 16 WHEN B WHEN B WHEN B WHEN B WHEN B WHEN B E = 7; THEN E = 0; < 32 THEN E = 1; < 64 THEN E = 2; < 128 THEN E = 3; < 256 THEN E = 4; < 512 THEN E = 5; < 1024 THEN E = 6; (E==0) (E==1) (E==2) (E==3) (E==4) (E==5) (E==6) (E==7) & & & & & & & & [B3..B0] [B4..B1] [B5..B2] [B6..B3] [B7..B4] [B8..B5] [B9..B6] [B10..B7]; end fpenc
6.2.2 Simple Floating-Point Encoder We defined a simple floating-point number format on page 467, and posed the design problem of converting a number from fixed-point to this floating point format. The I/O-pin requirements of this design are limited11 inputs and 7 outputsso we can potentially use a single PLD to replace the four parts that were used in the MSI solution. An ABEL program for the fixed-to-floating-point converter is given in Table 6-4. The WHEN statement expresses the operation of determining the exponent value E in a very natural way. Then E is used to select the appropriate bits of B to use as the mantissa M. Despite the deep nesting of the WHEN statement, only four product terms are needed in the minimal sum for each bit of E. The equations for the M bits are not too bad either, requiring only eight product terms each. Unfortunately, the
module fpenc title 'Fixed-point to Floating-point Encoder' FPENC device 'P20L8'; " Input and output pins B10..B0 pin 1..11; E2..E0, M3..M0 pin 21..15 istype 'com';
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GAL20V8 has available only seven product terms per output. However, the GAL22V10 (Figure 8-22 on page 684) has more product terms available, so we can use that if we like. One drawback of the design in Table 6-4 is that the [M3..M0] outputs are slow; since they use [E2..E0], they take two passes through the PLD. A faster approach, if it fits, would be to rewrite the select terms (E==0, etc.) as intermediate equations before the equations section, and let ABEL expand the resulting M equations in a single level of logic. Unfortunately, ABEL does not allow WHEN statements outside of the equations section, so well have to roll up our sleeves and write our own logic expressions in the intermediate equations. Table 6-5 shows the modified approach. The expressions for S7S0 are just mutually-exclusive AND -terms that indicate exponent values of 70 depending on the location of the most significant 1 bit in the fixed-point input number. The exponent [E2..E0] is a binary encoding of the select terms, and the mantissa bits [M3..M0] are generated using a select term for each case. It turns out that these M equations still require 8 product terms per output bit, but at least theyre a lot faster since they use just one level of logic.
module fpence title 'Fixed-point to Floating-point Encoder' FPENCE device 'P20L8'; " Input and output pins B10..B0 E2..E0, M3..M0
" Intermediate equations S7 = B10; S6 = !B10 & B9; S5 = !B10 & !B9 & B8; S4 = !B10 & !B9 & !B8 & B7; S3 = !B10 & !B9 & !B8 & !B7 S2 = !B10 & !B9 & !B8 & !B7 S1 = !B10 & !B9 & !B8 & !B7 S0 = !B10 & !B9 & !B8 & !B7 equations
E2 = S7 # S6 # S5 # S4; E1 = S7 # S6 # S3 # S2; E0 = S7 # S5 # S3 # S1;
[M3..M0] = S0 & [B3..B0] # S1 & [B4..B1] # S2 & [B5..B2] # S3 & [B6..B3] # S4 & [B7..B4] # S5 & [B8..B5] # S6 & [B9..B6] # S7 & [B10..B7]; end fpenc
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Ta b l e 6 - 5 Alternative ABEL program for the fixed-point to floating-point PLD.
pin 1..11; pin 21..15 istype 'com'; & & & & B6; !B6 & B5; !B6 & !B5 & B4; !B6 & !B5 & !B4;
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Ta b l e 6 - 6 ABEL program for a dual priority encoder.
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title 'Dual Priority Encoder' PRIORTWO device 'P16V8'; " Input and output pins R7..R0 AVALID, A2..A0, BVALID, B2..B0 " Set definitions A = [A2..A0]; B = [B2..B0]; equations WHEN ELSE ELSE ELSE ELSE ELSE ELSE ELSE pin 1..8; pin 19..12 istype 'com'; R0==1 THEN WHEN R1==1 WHEN R2==1 WHEN R3==1 WHEN R4==1 WHEN R5==1 WHEN R6==1 WHEN R7==1 A=0; THEN THEN THEN THEN THEN THEN THEN A=1; A=2; A=3; A=4; A=5; A=6; A=7; AVALID = ([R7..R0] != 0); WHEN ELSE ELSE ELSE ELSE ELSE ELSE ELSE (R0==1) & (A!=0) THEN WHEN (R1==1) & (A!=1) WHEN (R2==1) & (A!=2) WHEN (R3==1) & (A!=3) WHEN (R4==1) & (A!=4) WHEN (R5==1) & (A!=5) WHEN (R6==1) & (A!=6) WHEN (R7==1) & (A!=7) (R0==1) (R2==1) (R4==1) (R6==1) & & & & (A!=0) (A!=2) (A!=4) (A!=6) B=0; THEN THEN THEN THEN THEN THEN THEN B=1; B=2; B=3; B=4; B=5; B=6; B=7; BVALID = # # # # # # # (R1==1) (R3==1) (R5==1) (R7==1) & & & & (A!=1) (A!=3) (A!=5) (A!=7); end priortwo
6.2.3 Dual-Priority Encoder In this example, well design a PLD-based priority encoder that identifies both the highest-priority and the second-highest-priority asserted signal among a set of eight active-high request inputs named [R0..R7], where R0 has the highest priority. Well use [A2..A0] and AVALID to identify the highest-priority request, asserting AVALID only if a highest-priority request is present. Similarly, well use [B2:B0] and BVALID to identify the second-highest-priority request. Table 6-6 shows an ABEL program for the priority encoder. As usual, a nested WHEN statement is perfect for expressing priority behavior. To find the
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P-Terms --------8/1 4/5 4/5 4/5 24/8 24/17 20/21 18/22 ========= 106/84
second-highest priority input, we exclude an input if its input number matches the highest-priority input number, which is A. Thus, were using two-pass logic to compute the B outputs. The equation for AVALID is easy; AVALID is 1 if the request inputs are not all 0. To compute BVALID, we OR all of the conditions that set B in the WHEN statement. Even with two-pass logic, the B outputs use too many product terms to fit in a 16V8; Table 6-7 shows the product-term usage. The B outputs use too many terms even for a 22V10, which has 16 terms for two of its output pins, and 814 for the others. Sometimes you just have to work harder to make things fit! So, how can we save some product terms? One important thing to notice is that R0 can never be the second-highest priority asserted input, and therefore B can never be valid and 0. Thus, we can eliminate the WHEN clause for the R0==1 case. Making this change reduces the minimum number of terms for B2B0 to 14, 17, and 15, respectively. We can almost fit the design in a 22V10, if we can just know one term out of the B1 equation. Well lets try something else. The second WHEN clause, for the R0==2 case, also fails to make use of everything we know. We dont need the full generality
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Fan-in -----8 8 8 8 11 11 11 11 Fan-out ------1 1 1 1 1 1 1 1 Type ---Pin Pin Pin Pin Pin Pin Pin Pin Name ---------AVALID A2 A1 A0 BVALID B2 B1 B0
Ta b l e 6 - 7 Product-term usage in the dual priority encoder PLD.
Best P-Term Total: 76 Total Pins: 16 Average P-Term/Output: 9
SUMS OF PRODUCTS AND PRODUCTS OF SUMS (SAY THAT 5 TIMES FAST)
You may recall from Section 4.3.6 that the minimal sum-of-products expression for the complement of a function can be manipulated through DeMorgans theorem to obtain a minimal product-of-sums expression for the original function. You may also recall that the number of product terms in the minimal sum of products may differ from the number of sum terms in the minimal product of sums. The P-terms column in Table 6-7 lists the number of terms in both minimal forms (product/sum terms). If either minimal form has less than or equal to the number of product terms available in a 22V10s AND-OR array, then the function can be made to fit.
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WHEN (R1==1) & (R0==1) THEN B=1;
of A!=0; this case is only important when R0 is 1. So, let us replace the first two lines of the original WHEN statement with This subtle change reduces the minimum number of terms for B2B0 to 12, 16, and 13, respectively. We made it! Can the number of product terms be reduced further, enough to fit into a 16V8 while maintaining the same functionality? Its not likely, but well leave that as an exercise (6.4) for the reader!
6.2.4 Cascading Comparators We showed in Section 5.9.5 that equality comparisons are easy to realize in PLDs, but that magnitude comparisons (greater-than or less-than) of more than a few bits are not good candidates for PLD realization due to the large number of product terms required. Thus, comparators are best realized using discrete MSI comparator components or as specialized cells within an FPGA or ASIC library. However, PLDs are quite suitable for realizing the combinational logic used in parallel expansion schemes that construct wider comparators from smaller ones, as well show here. In Section 5.9.4, we showed how to connect 74x85 4-bit comparators in series to create larger comparators. Although a serial cascading scheme requires no extra logic to build arbitrarily large comparators, it has the major drawback that the delay increases linearly with the length of the cascade. In Section 6.1.4, on the other hand, we showed how multiple copies of the 74x682 8-bit comparator could be used in parallel along with combinational logic to perform a 24-bit comparison. This scheme can be generalized for comparisons of arbitrary width. Table 6-8 is an ABEL program that uses a GAL22V10 to perform a 64-bit comparison using eight 74x682s to combine the equal (EQ) and greater-than (GT) outputs from the individual byte to produce all six possible relations of the two 64-bit input values (=, , >, , <, ). In this program, the PEQQ and PNEQ outputs can be realized with one product term each. The remaining eight outputs use eight product terms each. As weve mentioned previously, the 22V10 provides 8-16 product terms per output, so the design fits.
HAVE IT YOUR WAY
Early PLDs such as the PAL16L8s did not have output-polarity control. Designers who used these devices were forced to choose a particular polarity, active high or active low, for some outputs in order to obtain reduced equations that would fit. When a 16V8, 20V8, 22V10, or any of a plethora of modern CPLDs is used, no such restriction exists. If an equation or its complement can be reduced to the number of product terms available, then the corresponding output can be made active high or active low by programming the output-polarity fuse appropriately.
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module compexp title 'Expansion logic for 64-bit comparator' COMPEXP device 'P22V10';
" Inputs from the individual comparators, active-low, 7 = MSByte EQ_L7..EQ_L0, GT_L7..GT_L0 pin 1..11, 13..14, 21..23; " Comparison outputs PEQQ, PNEQ, PGTQ, PGEQ, PLTQ, PLEQ " Active-level conversions EQ7 = !EQ_L7; EQ6 = !EQ_L6; EQ3 = !EQ_L3; EQ2 = !EQ_L2; GT7 = !GT_L7; GT6 = !GT_L6; GT3 = !GT_L3; GT2 = !GT_L2; " Less-than LT7 = !(EQ7 LT4 = !(EQ4 LT1 = !(EQ1 equations pin 15..20 istype 'com';
PEQQ = EQ7 & EQ6 & EQ5 & EQ4 & EQ3 & EQ2 & EQ1 & EQ0;
PNEQ = !(EQ7 & EQ6 & EQ5 & EQ4 & EQ3 & EQ2 & EQ1 & EQ0); PGTQ = # # # # GT7 EQ7 EQ7 EQ7 EQ7 # EQ7 EQ6 & EQ6 & EQ6 & EQ6 & # & GT6 EQ5 & EQ5 & EQ5 & EQ5 & # GT4 EQ4 EQ4 EQ4
PLEQ = !(GT7 # EQ7 # EQ7 # EQ7 # EQ7 PLTQ = # # # # LT7 EQ7 EQ7 EQ7 EQ7
PGEQ = !(LT7 # EQ7 # EQ7 # EQ7 # EQ7 end compexp
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Ta b l e 6 - 8 ABEL program for combining eight 74x682s into a 64-bit comparator.
EQ5 EQ1 GT5 GT1 = = = = !EQ_L5; !EQ_L1; !GT_L5; !GT_L1; EQ4 EQ0 GT4 GT0 = = = = !EQ_L4; !EQ_L0; !GT_L4; !GT_L0; terms # GT7); LT6 = !(EQ6 # GT6); LT5 = !(EQ5 # GT5); # GT4); LT3 = !(EQ3 # GT3); LT2 = !(EQ2 # GT2); # GT1); LT0 = !(EQ0 # GT0); & & & & EQ7 & EQ6 & GT5 # EQ7 & EQ6 & EQ5 & EQ4 & GT3 & EQ3 & GT2 & EQ3 & EQ2 & GT1 & EQ3 & EQ2 & EQ1 & GT0; & & & & EQ7 EQ6 & EQ6 & EQ6 & EQ6 & & GT6 EQ5 & EQ5 & EQ5 & EQ5 & # GT4 EQ4 EQ4 EQ4 EQ7 & EQ6 & GT5 # EQ7 & EQ6 & EQ5 & EQ4 & GT3 & EQ3 & GT2 & EQ3 & EQ2 & GT1 & EQ3 & EQ2 & EQ1 & GT0); # & & & & EQ7 EQ6 & EQ6 & EQ6 & EQ6 & # & LT6 EQ5 & EQ5 & EQ5 & EQ5 & # LT4 EQ4 EQ4 EQ4 EQ7 & EQ6 & LT5 # EQ7 & EQ6 & EQ5 & EQ4 & LT3 & EQ3 & LT2 & EQ3 & EQ2 & LT1 & EQ3 & EQ2 & EQ1 & LT0; & & & & EQ7 EQ6 & EQ6 & EQ6 & EQ6 & & LT6 EQ5 & EQ5 & EQ5 & EQ5 & # LT4 EQ4 EQ4 EQ4 EQ7 & EQ6 & LT5 # EQ7 & EQ6 & EQ5 & EQ4 & LT3 & EQ3 & LT2 & EQ3 & EQ2 & LT1 & EQ3 & EQ2 & EQ1 & LT0);
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Ta b l e 6 - 9 Mode-control bits for the mode-dependent comparator.
M1 M0 Comparison
0 0 1 1
0 1 0
32-bit 31-bit 30-bit
1
not used
6.2.5 Mode-Dependent Comparator For the next example, let us suppose we have a system in which we need to compare two 32-bit words under normal circumstances, but where we must sometimes ignore one or two low-order bits of the input words. The operating mode is specified by two mode-control bits, M1 and M0, as shown in Table 6-9. As weve noted previously, comparing, adding, and other iterative operations are usually poor candidates for PLD-based design, because an equivalent two-level sum-of-products expression has far too many product terms. In Section 5.9.5, we calculated how many product terms are needed for an n-bit comparator. Based on these results, we certainly wouldnt be able to build the 32-bit mode-dependent comparator or even an 8-bit slice of it with a PLD; the 74x682 8-bit comparator is just about the most efficient possible single chip we can use to perform an 8-bit comparison. However, a PLD-based design is quite reasonable for handling the mode-control logic and the part of the comparison that is dependent on mode (the two low-order bits). Figure 6-9 shows a complete circuit design resulting from this idea, and Table 6-11 is the ABEL program for a 16V8 MODECOMP PLD that handles the random logic. Four 682s are used to compare most of the bits, and the 16V8 combines the 682 outputs and handles the two low-order bits as a function of the mode. Intermediate expressions EQ30 and GT30 are defined to save typing in the equations section of the program. As shown in Table 6-10, the XEQY and XGTY outputs use 7 and 11 product terms, respectively. Thus, XGTY does not fit into the 7 product terms available on a 16V8 output. However, this is another example where we have some flexibility in our coding choices. By changing the coding of MODE30 to [1,.X.], we can reduce the product-term requirements for XGTY to 7/12, and thereby fit the design into a 16V8.
Ta b l e 6 - 1 0 Product-term usage for the MODECOMP PLD.
P-Terms --------7/9 11/13 ========= 18/22 Fan-in -----10 14 Fan-out ------1 1 Type ---Pin Pin Name -------XEQY XGTY
Best P-Term Total: 18 Total Pins: 16 Average P-Term/Output: 9
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Figure 6-9 A 32-bit mode-dependent comparator.
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74x682 74x682
2 3 4 5 6 7 8 9
P0
X16 Y16
2 3 4 5 6 7 8 9
X2 Y2
Q0 P1 Q1 P2 Q2 P3 Q3 P4 Q4 P5
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P EQ Q
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P0 Q0 P1 Q1 P2 Q2 P3 Q3 P4 Q4 P5 Q5
P EQ Q
19 EQ2_L
X0
X1 Y0 Y1
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11 12 13 14 15
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1 GT0_L
P GT Q
1 GT2_L
X6 Y6 X7 Y7
Q5 P6 16 Q6
17
X22 Y22 X23 Y23
PAL16V8
P7 18 Q7
U1
P6 16 Q6 17 P7 18 Q7
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Ta b l e 6 - 1 1 ABEL program for combining eight 74x682s into a 64-bit comparator.
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module modecomp title 'Control PLD for Mode-Dependent Comparator' MODECOMP device 'P16V8'; " Input and output pins M0, M1, EQ2_L, GT2_L, EQ0_L, GT0_L EQ1_L, GT1_L, EQ3_L, GT3_L, X0, X1, Y0, Y1 XEQY, XGTY " Active-level conversions EQ3 = !EQ3_L; EQ2 = !EQ2_L; EQ1 = !EQ1_L; EQ0 = !EQ0_L; GT3 = !GT3_L; GT2 = !GT2_L; GT1 = !GT1_L; GT0 = !GT0_L; " Mode MODE32 MODE31 MODE30 MODEXX definitions = ([M1,M0] == = ([M1,M0] == = ([M1,M0] == = ([M1,M0] == [0,0]); [0,1]); [1,0]); [1,1]); " " " " 32-bit comparison 31-bit comparison 30-bit comparison Unused equations WHEN MODE32 THEN { XEQY = EQ30 & (X1==Y1) & (X0==Y0); XGTY = GT30 # (EQ30 & (X1>Y1)) # (EQ30 & (X1==Y1) & (X0>Y0)); } ELSE WHEN MODE31 THEN { XEQY = EQ30 & (X1==Y1); XGTY = GT30 # (EQ30 & (X1>Y1)); } ELSE WHEN MODE30 THEN { XEQY = EQ30; XGTY = GT30; } end modecomp
pin 1..6; pin 7..9, 10, 15..18; pin 19, 12 istype 'com';
" Expressions for 30-bit equal and greater-than EQ30 = EQ3 & EQ2 & EQ1 & EQ0; GT30 = GT3 # (EQ3 & GT2) # (EQ3 & EQ2 & GT1) # (EQ3 & EQ2 & EQ1 & GT0);
6.2.6 Ones Counter There are several important algorithms that include the step of counting the number of 1 bits in a data word. In fact, some microprocessor instruction sets have been extended recently to include ones counting as a basic instruction. Counting the ones in a data word can be done easily as an iterative process, where you scan the word from one end to the other and increment a counter each time a 1 is encountered. However, this operation must be done more quickly inside the arithmetic and logic unit of a microprocessor. Ideally, we would like
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ones counting to run as fast as any other arithmetic operation, such as adding two words. Therefore, a combinational circuit is required. In this example, let us suppose that we have a requirement to build a 32-bit ones counter as part of a larger system. Based on the number of inputs and outputs required, we obviously cant fit the design into a single 22V10-class PLD, but we might be able to partition the design into a reasonably small number of PLDs. Figure 6-10 shows such a partition. Two copies of a first 22V10, ONESCNT1, are used to count the ones in two 15-bit chunks of the 32-bit input word D[31:0], each producing a 4-bit sum output. A second 22V10, ONESCNT2, is used to add the two four bit sums and the last two input bits. The program for ONESCNT1 is deceptively simple, as shown in Table 6-12. The statement @CARRY 1 is included to limit the carry chain to one stage; as explained in Section 5.10.8, this reduces product-term requirements at the expense of helper outputs and increased delay.
module onescnt1 title 'Count the ones in a 15-bit word' ONESCNT1 device 'P22V10';
" Input and output pins D14..D0 pin 1..11, 13..15, 23; SUM3..SUM0 pin 17..20 istype 'com'; equations
@CARRY 1; [SUM3..SUM0] = D0 + D1 + D2 + D3 + D4 + D5 + D6 + D7 + D8 + D9 + D10 + D11 + D12 + D13 + D14; end onescnt1
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D[14:0]
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D30 D31
D1 D0
Figure 6-10 Possible partitioning for the ones-counting circuit.
U3
Ta b l e 6 - 1 2 ABEL program for counting the 1 bits in a 15-bit word.
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TIC-TAC-TOE, IN CASE YOU DIDNT KNOW Copyright 1999 by John F. Wakerly
Unfortunately, when I compiled this program, my computer just sat there, CPU-bound, for an hour without producing any results. That gave me time to use my brain, a good exercise for those of us who have become too dependent on CAD tools. I then realized that I could write the logic function for the SUM0 output by hand in just a few seconds,
SUM0 = D0 D1 D 2 D3 D4 D5 D6 D7 D13 D14
The Karnaugh map for this function is a checkerboard, and the minimal sum-ofproducts expression has 214 product terms. Obviously this is not going to fit in one or a few passes through a 22V10! So, anyway, I killed the ABEL compiler process, and rebooted Windows just in case the compiler had gone awry. Obviously, a partitioning into smaller chunks is required to design the ones-counting circuit. Although we could pursue this further using ABEL and PLDs, its more interesting to do a structural design using VHDL, as we will in Section 6.3.6. The ABEL and PLD version is left as an exercise (6.6).
6.2.7 Tic-Tac-Toe In this example, well design a combinational circuit that picks a players next move in the game of Tic-Tac-Toe. The first thing well do is decide on a strategy for picking the next move. Let us try to emulate the typical humans strategy, by following the decision steps below: 1. Look for a row, column, or diagonal that has two of my marks (X or O, depending on which player I am) and one empty cell. If one exists, place my mark in the empty cell; I win! 2. Else, look for a row, column, or diagonal that has two of my opponents marks and one empty cell. If one exists, place my mark in the empty cell to block a potential win by my opponent. 3. Else, pick a cell based on experience. For example, if the middle cell is open, its usually a good bet to take it. Otherwise, the corner cells are good bets. Intelligent players can also notice and block a developing pattern by the opponent or look ahead to pick a good move.
The game of Tic-Tac-Toe is played by two players on a 3 3 grid of cells that are initially empty. One player is X and the other is O. The players alternate in placing their mark in an empty cell; X always goes first. The first player to get three of his or her own marks in the same row, column, or diagonal wins. Although the first player to move (X) has a slight advantage, it can be shown that a game between two intelligent players will always end in a draw; neither player will get three in a row before the grid fills up.
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Planning ahead, well call the second player Y to avoid confusion between O and 0 in our programs. The next thing to think about is how we might encode the inputs and outputs of the circuit. There are only nine possible moves that a player can make, so the output can be encoded in just four bits. The circuits input is the current state of the playing grid. There are nine cells, and each cell has one of three possible states (empty, occupied by X, occupied by Y). There are several choices of how to code the state of one cell. Because the game is symmetric, well choose a symmetric encoding that may help us later: 00 Cell is empty. 10 Cell is occupied by X. 01 Cell is occupied by Y.
So, we can encode the 3 3 grids state in 18 bits. As shown in Figure 6-11, well number the grid with row and column numbers, and use ABEL signals Xij and Yij to denote the presence of X or Y in cell i,j. Well look at the output coding later. With a total of 18 inputs and 4 outputs, the Tic-Tac-Toe circuit could conceivably fit in just one 22V10. However, experience suggests that theres just no way. Were going to have to find a partitioning of the function, and partitioning along the lines of the decision steps on the preceding page seems like a good idea. In fact, steps 1 and 2 are very similar; they differ only in reversing the roles of the player and the opponent. Heres where our symmetric encoding can pay
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Figure 6-11 Tic-Tac-Toe grid and ABEL signal names.
COMPACT ENCODING
Since each cell in the Tic-Tac-Toe grid can have only three states, not four, the total number of board configurations is 39, or 19,683. This is less than 215, so the board state can be encoded in only 15 bits. However, such an encoding would lead to much larger circuits for picking a move, unless the move-picking circuit was a read-only memory (see Exercise 11.26).
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TWOINROW
Figure 6-12 Preliminary PLD partitioning for the Tic-Tac-Toe game.
Ta b l e 6 - 1 3 ABEL program to find two in a row in Tic-Tac-Toe.
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9 X11-X33 X11-X33 PICK 4 MOVE[3:0] XMOVE[3:0] 9 Y11-Y33 Y11-Y33 U1 4 TWOINROW MOVE[3:0] MOVE[3:0] X11-X33 4 MOVE[3:0] YMOVE[3:0] Y11-Y33 U2 9 9 X11-X33 Y11-Y33 U3
off. A PLD that finds me two of my marks in a row along with one empty cell for a winning move (step 1) can find two of my opponents marks in a row plus an empty for a blocking move (step 2). All we have to do is swap the encodings for X and Y. With out selected coding, that doesnt require any logic, just physically swapping the Xij and Yij signals for each cell. With this in mind, we can use two copies of the same PLD, TWOINROW, to perform steps 1 and 2 as shown in Figure 6-12. Notice that the X11X33 signals are connected to the top inputs of the first TWOINROW PLD, but to the bottom inputs of the second. The moves from the two TWOINROW PLDs can be examined in another PLD, PICK. This device picks a move from the first two PLDs if either found one; else it performs step 3. It looks like PICK has too many inputs and outputs to fit in a 22V10, but well come back to that later. Table 6-13 is a program for the TWOINROW PLD. It looks at the grids state from the point of view of X, that is, it looks for a move where X can get three in a row. The program makes extensive use of intermediate equations to define
module twoinrow Title 'Find Two Xs and an empty cell in a row, column, or diagonal' TWOINROW device 'P22V10'; " Inputs and Outputs X11, X12, X13, X21, X22, X23, X31, X32, X33 pin 1..9; Y11, Y12, Y13, Y21, Y22, Y23, Y31, Y32, Y33 pin 10,11,13..15,20..23; MOVE3..MOVE0 pin 16..19 istype 'com'; " MOVE MOVE MOVE11 MOVE21 MOVE31 NONE output encodings = [MOVE3..MOVE0]; = [1,0,0,0]; MOVE12 = [0,1,0,0]; MOVE13 = [0,0,1,0]; = [0,0,0,1]; MOVE22 = [1,1,0,0]; MOVE23 = [0,1,1,1]; = [1,0,1,1]; MOVE32 = [1,1,0,1]; MOVE33 = [1,1,1,0]; = [0,0,0,0];
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" Find moves in R11 = X12 & X13 R12 = X11 & X13 R13 = X11 & X12 R21 = X22 & X23 R22 = X21 & X23 R23 = X21 & X22 R31 = X32 & X33 R32 = X31 & X33 R33 = X31 & X32 " Find moves in C11 = X21 & X31 C12 = X22 & X32 C13 = X23 & X33 C21 = X11 & X31 C22 = X12 & X32 C23 = X13 & X33 C31 = X11 & X21 C32 = X12 & X22 C33 = X13 & X23 " Find moves in D11 = X22 & X33 D22 = X11 & X33 D33 = X11 & X22 E13 = X22 & X31 E22 = X13 & X31 E31 = X13 & X22 " Combine G11 = R11 G12 = R12 G13 = R13 G21 = R21 G22 = R22 G23 = R23 G31 = R31 G32 = R32 G33 = R33 equations WHEN ELSE ELSE ELSE ELSE ELSE ELSE ELSE ELSE ELSE
end twoinrow
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rows. & !X11 & !X12 & !X13 & !X21 & !X22 & !X23 & !X31 & !X32 & !X33 Rxy ==> a move exists in cell xy & !Y11; & !Y12; & !Y13; & !Y21; & !Y22; & !Y23; & !Y31; & !Y32; & !Y33;
Ta b l e 6 - 1 3 (continued)
columns. & !X11 & & !X12 & & !X13 & & !X21 & & !X22 & & !X23 & & !X31 & & !X32 & & !X33 &
Cxy ==> a move exists in cell xy !Y11; !Y12; !Y13; !Y21; !Y22; !Y23; !Y31; !Y32; !Y33;
diagonals. Dxy or Exy ==> a move exists in cell xy & !X11 & !Y11; & !X22 & !Y22; & !X33 & !Y33; & !X13 & !Y13; & !X22 & !Y22; & !X31 & !Y31; Gxy ==> a move exists in cell xy
moves for each cell. # C11 # D11; # C12; # C13 # E13; # C21; # C22 # D22 # E22; # C23; # C31 # E31; # C32; # C33 # D33;
G22 THEN MOVE= MOVE22; WHEN G11 THEN MOVE = MOVE11; WHEN G13 THEN MOVE = MOVE13; WHEN G31 THEN MOVE = MOVE31; WHEN G33 THEN MOVE = MOVE33; WHEN G12 THEN MOVE = MOVE12; WHEN G21 THEN MOVE = MOVE21; WHEN G23 THEN MOVE = MOVE23; WHEN G32 THEN MOVE = MOVE32; MOVE = NONE;
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Ta b l e 6 - 1 4 Product-term usage for the TWOINROW PLD.
P-Terms --------61/142 107/129 77/88 133/87 ========= 378/446 Fan-in -----18 18 17 18 Fan-out ------1 1 1 1 Type ---Pin Pin Pin Pin Best P-Term Total: 332 Total Pins: 22 Average P-Term/Output: 83
all possible row, column, and diagonal moves. It combines all of the moves for a cell i,j in an expression for Gij, and finally the equations section uses a WHEN statement to select a move. Note that a nested WHEN statement must be used rather than nine parallel WHEN statements or assignments, because we can only select one move even if multiple moves are available. Also note that G22, the center cell, is checked first, followed by the corners. This was done hoping that we could minimize the number of terms by putting the most common moves early in the nested WHEN. Alas, the design still requires a ton of product terms, as shown in Table 6-14. By the way, we still havent explained why we chose the output coding that we did (as defined by MOVE11, MOVE22, etc. in the program). Its pretty clear that changing the encoding is never going to save us enough product terms to fit the design into a 22V10. But theres still method to this madness, as well now show. Clearly well have to split TWOINROW into two or more pieces. As in any design problem, several different strategies are possible. The first strategy I tried was to use two different PLDs, one to find moves in all the rows and one of the diagonals, and the other to work on all the columns and the remaining diagonal. That helped, but not nearly enough to fit each half into a 22V10. With the second strategy, I tried slicing the problem a different way. The first PLD finds all the moves in cells 11, 12, 13, 21, and 22, and the second PLD finds all the moves in the remaining cells. That worked! The first PLD, named TWOINHAF, is obtained from Table 6-13 simply by commenting out the four lines of the WHEN statement for the moves to cells 23, 31, 32, and 33. We could obtain the second PLD from TWOINROW in a similar way, but lets wait a minute. In the manufacture of real digital systems, it is always desirable to minimize the number of distinct parts that are used; this saves on inventory costs and complexity. With programmable parts, it is desirable to minimize the number of distinct programs that are used. Even though the physical parts are identical, a different set of test vectors must be devised at some cost for each different program. Also, its possible that the product will be successful enough for us to save money by converting the PLDs into hard-coded devices, a different one for each program, again encouraging us to minimize programs.
Name ----------MOVE3 MOVE2 MOVE1 MOVE0
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The Tic-Tac-Toe game is the same game even if we rotate the grid 90 or 180. Thus, the TWOINHAF PLD can find moves for cells 33, 32, 31, 23, and 22 if we rotate the grid 180 . Because of the way we defined the grid state, with a separate pair of inputs for each cell, we can rotate the grid simply by shuffling the input pairs appropriately. That is, we swap 3311, 3212, 3113, and 2321. Of course, once we rearrange inputs, TWOINHAF will still produce output move codes corresponding to cells in the top half of the grid. To keep things straight, we should transform these into codes for the proper cells in the bottom half of the grid. We would like this transformation to take a minimum of logic. This is where our choice of output code comes in. If you look carefully at the MOVE coding defined at the beginning of Table 6-13, youll see that the code for a given position in the 180 rotated grid is obtained by complementing and reversing the order of the code bits for the same position in the unrotated grid. In other words, the code transformation can be done with four inverters and a rearrangement of wires. This can be done for free in the PLD that looks at the TWOINHAF outputs. You probably never thought that Tic-Tac-Toe could be so tricky. Well, were halfway there. Figure 6-13 shows the partitioning of the design as well now continue it. Each TWOINROW PLD from our original partition is replaced
TWOINHAF 9
X11-X33
Y11-Y33
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X11-X33 PICK1 4 MOVE[3:0] WINA[3:0] 9 Y11-Y33 U1 TWOINHAF P X11-X33 4 MOVE[3:0] T WINB[3:0] P Y11-Y33 U2 PICK2 4 TWOINHAF MOVE[3:0] PICK[3:0] X11-X33 4 MOVE[3:0] BLKA[3:0] Y11-Y33 U3 TWOINHAF 4 MOVE[3:0] MOVE[3:0] P X11-X33 T BLKB[3:0] X22 Y22 4 MOVE[3:0] P Y11-Y33 U4 U5 9 9
X22 Y22
Figure 6-13 Final PLD partitioning for the Tic-Tac-Toe game.
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module pick1 Title 'Pick One Move from Four Possible' PICK1 device 'P22V10';
" Inputs from TWOINHAF PLDs WINA3..WINA0 pin 1..4; "Winning moves in cells 11,12,13,21,22 WINB3..WINB0 pin 5..8; "Winning moves in cells 11,12,13,21,22 of rotated grid BLKA3..BLKA0 pin 9..11, 13; "Blocking moves in cells 11,12,13,21,22 BLKB3..BLKB0 pin 14..16, 21; "Blocking moves in cells 11,12,13,21,22 of rotated grid " Inputs from grid X22, Y22 pin 22..23; "Center cell; pick if no other moves " Move outputs to PICK2 PLD MOVE3..MOVE0 pin 17..20 istype 'com'; " Sets WINA = [WINA3..WINA0]; BLKA = [BLKA3..BLKA0]; MOVE = [MOVE3..MOVE0]; WINB = [WINB3..WINB0]; BLKB = [BLKB3..BLKB0];
" Non-rotated move input and MOVE11 = [1,0,0,0]; MOVE12 = MOVE21 = [0,0,0,1]; MOVE22 = MOVE31 = [1,0,1,1]; MOVE32 = NONE = [0,0,0,0]; equations WHEN ELSE ELSE ELSE ELSE ELSE WINA WHEN WHEN WHEN WHEN MOVE
end pick1
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Ta b l e 6 - 1 5 ABEL program to pick one move based on four inputs.
output encoding [0,1,0,0]; MOVE13 = [0,0,1,0]; [1,1,0,0]; MOVE23 = [0,1,1,1]; [1,1,0,1]; MOVE33 = [1,1,1,0]; != NONE THEN MOVE = WINA; WINB != NONE THEN MOVE = ![WINB0..WINB3]; BLKA != NONE THEN MOVE = BLKA; BLKB != NONE THEN MOVE = ![BLKB0..BLKB3]; !X22 & !Y22 THEN MOVE = MOVE22; = NONE; " Map rotated coding " Map rotated coding " Pick center cell if its empty
by a pair of TWOINHALF PLDs. The bottom PLD of each pair is preceded by a box labeled P, which permutes the inputs to rotate the grid 180 as discussed previously. Likewise, it is followed by a box labeled T, which compensates for the rotation by transforming the output code; this box will actually be absorbed into the PLD that follows it, PICK1. The function of PICK1 is pretty straightforward. As shown in Table 6-15, it is simply picks a winning move or a blocking move if one is available. Since there are two extra input pins available on the 22V10, we use them to input the state of the center cell. In this way, we can perform the first part of step 3 of the human algorithm on page 488, to pick the center cell if no winning or blocking move is available. The PICK1 PLD uses at most 9 product terms per output.
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The final part of the design in Figure 6-13 is the PICK2 PLD. This PLD must provide most of the experience in step 3 of the human algorithm if PICK1 does not find a move. We have a little problem with PICK2 in that a 22V10 does not have enough pins to accommodate the 4-bit input from PICK1, its own 4-bit output, and all 18 bits of grid state; it has only 22 I/O pins. Actually, we dont need to connect X22 and Y22, since they were already examined in PICK1, but that still leaves us two pins short. So, the purpose of the other logic block in Figure 6-13 is to encode
Ta b l e 6 - 1 6 ABEL program to pick one move using experience.
module pick2 Title 'Pick a move using experience' PICK2 device 'P22V10';
" Inputs from PICK1 PLD PICK3..PICK0 pin " Inputs from Tic-Tac-Toe grid corners X11, Y11, X13, Y13, X31, Y31, X33, Y33 pin " Combined inputs from external NOR gates; 1 E12, E21, E23, E32 pin " Move output MOVE3..MOVE0 pin
PICK = [PICK3..PICK0]; " Set definition " Non-rotated move input and output encoding MOVE = [MOVE3..MOVE0]; MOVE11 = [1,0,0,0]; MOVE12 = [0,1,0,0]; MOVE13 = [0,0,1,0]; MOVE21 = [0,0,0,1]; MOVE22 = [1,1,0,0]; MOVE23 = [0,1,1,1]; MOVE31 = [1,0,1,1]; MOVE32 = [1,1,0,1]; MOVE33 = [1,1,1,0]; NONE = [0,0,0,0]; " Intermediate equations for empty corner cells E11 = !X11 & !Y11; E13 = !X13 & !Y13; E31 = !X31 & !Y31; equations "Simplest WHEN PICK ELSE WHEN ELSE WHEN ELSE WHEN ELSE WHEN ELSE WHEN ELSE WHEN ELSE WHEN ELSE WHEN ELSE MOVE end pick2
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1..4; " Move, if any, from PICK1 PLD 5..11, 13; ==> corresponding cell is empty 14..15, 22..23; 17..20 istype 'com'; E33 = !X33 & !Y33; approach -- pick corner if available, else side != NONE THEN MOVE = PICK; E11 THEN MOVE = MOVE11; E13 THEN MOVE = MOVE13; E31 THEN MOVE = MOVE31; E33 THEN MOVE = MOVE33; E12 THEN MOVE = MOVE12; E21 THEN MOVE = MOVE21; E23 THEN MOVE = MOVE23; E32 THEN MOVE = MOVE32; = NONE;
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some of the information to save two pins. The method that well use here is to combine the signals for the middle edge cells 12, 21, 23, and 32 to produce four signals E12, E21, E23, and E32 that are asserted if and only if the corresponding cells are empty. This can be done with four 2-input NOR gates, and actually leaves two spare inputs or outputs on the 22V10. Assuming the four NOR gates as other logic, Table 6-16 on the preceding page gives a program for the PICK2 PLD. When it must pick a move, this program uses the simplest heuristic possibleit picks a corner cell if one is empty, else it picks a middle edge cell. This program could use some improvement, because it will sometimes lose (see Exercise 6.8). Luckily, the equations resulting from Table 6-16 require only 8 to 10 terms per output, so its possible to put in more intelligence (see Exercises 6.9 and 6.10).
6.3.1 Barrel Shifter On page 464, we defined a barrel shifter as a combinational logic circuit with n data inputs, n data outputs, and a set of control inputs that specify how to shift the data between input and output. We showed in Section 6.1.1 how to build a simple barrel shifter that performs only left circular shifts using MSI building blocks. Later, in Section 6.2.1, we showed how to define a more capable barrel shifter using ABEL, but we also pointed out that PLDs are normally unsuitable for realizing barrel shifters. In this subsection, well show how VHDL can be used to describe both the behavior and structure of barrel shifters for FPGA or ASIC realization. Table 6-17 is a behavioral VHDL program for a 16-bit barrel shifter that performs any of six different combinations of shift type and direction. The shift types are circular, logical, and arithmetic, as defined previously in Table 6-3, and the directions are of course left and right. As shown in the entity declaration, a 4-bit control input S gives the shift amount, and a 3-bit control input C gives the shift mode (type and direction). We used the IEEE std_logic_arith package and defined the shift amount S to be type UNSIGNED so we could later use the CONV_INTEGER function in that package. Notice that the entity declaration includes six constant definitions that establish the correspondence between shift modes and the value of C. Although we didnt discuss it in Section 4.7, VHDL allows you to put constant, type, signal, and other declarations within an entity declaration. It makes sense to define such items within the entity declaration only if they must be the same in any architecture. In this case, we are pinning down the shift-mode encodings, so they should go here. Other items should go in the architecture definition. In the architecture part of the program, we define six functions, one for each kind of shift on a 16-bit STD_LOGIC_VECTOR. We defined the subtype DATAWORD to save typing in the function definitions.
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library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity barrel16 is port ( DIN: in STD_LOGIC_VECTOR (15 downto 0); -S: in UNSIGNED (3 downto 0); -C: in STD_LOGIC_VECTOR (2 downto 0); -DOUT: out STD_LOGIC_VECTOR (15 downto 0) -); constant Lrotate: STD_LOGIC_VECTOR := "000"; constant Rrotate: STD_LOGIC_VECTOR := "001"; constant Llogical: STD_LOGIC_VECTOR := "010"; constant Rlogical: STD_LOGIC_VECTOR := "011"; constant Larith: STD_LOGIC_VECTOR := "100"; constant Rarith: STD_LOGIC_VECTOR := "101"; end barrel16; architecture barrel16_behavioral of barrel16 is subtype DATAWORD is STD_LOGIC_VECTOR(15 downto 0); function Vrol (D: DATAWORD; S: UNSIGNED) return DATAWORD is variable N: INTEGER; variable TMPD: DATAWORD; begin N := CONV_INTEGER(S); TMPD := D; for i in 1 to N loop TMPD := TMPD(14 downto 0) & TMPD(15); end loop; return TMPD; end Vrol; ... begin process(DIN, S, C) begin case C is when Lrotate => DOUT <= when Rrotate => DOUT <= when Llogical => DOUT <= when Rlogical => DOUT <= when Larith => DOUT <= when Rarith => DOUT <= when others => null; end case; end process; end barrel16_behavioral;
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Ta b l e 6 - 1 7 VHDL behavioral description of a 6-function barrel shifter.
Data inputs Shift amount, 0-15 Mode control Data bus output -- Define the coding of -- the different shift modes Vrol(DIN,S); Vror(DIN,S); Vsll(DIN,S); Vsrl(DIN,S); Vsla(DIN,S); Vsra(DIN,S);
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VHDL-93 actually has built-in array operators, rol, ror, sll, srl, sla, and sra, corresponding to the shift operations that we defined in Table 6-3. Since these operations are not provided in VHDL-87, weve defined our own functions in Table 6-17. Well, actually weve only defined one of them (Vrol); the rest are left as an exercise for the reader (Exercise 6.11).
Table 6-17 shows the details of only the first function (Vrol); the rest are similar with only a one-line change. We define a variable N for converting the shift amount S into an integer for the for loop. We also assign the input vector D to a local variable TMPD which is shifted N times in the for loop. In the body of the for loop, a single assignment statement takes a 15-bit slice of the data word (TMPD 14 downto 0)) and uses concatenation (&) to put it back together with the bit that falls off the left end (TMPD(15)). Other shift types can be described with similar operations. Note that the shift functions might not be defined in other, nonbehavioral descriptions of the barrel16 entity, for example in structural architectures. The concurrent statements part of the architecture is a single process that has all of the entitys inputs in its sensitivity list. Within this process, a case statement assigns a result to DOUT by calling the appropriate function based on the value of the mode-control input C. The process in Table 6-17 is a nice behavioral description of the barrel shifter, but most synthesis tools cannot synthesize a circuit from it. The problem is that most tools require the range of a for loop to be static at the time it is analyzed. The range of the for loop in the Vrol function is dynamic; it depends on the value of input signal S when the circuit is operating. Well, thats OK, its hard to predict what kind of circuit the synthesis tool would come up with even if it could handle a dynamic for range. This is an example where as designers we should take little more control over the circuit structure to obtain a reasonably fast, efficient synthesis result. In Figure 6-2 on page 466, we showed how to design a 16-bit barrel shifter for left circular shifts using MSI building blocks. We used a cascade of four 16-bit, 2-input multiplexers to shift their inputs by 0 or 1, 2, 4, or 8 positions depending of the values of S0 through S3, respectively. We can express the same kind behavior and structure using the VHDL program shown in Table 6-18. Even though the program uses a process and is therefore behavioral in style, we can be pretty sure that most synthesis engines will generate a 1-input multiplexer for each if statement in the program, thereby creating a cascade similar to Figure 6-2.
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library IEEE; use IEEE.std_logic_1164.all;
entity rol16 is port ( DIN: in STD_LOGIC_VECTOR(15 downto 0); -- Data inputs S: in STD_LOGIC_VECTOR (3 downto 0); -- Shift amount, 0-15 DOUT: out STD_LOGIC_VECTOR(15 downto 0) -- Data bus output ); end rol16;
architecture rol16_arch of rol16 is begin process(DIN, S) variable X, Y, Z: STD_LOGIC_VECTOR(15 downto 0); begin if S(0)='1' then X := DIN(14 downto 0) & DIN(15); else X := DIN; end if; if S(1)='1' then Y := X(13 downto 0) & X(15 downto 14); else Y := X; end if; if S(2)='1' then Z := Y(11 downto 0) & Y(15 downto 12); else Z := Y; end if; if S(3)='1' then DOUT <= Z(7 downto 0) & Z(15 downto 8); else DOUT <= Z; end if; end process; end rol16_arch;
Of course, our problem statement requires a barrel shifter that can shift both left and right. Table 6-19 revises the previous program to do circular shifts in either direction. An additional input, DIR, specifies the shift direction, 0 for left, 1 for right. Each rank of shifting is specified by a case statement that picks one of four possibilities based on the values of DIR and the bit of S that controls that rank. Notice that we created local 2-bit variables CTRLi to hold the pair of values DIR and S(i); each case statement is controlled by one of these variables. You might like to eliminate these variables and simply control each case statement with a concatenation DIR & S(i), but VHDL syntax doesnt allow that because the type of this concatenation would be unknown. A typical VHDL synthesis tool will generate a 3- or 4-input multiplexer for each of the case statements in Table 6-19. A good synthesis tool will generate only a 2-input multiplexer for the last case statement. So, now we have a barrel shifter that will do left or right circular shifts, but were not done yetwe need to take care of the logical and arithmetic shifts in both directions. Figure 6-14 shows our strategy for completing the design. We start out with the ROLR16 component that we just completed, and use other logic to control the shift direction as a function of C.
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T a b l e 6 - 1 8 VHDL program for a 16-bit barrel shifter for left circular shifts only. Copying Prohibited
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library IEEE; use IEEE.std_logic_1164.all; entity rolr16 port ( DIN: S: DIR: DOUT: ); end rolr16; is
architecture rol16r_arch of rolr16 is begin process(DIN, S, DIR) variable X, Y, Z: STD_LOGIC_VECTOR(15 downto 0); variable CTRL0, CTRL1, CTRL2, CTRL3: STD_LOGIC_VECTOR(1 downto 0); begin CTRL0 := S(0) & DIR; CTRL1 := S(1) & DIR; CTRL2 := S(2) & DIR; CTRL3 := S(3) & DIR; case CTRL0 is when "00" | "01" => X := DIN; when "10" => X := DIN(14 downto 0) & DIN(15); when "11" => X := DIN(0) & DIN(15 downto 1); when others => null; end case; case CTRL1 is when "00" | "01" => Y := X; when "10" => Y := X(13 downto 0) & X(15 downto 14); when "11" => Y := X(1 downto 0) & X(15 downto 2); when others => null; end case; case CTRL2 is when "00" | "01" => Z := Y; when "10" => Z := Y(11 downto 0) & Y(15 downto 12); when "11" => Z := Y(3 downto 0) & Y(15 downto 4); when others => null; end case; case CTRL3 is when "00" | "01" => DOUT <= Z; when "10" | "11" => DOUT <= Z(7 downto 0) & Z(15 downto 8); when others => null; end case; end process; end rol16r_arch;
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Ta b l e 6 - 1 9 VHDL program for a 16-bit barrel shifter for left and right circular shifts.
in STD_LOGIC_VECTOR(15 downto 0); in STD_LOGIC_VECTOR (3 downto 0); in STD_LOGIC; out STD_LOGIC_VECTOR(15 downto 0) ----Data inputs Shift amount, 0-15 Shift direction, 0=>L, 1=>R Data bus output
Next we must fix up some of the result bits if we are doing a logical or arithmetic shift. For a left logical or arithmetic n-bit shift, we must set the rightmost n1 bits to 0 or the original rightmost bit value, respectively. For a right logical or arithmetic n-bit shift, we must set the leftmost n1 bits to 0 or the original leftmost bit value, respectively.
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DIN(15:0)
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As shown in Figure 6-14, our strategy is to follow the circular shifter (ROLR16) with a fix-up circuit (FIXUP) that plugs in appropriate low-order bits for a left logical or arithmetic shift, and follow that with another fix-up circuit that plugs in high-order bits for a right logical or arithmetic shift. Table 6-20 is a behavioral VHDL program for the left-shift fix-up circuit. The circuit has 16 bits of data input and output, DIN and DOUT. Its control inputs are the shift amount S, an enable input FEN, and the new value FDAT to be plugged into the fixed-up data bits. For each output bit DOUT(i), the circuit puts out the fixed-up bit value if i is less than S and the circuit is enabled; else it puts out the unmodified data input DIN(i). The for loop in Table 6-20 is readily synthesizable, but you cant really be sure what kind of logic the synthesis tool will generate. In particular, the >
Ta b l e 6 - 2 0 Behavioral VHDL program for left-shift fix-ups.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity fixup is port ( DIN: in STD_LOGIC_VECTOR(15 downto 0); S: in UNSIGNED(3 downto 0); FEN: in STD_LOGIC; FDAT: in STD_LOGIC; DOUT: out STD_LOGIC_VECTOR(15 downto 0) ); end fixup;
architecture fixup_arch of fixup is begin process(DIN, S, FEN, FDAT) begin for i in 0 to 15 loop if (i < CONV_INTEGER(S)) and (FEN = '1') then DOUT(i) <= FDAT; else DOUT(i) <= DIN(i); end if; end loop; end process; end fixup_arch;
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ROLR16 FIXUP (left) FIXUP (right) DOUT(15:0)
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S(3:0)
other logic
Figure 6-14 Barrel-shifter components.
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Data inputs Shift amount, 0-15 Fixup enable Fixup data Data bus output
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architecture fixup_struc of fixup is signal FSEL: STD_LOGIC_VECTOR(15 downto 0); -- Fixup select begin FSEL(15) <= '0'; DOUT(15) <= DIN(15); U1: for i in 14 downto 0 generate FSEL(i) <= '1' when CONV_INTEGER(S) = i+1 else FSEL(i+1); DOUT(i) <= FDAT when (FSEL(i) = '1' and FEN = '1') else DIN(i); end generate; end fixup_struc;
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A SERIAL FIX-UP STRUCTURE Ta b l e 6 - 2 1 Structural VHDL architecture for left-shift fix-ups. Copyright 1999 by John F. Wakerly
A structural architecture for the fix-up logic is shown in Table 6-21. Here, we have defined what is in effect an iterative circuit to create a 16-bit vector FSEL, where FSEL(i) is 1 if bit i needs fixing up. We start by setting FSEL(15) to 0, since that bit never needs fixing up. Then we note that for the remaining values of i, FSEL(i) should be 1 if S equals i+1 or if FSEL(i+1) is already asserted. Thus, the FSEL assignment within the generate statement creates a serial chain of 2-input OR gates, where one input is asserted if S=i (decoded with a 4-input AND gate), and the other input is connected to the previous OR gates output. The DOUT(i) assignment statement creates 16 2-input multiplexers that select either DIN(i) or the fix-up data (FDAT) depending of the value of FSEL(i). Although the serial realization is compact, it is very slow compared to a one that realizes each FSEL output as a 2-level sum-of-products circuit. However, the long delay may not matter because the fix-up circuit appears near the end of the data path. If speed is still a problem, there is a zero-cost trick that cuts the delay in half (see Exercise 6.12).
operation in each step of the loop may cause the synthesis of a general-purpose magnitude comparator, even though one of the operands is a constant and each output could therefore be generated with no more than a handful of gates. (In fact, the logic for 7 < CONV_INTEGER(S) is just a wire, S(3)!) For a structural version of this function, see the box on this page. For right shifts, fix-ups start from the opposite end of the data word, so it would appear that we need a second version of the fix-up circuit. However, we can use the original version if we just reverse the order of its input and output bits, as well soon see. Table 6-22 puts together a structural architecture for the complete, 16-bit, 6-function barrel shifter using the design approach of Figure 6-14 on page 501. The entity declaration for barrel16 is unchanged from the original in Table 6-17 on page 497. The architecture declares two components, rolr16 and fixup; these use our previous entity definitions. The statement part of the architecture
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instantiates rolr16 and fixup and has several assignment statements that create needed control signals (the other logic in Figure 6-14). For example, the first assignment statement asserts DIR_RIGHT if C specifies one of the right shifts. The enable inputs for the left and right fix-up circuits are FIX_LEFT and FIX_RIGHT, asserted for left and right logical and arithmetic shifts. The fix-up data values are FIX_LEFT_DAT and FIX_RIGHT_DAT. While all the statements in the architecture execute concurrently, they are listed in Table 6-22 in the order of the actual dataflow to improve readability. First, rolr16 is instantiated to perform the basic left or right circular shift as specified. Its outputs are hooked up to the inputs of the first fixup component (U2) to handle fix-ups for left logical and arithmetic shifts. Next comes U3, a generate statement that reverses the order of the data inputs for the next fixup
architecture barrel16_struc of barrel16 is
component rolr16 port ( DIN: in STD_LOGIC_VECTOR(15 downto 0); S: in UNSIGNED(3 downto 0); DIR: in STD_LOGIC; DOUT: out STD_LOGIC_VECTOR(15 downto 0) ); end component; component fixup port ( DIN: in STD_LOGIC_VECTOR(15 downto 0); S: in UNSIGNED(3 downto 0); FEN: in STD_LOGIC; FDAT: in STD_LOGIC; DOUT: out STD_LOGIC_VECTOR(15 downto 0) ); end component;
signal DIR_RIGHT, FIX_RIGHT, FIX_RIGHT_DAT, FIX_LEFT, FIX_LEFT_DAT: STD_LOGIC; signal ROUT, FOUT, RFIXIN, RFIXOUT: STD_LOGIC_VECTOR(15 downto 0);
begin DIR_RIGHT <= '1' when C = Rrotate or C = Rlogical or C = Rarith else '0'; FIX_LEFT <= '1' when DIR_RIGHT='0' and (C = Llogical or C = Larith) else '0'; FIX_RIGHT <= '1' when DIR_RIGHT='1' and (C = Rlogical or C = Rarith) else '0'; FIX_LEFT_DAT <= DIN(0) when C = Larith else '0'; FIX_RIGHT_DAT <= DIN(15) when C = Rarith else '0'; U1: rolr16 port map (DIN, S, DIR_RIGHT, ROUT); U2: fixup port map (ROUT, S, FIX_LEFT, FIX_LEFT_DAT, FOUT); U3: for i in 0 to 15 generate RFIXIN(i) <= FOUT(15-i); end generate; U4: fixup port map (RFIXIN, S, FIX_RIGHT, FIX_RIGHT_DAT, RFIXOUT); U5: for i in 0 to 15 generate DOUT(i) <= RFIXOUT(15-i); end generate; end barrel16_struc;
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Ta b l e 6 - 2 2 VHDL structural architecture for the 6-function barrel shifter.
----Data inputs Shift amount, 0-15 Shift direction, 0=>L, 1=>R Data bus output -----Data inputs Shift amount, 0-15 Fixup enable Fixup data Data bus output
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Based on the encoding of C, you might like to replace the first assignment statement in Table 6-21 with DIR_RIGHT <= C(0), which would be guaranteed to lead to a more efficient realization for that control bitjust a wire! However, this would violate a programming principle of information hiding and lead to possible bugs. We explicitly wrote the shift encodings using constant definitions in the barrel16 entity declaration. The architecture does not need to be aware of the encoding details. Suppose that we nevertheless made the architecture change suggested above. If somebody else (or we!) came along later and changed the constant definitions in the barrel16 entity to make a different encoding, the architecture would not use the new encodings! Exercise 6.13 asks you to change the definitions so that the cost savings of our suggested change are enabled by the entity definition.
component (U4), which handles fix-ups for right logical and arithmetic shifts. Finally U5, another generate statement, undoes the bit reversing of U3. Note that in synthesis, U3 and U5 are merely permutations of wires. Many other architectures are possible for the original barrel16 entity. In Exercise 6.14, we suggest an architecture that enables the circular shifting to be done by the rol16 entity, which uses only 2-input multiplexers, rather than the more expensive rolr16. 6.3.2 Simple Floating-Point Encoder We defined a simple floating-point number format on page 467, and posed the design problem of converting a number from fixed-point to this floating point format. The problem of determining the exponent of the floating-point number mapped nicely into an MSI priority encoder. In an HDL, the same problem maps into nested if statements. Table 6-23 is a behavioral VHDL program for the floating-point encoder. Within the fpenc_arch architecture, a nested if statement checks the range of the input B and sets M and E appropriately. Notice that the program uses the IEEE std_logic_arith packag