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6 Pages

Final Exam

Course: ECE 315, Spring 2006
School: North Texas
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Word Count: 697

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Exam Final ECE 315 Spring 2006 Open Book and two pages of notes 1. 10pts. Below is a semiconductor which has been patterned into the shape illustrated. The thickness of the material is 1um with a mobility of 1000 cm2/Vsec. Assume the fields transform abruptly at the interface. The doping in region 1 and region 3 is 1x1017cm-3 the doping in region 2 is 1x1016cm3 L1=10um, L2=50um, L3=20um and W1=100um, W2=10um,...

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Exam Final ECE 315 Spring 2006 Open Book and two pages of notes 1. 10pts. Below is a semiconductor which has been patterned into the shape illustrated. The thickness of the material is 1um with a mobility of 1000 cm2/Vsec. Assume the fields transform abruptly at the interface. The doping in region 1 and region 3 is 1x1017cm-3 the doping in region 2 is 1x1016cm3 L1=10um, L2=50um, L3=20um and W1=100um, W2=10um, W3=50um a. b. c. d. Calculate the total resistance of each layer. What is the current in each layer if a voltage of 1V is applied to as shown What is the electron drift velocity in each layer If the voltage is increased and the saturation velocity is 1x107cm/sec. What is the voltage VA where saturation velocity is achieved in the materia L2 L1 Contact W1 W3 L3 Region 3 W2 Region 2 Region 1 V 2. 15pts. For a MOS Capacitor biased as shown below Vtn =1V. a. Sketch the charge vs distance for (VA=1V and VB=0) and (VA=1V and VB=.5V) b. Sketch the Electic Field vs distance. for (VA=1V and VB=0) and(VA=1V and VB=.5V) c. Sketch the Potential vs distance. for (VA=1V and VB=0) and (VA=1V and VB=.5V) d. Sketch the carrier densisty (n, p) verses distance. for, (VA=1V and VB=0) and (VA=1V and VB=.5V) For all graphs use the scale shown below indicate the different conditions by solid or dotted lines. Metal n+ poly Si Semiconductor (p type) Oxide V A F, (n, p), V B -tOx X 0 Solid line is case 1 inversion Dotted line is case 2 3. 10pts A MOS transistor has a threshold voltage (Vtn) of +1V the gate voltage is 2V and the Drain voltage is 5V if COx=5x10-8F/cm2 and u=100 cm2/V-sec. Assume the source and the body are connected to the ground potential. If W/L=100 and W=100um L=1um. a. What is the value of the carrier density n (number of carriers/cm2) at the source of the transistor for a drain voltage of 1V. b. For a drain voltage of 1V, and 5V calculate the carrier velocity at the source. For c. the gate voltage of 2V and if the satauration velocity of Si 1x107cm/sec approximate the carrier density at the drain termininal 4. 10pts Consider the bipolar circuit shown below the ac voltage is (.002)sin(106t)V calculate the current I required to make the voltage across the capacitor have a phase angle of -45degrees with respect to the input ac voltage. =100, C=10nF I C ~ 5. 10pts For a standard CMOS inverter circuit as shown VDD=5Volts. If Vtn= -Vtp=1V, and n=p=.1V-1 COx=50uA/V2 for the NMOS transistor and 25uA/V2for the PMOS transistor. Calculate the gate length (Ln and Lp) and W/L ratio for each device to produce a symetric transfer curve and a Noise Margin (NMH= NML) of greater than or equal to 2.4V. Neglect channel modulation effects 6. 15pts a. Consider the NMOS CS amplifier shown below Cgs=1pF, Cgd=1pF, Rs=100ohms, For I=500uA, roc(current source) =500K, ro of transistor=2Meg ohms a. Draw the small signal diagram b. Calculate the transistion frequency ft.(do not use Miller approx) c. Using the Miller approximation calculate the transfer function (Vout/Vin). What is 3dB I RS Vout ~ 10pts b. An additional transistor with the same equivalent circuit elements is added to form a cascode configuration shown below. Vg2 is high enough to bias the device in saturation. a. Draw the small signal diagram b. Using the Miller techniques calculate the transfer function c. What is the ratio of 3dB cascode/3db CS? I Vout Vg2 RS ~ 7. 10pts Plot the Bode plot both phase and magnitude for the following function 1 s /102 5 T(s) 10 1 s / .1 1 s /104 1 s /107 8. 10pts Consider the differential amplifier circuit shown below with acitve loads. Assume Vb is above the NMOS threshold Vtn. What is the minimal common-mode voltage that can keep the bias transistor Qb saturated? Use VDD Q3 Q4 vout vcm- vcm+ Q1 Q2 Vb Qb only Vb and Vth in your expression
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