Penn State, CSE 477
Excerpt: ... CSE477 VLSI Digital Circuits Fall 2001 Lecture 04: CMOS Inverter (static view) Vijay Narayanan www.cse.psu.edu/~cg477 [Adapted in part from Rabaey's Digital Integrated Circuits, Prentice Hall, 1995] CSE477 L04 CMOS Inverter .1 Irwin&Vijay, PSU, 2001 Review: The MOS Transistor Gate oxide Polysilicon W Gate Source n+ L Drain n+ Field-Oxide (SiO2) p substrate p+ stopper Bulk (Body) CROSS-SECTION of NMOS Transistor CSE477 L04 CMOS Inverter .2 Irwin&Vijay, PSU, 2001 CMOS Inverter : A First Look VDD Vin CL Vout CSE477 L04 CMOS Inverter .3 Irwin&Vijay, PSU, 2001 CMOS Inverter : Steady State Response VDD VDD Rp Vout = 1 Rn Vout = 0 Vin = 0 Vin = V DD CSE477 L04 CMOS Inverter .4 Irwin&Vijay, PSU, 2001 CMOS Properties q Full rail-to-rail swing high noise margins l Logic levels not dependent upon the relative device sizes ratioless q Always a path to Vdd or Gnd in steady state low output impedance (output resistance in k range) Extremely high input resistance (gate of MOS transistor is near per ...
Texas A&M, ELEN 454
Excerpt: ... ECEN 454 Digital Integrated Circuit Design Lecture 8 MOS Inverter Characteristics II ECEN 454 Lecture 8 1 CMOS Inverter Static power dissipation Leakage power does exist important for VDSM designs VTC resembles that of the ideal inverter Full output voltage swing: 0V Sharp VTC transition VDD ECEN 454 Lecture 8 2 Regions of Operation ECEN 454 Lecture 8 3 VTC of CMOS Inverter (1) I D , n = f n (V in , V out ) = I D , p = f p (V in , V out ) nMOS pMOS ECEN 454 Lecture 8 4 VTC of CMOS Inverter (2) 3D perspective of VTC ECEN 454 Lecture 8 5 VTC of CMOS Inverter (3) ECEN 454 Lecture 8 6 VTC of CMOS Inverter (4) Adopted from the lecture materials of CMU 18-322, Analysis and Design of Digital ICs ECEN 454 Lecture 8 7 VTC of CMOS Inverter (5) Adopted from the lecture materials of CMU 18-322, Analysis and Design of Digital ICs ECEN 454 Lecture 8 8 VTC of CMOS Inverter (6) Adopted from the lecture materials of CMU 18- ...
UCSD, ECE 260
Excerpt: ... ECE 260A VLSI Digital Circuits & Systems Fall 2002 Lecture 04: CMOS Inverter (static view) Paul M. Chau ( chau@ece.ucsd.edu ) [Adapted from Rabaey's Digital Integrated Circuits, 2002, J. Rabaey et al.; MJIrwin PSU 2002] VLSI Design: L4 Static CMOS Inverter .1 Chau/Cichy UCSD ECE Review: Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT Vin Vout DEVICE G S n+ D n+ VLSI Design: L4 Static CMOS Inverter .2 Chau/Cichy UCSD ECE Review: The MOS Transistor Gate oxide Polysilicon W Gate Source n+ L Drain n+ Field-Oxide (SiO2) p substrate p+ stopper Bulk (Body) VLSI Design: L4 Static CMOS Inverter .3 Chau/Cichy UCSD ECE CMOS Inverter : A First Look VDD Vin CL Vout VLSI Design: L4 Static CMOS Inverter .4 Chau/Cichy UCSD ECE CMOS Inverter : Steady State Response VDD VDD VOL = 0 VOH = VDD VM = f(Rn, Rp) Rp Vout = 1 Rn Vout = 0 Vin = 0 VLSI Design: L4 Static CMOS Inverter .5 Vin = V DD Chau/Cichy UCSD ECE CMOS Properties q Full rail-to-rail swing high noise margins l Logic levels not depend ...
MIT, ELECTRICAL 6.012
Excerpt: ... 6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 141 Lecture 14 Digital Circuits (III) CMOS October 27, 2005 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter : noise margins 3. CMOS inverter : propagation delay 4. CMOS inverter : dynamic power Reading assignment: Howe and Sodini, Ch. 5, 5.4 Announcements: Cadence tutorial by Kerwin Johnson in place of reg ular recitations on Friday 10/28 6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 142 Key questions How does CMOS work? What is special about CMOS as a logic technology? What are the key design parameters of a CMOS in verter? How can one estimate the propagation delay of a CMOS inverter ? Does CMOS burn any power? 6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 143 1. Complementary MOS (CMOS) Inverter Circuit schematic: VDD VIN CL VOUT Basic operation: VIN = 0 VOU T = VDD VGSn = 0 < VT n NMOS OFF VSGp = VDD > -VT p PMOS ON VIN = VDD VOU T = 0 VGSn = VDD > ...
UMBC, CPATEL 640
Excerpt: ... Advanced VLSI Design CMOS Inverter CMPE 640 The Inverter The electrical behavior of complex circuits (adders, multipliers) can be almost completely derived by extrapolating the results obtained for inverters! VGS < Vt Vin Vout CL Modeled Ron Vout VGS > Vt Ron Vout Observations Fully restored (VDD and GND) output levels results in high noise margins. Ratioless: Logic levels are not dependent on the relative device sizes. Low output impedance in steady state (kW connection to either VDD or GND), increases robustness to noise. High input impedance: fanout is theoretically unlimited for static operation, transient response is impacted however. Low static power dissipation: No path between power and ground. 1 Advanced VLSI Design CMOS Inverter 2.5V 2.0V 1.5V CMPE 640 The Inverter DC current characteristics 0V 0.5V IDS (mA) Load-line plot Here, PMOS curves have been mirrored around x and shifted. The current of the NMOS and PMOS device MUST be equal. All points are located at either the 0V high or low ...
Berkeley, EE 40
Excerpt: ... EECS 40 Spring 2003 Lecture 21 S. Ross EECS 40 Spring 2003 Lecture 21 S. Ross CMOS INVERTER CMOS means Complementary MOS: NMOS and PMOS working together in a circuit VDD (Logic 1) S D D VOUT VIN S EECS 40 Spring 2003 Lecture 21 S. Ross EECS 40 Spring 2003 Lecture 21 S. Ross CMOS INVERTER RESPONSE VOUT VDD VM: Voltage when VIN = VOUT (= VM) A B C D E VIN VDD EECS 40 Spring 2003 Lecture 21 S. Ross EECS 40 Spring 2003 Lecture 21 S. Ross LAST TIME: SINGLE TRANSISTOR CIRCUIT ID triode mode saturation mode VGS = 3 V VDS = VGS - VTH(N) Linear ID vs VDS given by surrounding circuit X VGS = 1 V VDS X EECS 40 Spring 2003 Lecture 21 S. Ross EECS 40 Spring 2003 Lecture 21 S. Ross ANALYSIS OF INVERTER CIRCUT Obtain: 1) the two nonlinear ID vs. VDS equations for the transistors: ID(N) vs. VDS(N) and ID(P) vs. VDS(P) 2) A linear relationship between ID(N) and ID(P) (e.g., via KCL) 3) An independent linear relationship between VDS(N) and VDS(P) (e.g. via KVL) Using the above, write: ID(P) vs. ...
Berkeley, EE 40
Excerpt: ... EECS 40 Spring 2003 Lecture 21 S. Ross CMOS INVERTER CMOS means Complementary MOS: NMOS and PMOS working together in a circuit VDD (Logic 1) S D D VOUT VIN S EECS 40 Spring 2003 Lecture 21 S. Ross CMOS INVERTER RESPONSE VOUT VDD M V : Voltage when IN OUT M V =V (= V ) VIN VDD A B C D E EECS 40 Spring 2003 Lecture 21 S. Ross LAST TIME: SINGLE TRANSISTOR CIRCUIT ID triode mode saturation mode VGS = 3 V DS GS TH(N) X V = VLinear ID vs VDS given -V by surrounding circuit X VGS = 1 V VDS EECS 40 Spring 2003 Lecture 21 S. Ross ANALYSIS OF INVERTER CIRCUT Obtain: 1) the two nonlinear ID vs. VDS equations for the transistors: ID(N) vs. VDS(N) and ID(P) vs. VDS(P) 1) A linear relationship between ID(N) and ID(P) (e.g., via KCL) 1) An independent linear relationship between VDS(N) and VDS(P) (e.g. via KVL) Using the above, write: ID(P) vs. VDS(P) in terms of ID(N) vs. VDS(N) (or vice-versa) Solve the two transistor equations simultaneously. EECS 40 Spring 2003 Lecture 21 S. Ross ANALYSI ...
Mississippi State, ECE 4263
Excerpt: ... ECE 4263 (VLS) Test 1 Study Guide The test is closed book/closed notes. Bring black, blue, purple, green markers. You will not need a calculator. You will be provided with the Shockley equations for a MOSFET, and the equation for Cox. a. Given a combinational boolean equation, give a static CMOS implementation and stick diagram layout. b. Recognize the difference between a pass transistor and transmission gate, and explain the advantage of a transmission gate. c. For chains of N or P pass transistors, be able to describe the resulting output voltage using either degraded/strong 0/1 terminology, or in terms symbolic names like Vdd, Vt, GND, etc. d. Given a CMOS transistor schematic, be able to give a truth table for the output using 0, 1, z. e. Be able to describe the basic fabrication steps for a CMOS inverter (Figures 1.36, 1.37, 1.38). f. Be able to draw the cross-section of a CMOS inverter and label all of the parts. g. Be able to draw typical operation curves for an NMOS, PMOS transisto ...
MIT, ELECTRICAL 6.012
Excerpt: ... 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 2005 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, 5.3 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-2 Key questions What are the key design trade-offs of the NMOS inverter with resistor pull-up? How can one improve upon these trade-offs? What is special about a CMOS inverter ? 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-3 1. NMOS inverter with resistor pull-up (cont.) V+=VDD IR VOUT ID VIN CL VOL=VMIN 0 0 VT VM VIL VIH VDD VIN=VGS VM VOUT=VDS VOH=VMAX=VDD R slope= Av(VM) VOUT=VIN 2 Noise margins: N ML = VIL - VOL = VM - VMAX - VM - VMIN |Av (VM )| N MH = VOH -VIH VMIN 1 )+ = VMAX -VM (1+ |Av (VM )| |Av (VM )| Need to compute |Av (VM )|. 6.012 - Microelectronic Devices ...
University of Michigan, EECS 312
Excerpt: ... Lecture 5: CMOS Inverter EECS 312 Reading: 5.3.1, 5.3.2 EECS 312 1 Last Time Important metrics for digital circuits are: Delay (50% and 10-90% are key), power/energy, area (cost), reliability Functionality is assumed. Voltage transfer characteristics show inputoutput relationships VTCs describe the static behavior of a gate CMOS inverter is the basic building block we will start with EECS 312 2 Lecture Outline Introduce the CMOS inverter , DC analysis Switch-based model; very useful for both steady-state (DC) and transient analysis VTC properties and analysis Start looking at delay analysis EECS 312 3 Introduction to the CMOS Inverter EECS 312 4 The CMOS Inverter : A First Glance VDD Vin Vout CL EECS 312 5 CMOS Inverter Layout VDD PMOS In Out In Out Metal1 We're not doing layout in 312 but useful to recognize Polysilicon NMOS GND EECS 312 6 Switch Model of MOS Transistor |VGS| From V=IR, Ron 1/Id Ron ...