• 1 Pages

#### 15

University of Texas, CS 310

Excerpt: ... CS310H - Spring 2009 Lecture 15 - Exam review 2/25/09 I. Announcements - Exam Wednesday (2/25) You may bring: - 1 8 1/2" x 11" sheet of notes (handwritten) Topics: Everything we have covered up to and including Friday (2/20) - Transistors - Gates - Combinational logic design - Memory/storage - Sequential logic design - State machines - Numerical representations - Floating point Format - Some small number of multiple choice - Some number of short answer (a few sentences) - Some number of problems (design or otherwise) How to study? - Do practice problems! - If you can do the homework with your eyes closed, you shouldn't have any problems II. Review - Basic logic gates: NOT, NAND, NOR - Simple transistor switch model - Ways of representing combinational logic - Truth table, logic equation, gate representation - Combinational logic design - F = A'(C+BD) - State - D-latches, FFs - Memory - State machine rev ...

• 9 Pages

#### L14-ajc-SDS-6up

Berkeley, CS 61

Excerpt: ... inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures What are Machine Structures? Application (Netscape) Compiler Operating System (MacOS X) Lecture #14: Combinational Logic , Gates, and State 61C Instruction Set Architecture Software Hardware Assembler Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors 2006-07-20 Andy Carle CS 61C L14 Combinational Logic (1) A Carle, Summer 2006 UCB Coordination of many levels of abstraction Well investigate lower abstraction layers! (contract between HW & SW) CS 61C L14 Combinational Logic (2) A Carle, Summer 2006 UCB Below the Program High-level language program (in C) swap int v[], int k){ int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; C compiler Physical Hardware - PowerPC 750 } Assembly language program (for MIPS) swap: sll add lw lw sw sw jr \$2, \$5, 2 \$2, \$4,\$2 \$15, 0(\$2) \$16, 4(\$2) \$16, 0(\$2) \$15, 4(\$2) \$31 assembler Machine (object) code (for MIPS) 000000 00000 00101 0001000 ...

• 49 Pages

#### L14-ajc-SDS

Berkeley, CS 61

Excerpt: ... inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #14: Combinational Logic , Gates, and State 2006-07-20 Andy Carle CS 61C L14 Combinational Logic (1) A Carle, Summer 2006 UCB What are Machine Structures? Application (Netscape) Compiler Operating System (MacOS X) 61C Instruction Set Architecture Software Hardware Assembler Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors Coordination of many levels of abstraction Well investigate lower abstraction layers! (contract between HW & SW) CS 61C L14 Combinational Logic (2) A Carle, Summer 2006 UCB Below the Program High-level language program (in C) swap int v[], int k){ int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; C compiler } Assembly language program (for MIPS) swap: sll add lw lw sw sw jr \$2, \$5, 2 \$2, \$4,\$2 \$15, 0(\$2) \$16, 4(\$2) \$16, 0(\$2) \$15, 4(\$2) \$31 assembler Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 00 ...

• 3 Pages

#### L23

Berkeley, CS CS61A

Excerpt: ... CS61C Machine Structures Lecture 23 - Representing and Designing Combinational Logic Circuits 10/19/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C L23 Combinational Logic 1 Wawrzynek, Fall 2007 UCB Combinational Logic (CL) circuits yi = fi(x0 , . . . . , xn-1), where x, y are {0,1}. Our previous adder circuit is an example. Output is a function of the inputs only. Similar to a pure function in mathematics, y = f(x). (No way to store information. No side effects) If we change X, Y will change immediately (after a short delay). Very important: This is not like a function call! F is active and doing what it does continuously. It is not "invoked" or "called". 2 Wawrzynek, Fall 2007 UCB CS61C L23 Combinational Logic Truth Tables Uniquely Define CL Function 0 CS61C L23 Combinational Logic 3 Wawrzynek, Fall 2007 UCB What do we need to know about CL? How to design it: Given its definition breaking into mana ...

• 2 Pages

#### 355Outl_F08

Western Michigan, ECE 3550

• 35 Pages

#### L17-ac-cl

Berkeley, CS 61

Excerpt: ... inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures 2008-7-21 Lecture #17 Combinational Logic Albert Chae, Instructor CS61C L17 Combinational Logic (1) Chae, Summer 2008 UCB Review ISA is very important abstraction layer Contract between HW and SW Clocks control pulse of our circuits Voltages are analog, quantized to 0/1 Circuit delays are fact of life Two types of circuits: Stateless Combinational Logic (&,|,~) State circuits (e.g., registers) CS61C L17 Combinational Logic (2) Chae, Summer 2008 UCB Review State elements are used to: Build memories Control the flow of information between other state elements and combinational logic D-flip-flops used to build registers Clocks tell us when D-flip-flops change Setup and Hold times important Finite State Machines extremely useful CS61C L17 Combinational Logic (3) Chae, Summer 2008 UCB Review of Signal vocabulary T is the period Period is time from one rising edge to next Unit is seconds 1/T is the ...

• 1 Pages

#### hp-figs-B11

NYU, V 22

Excerpt: ... State element Combinational logic ...

• 1 Pages

#### F0503

WVU, CH 242

Excerpt: ... State element Combinational logic ...

• 1 Pages

#### F0503

Georgia Tech, CHAPTER 3055

Excerpt: ... State element Combinational logic ...

• 18 Pages

#### L17-ac-cl-2up

Berkeley, CS 61

Excerpt: ... inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures 2008-7-21 Lecture #17 Combinational Logic Albert Chae, Instructor CS61C L17 Combinational Logic (1) Chae, Summer 2008 UCB Review ISA is very important abstraction layer Contract between HW and SW Clocks control pulse of our circuits Voltages are analog, quantized to 0/1 Circuit delays are fact of life Two types of circuits: Stateless Combinational Logic (&,|,~) State circuits (e.g., registers) CS61C L17 Combinational Logic (2) Chae, Summer 2008 UCB Review State elements are used to: Build memories Control the ow of information between other state elements and combinational logic D-ip-ops used to build registers Clocks tell us when D-ip-ops change Setup and Hold times important Finite State Machines extremely useful CS61C L17 Combinational Logic (3) Chae, Summer 2008 UCB Review of Signal vocabulary T is the period Period is time from one rising ed ...

• 22 Pages

#### 2008SpCS61C-L23-ddg-BLOCKS

Berkeley, CS 61c

Excerpt: ... UC Berkeley CS61C : Machine Structures Lecture 23 Combinational Logic Blocks 2008-03-19 Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c www.cs.berkeley.edu/~ddgarcia Long-Distance Wi-Fi The difficulty of providing WiFi to remote municipalities may soon be over. Intel has figured out how to deliver signals at a low cost > 60 miles away. Since "you can't lay cable" www.technologyreview.com/Infotech/20432/ CS61C L23 Combinational Logic Blocks (1) Garcia, Spring 2008 UCB Review Use this table and techniques we learned to transform from 1 to another CS61C L23 Combinational Logic Blocks (2) Garcia, Spring 2008 UCB Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor CS61C L23 Combinational Logic Blocks (3) Garcia, Spring 2008 UCB Data Multiplexor (here 2-to-1, n-bit-wide) "mux" CS61C L23 Combinational Logic Blocks (4) Garcia, Spring 2008 UCB N instances of 1-bit-wide mux How many rows in TT? CS61C L23 Combinational Logic Blocks ...

• 4 Pages

#### 2008SpCS61C-L23-ddg-BLOCKS-6up

Berkeley, CS 61c

Excerpt: ... UC Berkeley CS61C : Machine Structures Lecture 23 Combinational Logic Blocks 2008-03-19 Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c Review Use this table and techniques we learned to transform from 1 to another www.cs.berkeley.edu/~ddgarcia Long-Distance Wi-Fi The difficulty of providing WiFi to remote municipalities may soon be over. Intel has figured out how to deliver signals at a low cost > 60 miles away. Since "you can't lay cable" www.technologyreview.com/Infotech/20432/ CS61C L23 Combinational Logic Blocks (1) Garcia, Spring 2008 UCB CS61C L23 Combinational Logic Blocks (2) Garcia, Spring 2008 UCB Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor Data Multiplexor (here 2-to-1, n-bit-wide) "mux" CS61C L23 Combinational Logic Blocks (3) Garcia, Spring 2008 UCB CS61C L23 Combinational Logic Blocks (4) Garcia, Spring 2008 UCB N instances of 1-bit-wide mux How many rows in TT? How do we build a 1-bit-wide mux? CS61C L23 ...

• 4 Pages

#### ee261_lecture_26

Montana, EE 261

Excerpt: ... EE 261 Introduction to Logic Circuits Lecture #26 Agenda 1. Combinational Logic Design Flow 2. Exam #2 Announcements : Wednesday (11/5) 1. Exam #2 Friday (11/7) EE 261 Introduction to Logic Circuits Fall 2008 Lecture #26 Page 1 Combinational Logic Design Flow Design Flow - We now have all the pieces for a complete design process 1) Design Specifications 2) Truth Table 3) Describe using SOP/POS/Minterm/Maxterm 4) Logic Minimization 5) Logic Manipulation 6) Hazard Prevention : description of what we want to do : listing the logical operation of the system : creating the logic expression : K-maps : Convert to desired technology (NAND/NAND, .) EE 261 Introduction to Logic Circuits Fall 2008 Lecture #26 Page 2 Exam #2 Review Details - 50 minutes, closed book, closed notes - you can use a 1-page note sheet (8.5" x 11"), front & back - you can use your Boolean Algebra Cheat Sheet EE 261 Introduction to Logic Circuits Fall 2008 Lecture #26 Page 3 Exam #2 Review Topics Boolean Algebra ...

• 2 Pages

#### ee261_lecture_26

Montana, EE 261

Excerpt: ... EE 261 Introduction to Logic Circuits Lecture #26 Agenda 1. Combinational Logic Design Flow 2. Exam #2 Announcements : Wednesday (11/5) 1. Exam #2 Friday (11/7) EE 261 Introduction to Logic Circuits Fall 2008 Lecture #26 Page 1 Combinational Logic Design Flow Design Flow - We now have all the pieces for a complete design process 1) Design Specifications 2) Truth Table 3) Describe using SOP/POS/Minterm/Maxterm 4) Logic Minimization 5) Logic Manipulation 6) Hazard Prevention : description of what we want to do : listing the logical operation of the system : creating the logic expression : K-maps : Convert to desired technology (NAND/NAND, ) EE 261 Introduction to Logic Circuits Fall 2008 Lecture #26 Page 2 1 Exam #2 Review Details - 50 minutes, closed book, closed notes - you can use a 1-page note sheet (8.5" x 11"), front & back - you can use your Boolean Algebra Cheat Sheet EE 261 Introduction to Logic Circuits Fall 2008 Lecture #26 Page 3 Exam #2 Review To ...

• 4 Pages

#### ee414_lecture_17

Montana, EE 414

Excerpt: ... EE 414 Introduction to VLSI Design Lecture #17 Agenda 1. Combinational Logic - graph theory - AOI / OAI - T-gates Announcements (Thursday, 11/13/08) 1. Read 7.4 - 7.5 2. HW #9 CMOS Combinational Logic Complex CMOS Logic Circuits - we can implement any logic functions using NANDs, NORs, and INVs. - however, the timing and area of the standard SOP approach can be improved further by creating the entire logic function in one circuit. - we can design a complex function by: 1) Creating the NMOS pull-down network of F where: - an OR is performed using parallel connected NMOSs - an AND is performed using series connected NMOSs NOTE: this is an NMOS pull-down network so the logic function must be in an F form (or a dual of F). these rules can be used in a nested configuration to form any logic function NOTE: 2) Creating the PMOS pull-up network to be the complement of the pull-down network EE 414 Introduction to VLSI Design Fall 2008 Lecture #17 Page 1 EE 414 Introduction ...

• 15 Pages

#### cl1

Washington, CS 467

Excerpt: ... Lecture Notes CSE 467 Advanced Digital Design Combinational logic Logic gates Regular structures for two-level logic Limits of two-level regular structures Multi-level logic Mapping combinational logic to programmable logic devices CSE 467 2 Combinational Logic 1 Logic gates Commonly use NANDs, NORs, AOIs, OAIs, sum-of-products easy to build in common IC technologies limited number of inputs Technology mapping process of mapping Boolean equations into the available gate types with their fan-in and fan-out restrictions two-level sum-of-products or multi-level logic implementation speed optimization (depth, fanout) Tends to be highly irregular ok for IC design where there is full control of what goes in the package not acceptable for design with off-the-shelf pre-packaged parts too much design time, not easy to change (upgrade, fix) Regular structures easy to interconnect tradeoff efficiency for ease of design and testing economies of scale CSE 467 2 Combinational Logic 2 ...

• 2 Pages

#### Week8

Cincinnati, CAS 483

Excerpt: ... This Week 1. Hand in Lab #3, Assign #4 and exam makeup 2. Lab #4 3. Multi-cycle datapath and control Computer Organization and Design Patterson & Hennessy Chapter 5.4 Single Cycle Datapath and Control Clocking All computers contain both Combinational Logic and State Elements Combinational Logic 's output vary directly from their inputs o Example An Arithmetic Logic Unit (ALU) State Elements hold their values until updated o Example A "D" type flip-flop State Elements are modified on the leading edge of a regular clock Edge-triggered Methodology Combinational Logic is feed from and feeds back into State Elements Once Combinational Logic achieves a steady state, the state is captured and fead back to the Combinational Logic Single Cycle Implementation Each instruction is executed in a single clock cycle Requires duplicating hardware as all operation have to happen at once Requires separate data and instruction memory Cycle time has to be longer than propigation delay of most complex in ...

• 2 Pages

#### hw2

UC Riverside, CS 120

Excerpt: ... Homework 2 UCR EE/CS120B: Introduction to Embedded Systems Winter Quarter 2004, Lecturer Brian Grattan Due Wednesday, January 21 at the beginning of class. 1. Design a FSM (state diagram) for the following problem definition: inputs: I1 output: OUT If I1 has been zero for two consecutive cycles OR if it has been one for three consecutive clock cycles set OUT to 1 for one clock cycle then begin counting again. OUT is 0 at all other times. The clock cycle that OUT is 1 is counted. That means if you start with a long string of zero's on I1 then OUT will 001010101. and if you get a long string of one's then OUT will be 0001001001001. You should be able to do this in less than 8 states. Make this a Moore machine (output depends on state only). 2. Convert the FSM in Problem #1 to a state table. 3. Convert the state table in Problem #2 into combinational logic (and's or's etc.) 4. Design a circuit that will compute X! (X factorial, look it u ...

• 1 Pages

#### Quiz3Solutions

UC Riverside, CS 120

Excerpt: ... Quiz 3 CS/EE120B Lecturer: Brian Grattan Do not use any notes or calculators Feb. 11, 2005 Name:_Solutions_ UCR ID:_ 1. (4 points) Rank the following types of memory for their memory retention. '1' being the memory that holds it's contents for the longest, and '4' for the memory that loses it's contents the fastest. _1_ OTP (One Time Programmable) _4_ DRAM _2_ Flash _3_ SRAM 2. (2 points) How does someone erase EPROM? (Note: this is not EEPROM) Shine Ultraviolet light on it for anywhere from 5 to 30 minutes. 3. (1 point) Which type of memory takes less space when implemented on a chip, SRAM or DRAM? DRAM 4. (1 point) When using a ROM to implement combinational logic , the address lines are used as what? a) the inputs b) the outputs c) instructions d) A way to describe the logic 5. (3 points) Create a memory by making a table, and show every bit stored inside of it, for a memory that could be used to replace this combinational logic : A(0) A(1) A(2) Address X Value 0 0 0 0 0 1 1 ...

• 1 Pages

#### verilog_problem

UCF, EEL 4768

Excerpt: ... The questions are adopted from the book: Verilog Styles for Synthesis of Digital Systems by D. Smith and P. Franzon, Prentice Hall, 2000. 1. What signals, if any, result in latches in the following Verilog code segment? Recode the design to remove the latches. In other words, the code is trying to capture some combinational logic . always@ (foo or fred) if(foo = = 2`b0) bar = fred; 2. What signals, if any, result in latches in the following Verilog code segment? Recode the design to remove the latches. In other words, the code is trying to capture some combinational logic . always@ (foo or hal or tron) begin case (foo) 2`b00: fred = hal; 2`b01: fred = tron; 2`b10: mike = hal; 2`b11: mike = tron; endcase end 3. Redesign the counter example in the lecture notes to count up instead of a countdown. Design it so that it halts when the count value reaches 4`b1111 and replace the zero flag with a ones flag, which is set when 4`b1111 is reached. ...

• #### Lecture11-CombLogic-6up

Berkeley, EECS 141

Excerpt: ... Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic EECS 141 F01 Lecture 11 Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-CMOS Digital Integrated Circuits Combinational Logic Prentice Hall 2000 Digital Integrated Circuits Combinational Logic Prentice Hall 2000 Administrivia G Combinational vs. Sequential Logic Logic Circuit In Out Logic Circuit Out Review session on Wednesday 7:309pm 22 Warren Hall In No labs this week G No new homework this week G (a) Combinational Output = f(In) Digital Integrated Circuits Combinational Logic Prentice Hall 2000 Digital Integrated Circuits State (b) Sequential Output = f(In, Previous In) Combinational Logic Prentice Hall 2000 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once ...

• 5 Pages

#### lecture2

Arizona, ECE 274

Excerpt: ... ECE 274 - Digital Logic Lecture 2 Digital Design Circuit Types: Combinational vs. Sequential Lecture 2 Transistors, Switches, CMOS Basic Logic Gates Boolean Equations Truth Table: w/o time or previous values 1 2 Digital Design Circuit Components: Historical Perspective Digital Design Transistors as Switches: Binary Switch x = 0 x = 1 (a) Two states of a switch S x The evolution of switches: Relays (1930s), vacuum tubes (1940s), discrete transistors (1950s), and integrated circuits (ICs) containing transistors (1960s-present). IC's originally held about ten transistors; now they can hold more than a billion. (b) Symbol for a switch 3 4 Digital Design Transistors as Switches: Light controlled be a Switch Digital Design Transistors as Switches: Basic Functions (AND/OR) S Battery x L Light (a) Simple connection to a battery S Power supply x L (b) Using a ground connection as the return path 5 6 Digital Design Combinational Logic Design Digital Design Combinational Logic Design CMOS transis ...