Berkeley, CS 61
Excerpt: ... inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures What are Machine Structures? Application (Netscape) Compiler Operating System (MacOS X) Lecture #14: Combinational Logic , Gates, and State 61C Instruction Set Architecture Software Hardware Assembler Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors 2006-07-20 Andy Carle CS 61C L14 Combinational Logic (1) A Carle, Summer 2006 UCB Coordination of many levels of abstraction Well investigate lower abstraction layers! (contract between HW & SW) CS 61C L14 Combinational Logic (2) A Carle, Summer 2006 UCB Below the Program High-level language program (in C) swap int v[], int k){ int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; C compiler Physical Hardware - PowerPC 750 } Assembly language program (for MIPS) swap: sll add lw lw sw sw jr $2, $5, 2 $2, $4,$2 $15, 0($2) $16, 4($2) $16, 0($2) $15, 4($2) $31 assembler Machine (object) code (for MIPS) 000000 00000 00101 0001000 ...
Berkeley, CS CS61A
Excerpt: ... CS61C Machine Structures Lecture 23 - Representing and Designing Combinational Logic Circuits 10/19/2007 John Wawrzynek (www.cs.berkeley.edu/~johnw) www-inst.eecs.berkeley.edu/~cs61c/ CS61C L23 Combinational Logic 1 Wawrzynek, Fall 2007 UCB Combinational Logic (CL) circuits yi = fi(x0 , . . . . , xn-1), where x, y are {0,1}. Our previous adder circuit is an example. Output is a function of the inputs only. Similar to a pure function in mathematics, y = f(x). (No way to store information. No side effects) If we change X, Y will change immediately (after a short delay). Very important: This is not like a function call! F is active and doing what it does continuously. It is not "invoked" or "called". 2 Wawrzynek, Fall 2007 UCB CS61C L23 Combinational Logic Truth Tables Uniquely Define CL Function 0 CS61C L23 Combinational Logic 3 Wawrzynek, Fall 2007 UCB What do we need to know about CL? How to design it: Given its definition breaking into mana ...
Berkeley, CS 61
Excerpt: ... inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures 2008-7-21 Lecture #17 Combinational Logic Albert Chae, Instructor CS61C L17 Combinational Logic (1) Chae, Summer 2008 UCB Review ISA is very important abstraction layer Contract between HW and SW Clocks control pulse of our circuits Voltages are analog, quantized to 0/1 Circuit delays are fact of life Two types of circuits: Stateless Combinational Logic (&,|,~) State circuits (e.g., registers) CS61C L17 Combinational Logic (2) Chae, Summer 2008 UCB Review State elements are used to: Build memories Control the flow of information between other state elements and combinational logic D-flip-flops used to build registers Clocks tell us when D-flip-flops change Setup and Hold times important Finite State Machines extremely useful CS61C L17 Combinational Logic (3) Chae, Summer 2008 UCB Review of Signal vocabulary T is the period Period is time from one rising edge to next Unit is seconds 1/T is the ...
Berkeley, CS 61c
Excerpt: ... UC Berkeley CS61C : Machine Structures Lecture 23 Combinational Logic Blocks 2008-03-19 Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c www.cs.berkeley.edu/~ddgarcia Long-Distance Wi-Fi The difficulty of providing WiFi to remote municipalities may soon be over. Intel has figured out how to deliver signals at a low cost > 60 miles away. Since "you can't lay cable" www.technologyreview.com/Infotech/20432/ CS61C L23 Combinational Logic Blocks (1) Garcia, Spring 2008 UCB Review Use this table and techniques we learned to transform from 1 to another CS61C L23 Combinational Logic Blocks (2) Garcia, Spring 2008 UCB Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor CS61C L23 Combinational Logic Blocks (3) Garcia, Spring 2008 UCB Data Multiplexor (here 2-to-1, n-bit-wide) "mux" CS61C L23 Combinational Logic Blocks (4) Garcia, Spring 2008 UCB N instances of 1-bit-wide mux How many rows in TT? CS61C L23 Combinational Logic Blocks ...
Berkeley, CS 61c
Excerpt: ... UC Berkeley CS61C : Machine Structures Lecture 23 Combinational Logic Blocks 2008-03-19 Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c Review Use this table and techniques we learned to transform from 1 to another www.cs.berkeley.edu/~ddgarcia Long-Distance Wi-Fi The difficulty of providing WiFi to remote municipalities may soon be over. Intel has figured out how to deliver signals at a low cost > 60 miles away. Since "you can't lay cable" www.technologyreview.com/Infotech/20432/ CS61C L23 Combinational Logic Blocks (1) Garcia, Spring 2008 UCB CS61C L23 Combinational Logic Blocks (2) Garcia, Spring 2008 UCB Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor Data Multiplexor (here 2-to-1, n-bit-wide) "mux" CS61C L23 Combinational Logic Blocks (3) Garcia, Spring 2008 UCB CS61C L23 Combinational Logic Blocks (4) Garcia, Spring 2008 UCB N instances of 1-bit-wide mux How many rows in TT? How do we build a 1-bit-wide mux? CS61C L23 ...
Cincinnati, CAS 483
Excerpt: ... This Week 1. Hand in Lab #3, Assign #4 and exam makeup 2. Lab #4 3. Multi-cycle datapath and control Computer Organization and Design Patterson & Hennessy Chapter 5.4 Single Cycle Datapath and Control Clocking All computers contain both Combinational Logic and State Elements Combinational Logic 's output vary directly from their inputs o Example An Arithmetic Logic Unit (ALU) State Elements hold their values until updated o Example A "D" type flip-flop State Elements are modified on the leading edge of a regular clock Edge-triggered Methodology Combinational Logic is feed from and feeds back into State Elements Once Combinational Logic achieves a steady state, the state is captured and fead back to the Combinational Logic Single Cycle Implementation Each instruction is executed in a single clock cycle Requires duplicating hardware as all operation have to happen at once Requires separate data and instruction memory Cycle time has to be longer than propigation delay of most complex in ...
Berkeley, EECS 141
Excerpt: ... Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic EECS 141 F01 Lecture 11 Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-CMOS Digital Integrated Circuits Combinational Logic Prentice Hall 2000 Digital Integrated Circuits Combinational Logic Prentice Hall 2000 Administrivia G Combinational vs. Sequential Logic Logic Circuit In Out Logic Circuit Out Review session on Wednesday 7:309pm 22 Warren Hall In No labs this week G No new homework this week G (a) Combinational Output = f(In) Digital Integrated Circuits Combinational Logic Prentice Hall 2000 Digital Integrated Circuits State (b) Sequential Output = f(In, Previous In) Combinational Logic Prentice Hall 2000 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once ...
Arizona, ECE 274
Excerpt: ... ECE 274 - Digital Logic Lecture 2 Digital Design Circuit Types: Combinational vs. Sequential Lecture 2 Transistors, Switches, CMOS Basic Logic Gates Boolean Equations Truth Table: w/o time or previous values 1 2 Digital Design Circuit Components: Historical Perspective Digital Design Transistors as Switches: Binary Switch x = 0 x = 1 (a) Two states of a switch S x The evolution of switches: Relays (1930s), vacuum tubes (1940s), discrete transistors (1950s), and integrated circuits (ICs) containing transistors (1960s-present). IC's originally held about ten transistors; now they can hold more than a billion. (b) Symbol for a switch 3 4 Digital Design Transistors as Switches: Light controlled be a Switch Digital Design Transistors as Switches: Basic Functions (AND/OR) S Battery x L Light (a) Simple connection to a battery S Power supply x L (b) Using a ground connection as the return path 5 6 Digital Design Combinational Logic Design Digital Design Combinational Logic Design CMOS transis ...