UMass (Amherst), ECE 221

Excerpt: ... ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip flop s ENGIN112 L20: Sequential Circuits: Flip flop s October 20, 2003 Overview Latches respond to trigger levels on control inputs Example: If G = 1, input reflected at output Difficult to precisely time when to store data with latches Flip flips store data on a rising or falling trigger edge. Example: control input transitions from 0 -> 1, data input appears at output Data remains stable in the flip flop until until next rising edge. Different types of flip flop s serve different functions Flip flop s can be defined with characteristic functions. ENGIN112 L20: Sequential Circuits: Flip flop s October 20, 2003 D Latch D C Q S S Q R D 0 1 X C R S R 0 0 0 1 1 0 1 1 X X C 1 1 0 Q 0 1 Q0 Q 1 0 Q0 1 1 1 1 0 Q Q0 0 1 1 Q0 Q Q0 1 0 1 Q0 Store Reset Set Disallowed Store When C is high, D passes from input to output (Q) ENGIN112 L20: Sequential Circuits: F ...

New Hampshire, ECE 543

Excerpt: ... EE543 Introduction to Digital Systems LABORATORY #6 Flip-flop Elements OBJECTIVE: The objective of this laboratory is to study the behavior of flip-flops and to use them to construct a simple sequential circuit. EQUIPMENT REQUIRED: Global Specialti ...

New Hampshire, ECE 543

Excerpt: ... 4 CLOCK Q1 Q2 Q3 Q4 For Prelab complete the following: a. wiring diagrams for each circuit. b. a wire list (commonly called a NET LIST) for each circuit. NOTE: You do not have Toggle Flip Flop s and must construct them from the JK Flip-Flops that you are given. Also do not forget to address the Clear lines on the JK Flip-Flops LAB: Created by Richard A. Messner: January 1989 Last Update: 6/15/2009, 6/15/2009 EE543 Introduction to Digital Systems 1. Assemble and test each flip-flop circuit which you implemented. Test a JK master-slave edgetriggered flop-flop on one of the 74107 IC packages. Using a pulse switch on the IDL-800 Digital Lab as the clock input, verify the behavior tables associated with each flip-flop. Draw timing diagrams based upon your actual observations showing all the modes of operation of each flip-flop. 2. Assemble and test the binary ripple counter. Draw a timing diagram showing the clock input and all four flip-flop outputs. Use a pulse switch for the clock input initially, then ...

Washington University in St. Louis, CSE 260

Excerpt: ... CSE 260 Digital Computers: Organization and Logical Design Homework 3b Solutions Jon Turner 1. (10 points) Consider the SR latch shown on page 3-18 of the lecture notes. Assume the NOR gates each have a delay of exactly 1 ns and suppose that at time 0, the latch is cleared (Q=0) and the S and R inputs are both low. Then at time 10 ns, S and R both go high and at time 20 ns, they both go low. Draw a timing diagram showing how the outputs change in response to this. S R Q Q -1- 2. (10 points) The diagram shown below shows a negative edge-triggered D flip flop and an SR master-slave flip flop with labels added to some intermediate signals. Complete the timing diagram shown below, assuming that every gate has a delay equal to half of one time unit. Explain how the behavior of the SR flip flop is similar to the behavior of the D flip flop and how it is different. D A Q1 C S R C 0 C D A Q1 S R B Q2 4 8 12 16 20 24 28 B Q2 The behavior of the two flip flop s is similar in the sense that the outputs ...

Harvard, ES 50

Excerpt: ... orage. In subsequent experiments, we shall see many applications of bistable circuits, but for now, we will concentrate on their basic properties. Flip Flop s Part 1: The RS flip-flop The simplest bistable circuit is the RS flip-flop. Using a couple of NAND gates (74HCT00), connect the circuit, as shown in figure 3-1. Figure 3-1 Connect the S (set) and R (reset) inputs, noting that these are active-low inputs, to the normally high terminals of the pulser switches. Connect the complementary outputs Q and Q to monitor lamps. Try various combinations of set and reset until you convince yourself of the following truth table: Rev. November 2000 Engineering Sciences 50 Lab 3 - 4 The RS flip-flop R S 0 1 0 1 Q 0 1 Q 0 0 1 1 Not Defined 1 0 No Change The Q output can be made high or low by applying a momentary low pulse to either the S or R input respectively. The pulse must go from a 1 to 0 and back to 1 (1 0 1) . Why doesn't the opposite sequence, 0 1 0 work? Note that once the RS flip-flop is in ...

Christopher Newport University, CPEN 214

Excerpt: ... The second exam will cover chapters 4 and 5 You should focus on the following: Combinational logic circuit design at the block level (FA and HA). There will not be any analysis of combinational circuits. Function implementation using decoders an ...

UMBC, CS 313

Excerpt: ... 1 (t)s0 (t) q0 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t) q1 (t+1) = r(t)s1 (t)s0 (t) + r(t)s1 (t)s0 (t) Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring A-64 Appendix A: Digital Logic Logic Design for Mod-4 Counter RESET CLK DQ s1 Q q1 DQ s0 Q q0 Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring Mod 4 Counter Timing Clock Reset s1 s0 q1 q0 Outputs 00 only when reset is high UMBC, CMSC313, Richard Chang <chang@umbc.edu> Mealy vs Moore Finite State Machines Mealy: output depends on input and state bits input Combinational Logic output Flip Flop s Moore: output depends only on state bits input Combinational Logic Flip Flop s Combinational Logic output UMBC, CMSC313, Richard Chang <chang@umbc.edu> CMSC 313, Computer Organization & Assembly Language Programming Fall 2004 Section 0101 DigSim Assignment 2: A Finite State Machine Due: Tuesday November 30, 2004 Objective: The objecti ...

UMBC, CS 313

Excerpt: ... Edge-triggered Flip Flop s Introduction to Finite State Machines UMBC, CMSC313, Richard Chang <chang@umbc.edu> ...

Simon Fraser, ENSC 150

Excerpt: ... 1/4 ENSC150 Lecture 20 Agenda Other Flip Flop Types JK Flip Flop T Flip Flop Lecture 20 Atousa Hajshirmohammadi, SFU JK Flip Flop In addition to its clock pulse, this ip op has two inputs; J and K 2/4 The J input acts as the set and the K input acts as the reset input. J 0 The characteristic table of JK Flip Flop 0 1 1 the inputs and the previous state: K 0 1 0 1 Q(t + 1) Q(t) 0 1 Q(t) characteristic equation, is the equation that relates the next state to Lecture 20 Atousa Hajshirmohammadi, SFU Example Implement a JK ip op using a D ip op. 3/4 Lecture 20 Atousa Hajshirmohammadi, SFU T Flip Flop The T (Toggle) ip op is equivalent to the JK ip op, with J and K connected together: 4/4 Characteristic Table: Implement the T ip op using the D ip op. Lecture 20 Atousa Hajshirmohammadi, SFU ...

Washington University in St. Louis, CSE 260

Excerpt: ... CSE 260 Digital Computers: Organization and Logical Design Homework 3b Solutions Jon Turner Due 2/21/2008 1. (10 points) Consider the SR latch shown on page 3-18 of the lecture notes. Assume the NOR gates each have a delay of exactly 1 ns and suppose that at time 0, the latch is cleared (Q=0) and the S and R inputs are both low. Then at time 10 ns, S and R both go high and at time 20 ns, they both go low. Draw a timing diagram showing how the outputs change in response to this. -1- 2. (10 points) The diagram shown below shows a negative edge-triggered D flip flop and an SR master-slave flip flop with labels added to some intermediate signals. Complete the timing diagram shown below, assuming that every gate has a delay equal to half of one time unit. Explain how the behavior of the SR flip flop is similar to the behavior of the D flip flop and how it is different. D A Q1 C S R C 0 C D A Q1 S R B Q2 4 8 12 16 20 24 28 B Q2 -2- ...

Washington University in St. Louis, CSE 260

Excerpt: ... CSE 260 Digital Computers: Organization and Logical Design Problem Set 8 Jon Turner 1. Write a VHDL module that defines a sequential circuit implementing each of the state diagrams in the posted solutions for problem 8 of Problem Set 9. Write these VHDL modules in the style shown on page 8.3 of the lecture notes. That is, use explicit binary state variables, rather than symbolic variables. 2. Write a VHDL module that defines a sequential circuit implementing each of the state diagrams in problem 9 of Problem Set 9. Write these VHDL modules in the style shown on page 8.4 of the lecture notes. That is, use symbolic state variables, with state names, red, green, blue and yellow in place of s1s0 = 00, 01, 10 or 11. 3. A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. One simple design for this circuit uses four flip flop s connected in a ring, with an inverter between the last flip flop a ...

Allan Hancock College, ELEC 1700

Excerpt: ... ELEC1700/6700 LECTURE 8 Using flip flop s to build sequential machines References Dueck pages 275 to 329, 457 to 497 Mano pages 187 to 199. Floyd pages 390 to 398. Tocci pages 196 to 210, 237 to 238. Yarbrough pages 322 to 329, 339 to 348. 2 The story so far We have seen the data latch - a device that can "store" one bit of information. A latch is "enabled" by an active level. A problem of "transparency" was identified, where the outputs of a latch changed as soon as the inputs changed, rather than waiting for the clock. The master-slave flip flop was developed to avoid the transparency. The master slave was "clocked" by consecutive level triggers (also called "pulse triggered"). An even better solution is to use edge triggering. 3 Now we will look at: Preset and clear (asynchronous) inputs; Formats for describing operation of sequential circuits: timing diagrams; state transition tables; state transition diagrams; Flip flop excitation tables. Analysing and synthesising state machines. 4 Preset and ...