parasitic_extraction

Berkeley, EE 141
Excerpt: ... How to extract parasitic capacitance ? Please refer to lab3 tutorial extraction section. To extract the parasitic capacitance , click on the "Set Switches" and select Extract_parasitic_caps as shown below. That is the only difference from the tutorial in lab 3. Note that capacitance under 2fF is ignored. Then just follow the lab 3 tutorial on how to get the netlist. ...

Exp3.supplement

Berkeley, EE 105
Excerpt: ... Supplemental Part for Lab 3 Find the parasitic capacitance in our metal runner 1. Use signal generator to insert a 1Vp-p, 1KHz sinusoidal waveform into PIN#13 of Lab Chip 1. Use oscilloscope to observe the waveforms at PIN#13 (input) and PIN#15 (output). Please note that the references of the oscilloscope probes and the signal generator should all be connected to PIN#14 (VSS). Write down the magnitudes of the input and output waveforms and the phase shift (if any) under this frequency. 2. Keep increasing the input frequency and observe the waveforms. When dose the magnitude of output become 0.707 times that of the input? What is the phase shift under this frequency? Why do we choose the value 0.707 here? 3. Keep increasing the input frequency till you reach the maximum frequency the generator could generate. Carefully record the values of magnitude and phase shift around the break frequency . Sketch the Bode plot by using the values of magnitude and phase shift you just recorded. 4. By using the ...

Exam3Info

Georgia Tech, ECE 4430
Excerpt: ... licon dioxide, FOX, TOX, IOX, polysilicon, metal, etc. Be able to find the parasitic capacitance from a MOSFET or BJT terminal to ground Be able to find the bulk resistance between the actual MOSFET or BJT to its external terminals Be able to identify a circuit from a layout How a passive component is made from MOS or BJT technologies Be able to identify the cross-section of a passive component Know the typical values and accuracies of passive components Purpose and definition of design rules Be able to connect the physical aspects of the active and passive components to their performance. The examples in Lectures 210 and 215 are a good study guide for this exam. The exam will be proctored by Susanta Sengupta because Dr. Allen will not be in town on the 16th. Office hours for Dr. Allen are Monday 12-1pm and Wednesday 11-12 noon. ...

lecture4

UC Riverside, CS 168
Excerpt: ... CS168 Lecture Four ASIC LIBRARY DESIGN Home work Smith: 3.1, 3.4, 3.14 Due : Next Mon. Feb.10, 6:10pm Midterm: Feb. 10, 6:10pm - 7:40 pm 1 Transistors as Resistors Propagation delay: 0.5 of input to 0.35 (falling, tpdf) and 0.65 (rising, tpdr) M1 start from off saturation linear Pull down resistance: Rpd Pull up resistance : Rpu 2 3 4 5 6 7 8 Parasitic capacitance measurement (a) All devices in this circuit include parasitic capacitance (b) This circuit uses linear capacitors to model the parasitic capacitance of m9/10. The load formed by the inverter (m5 and m6) is modeled by a 0.0335pF capacitor (c2) The parasitic capacitance due to the overlap of the gates of m3 and m4 with their source, drain, and bulk terminals is modeled by a 0.01pF capacitor (c3) The effect of the parasitic capacitance at the drain terminals of m3 and m4 is modeled by a 0.025pF capacitor (c4) (c) Comparison of (a) and (b). The delay (1.22-1.135=0.085ns) is equal to t PDf for t ...

tx_lab

Washington, EE 400
Excerpt: ... FM Transmitter Lab EE400E Undergraduate Radio Lab Professor: Brian Otis TA: Dan Yeager Spring 2009 Demos 4/24 This is a group of 2 assignment. Please turn in a typed hardcopy with your design decisions. Procedure The first two prelabs have prepared you to design and fabricate an FM transmitter. Specifically, you should be comfortable with biasing the BJT in the Colpitts oscillator and setting the frequency of oscillation through an LC tank circuit. The first step will be to design circuit values, similar to prelab 2. The second step is to plan a layout. This is necessary because RF circuits are sensitive to long wires (which act as inductors or even antennas), and parasitic capacitance s (solderless breadboards are notorious for high parasitic capacitance s). The third step is to solder the components to the breadboard and test out the transmitter. 1. Design The varactor we will use is the BB208. Please look up the datasheet and find Cmax and Cmin. From this, compute L, assuming 30pF of additional tank capa ...

EE 508 Lect 39 Fall 2008

Iowa State, EE 508
Excerpt: ... l input and output OTAs Parasitic Capacitance s and Floating Nodes R2 R3 CP1 CP2 C1 R1 C2 VOUT CP3 VIN CP4 1 1 2 OUT P2 P3 2 P4 There is invariably a parasitic capacitance associated with every terminal of every element in a filter These parasitic capacitance s can be significant in integrated filters These can be combined into a single parasitic capacitance on each node IN P1 Parasitic Capacitance s and Floating Nodes R2 R3 CP1 CP2 C1 R1 C2 VOUT CP3 VIN CP4 A floating node is a node that is not connected to either a zeroimpedance element or across a null-port Floating nodes are generally avoided in integrated filters because the parasitic capacitance s on the floating nodes usually degrades filter performance and often increases the order of the filter Some filter architectures inherently have no floating nodes, specifically, most of the basic integrator-based filters have no floating nodes Parasitic Capacitance s and Floating Nodes Parasitic Capacitance s and Floating Nodes No floating nodes ! Sign ...

exam1.obj

Valparaiso, ECE 429
Excerpt: ... ECE 429 VLSI Design Sectional Objectives Section I - Rabaey Chapters 1-3, Appendix A After reading and studying Chapters 1 through 3 and Appendix A you should be able to: create a minimized CMOS circuit schematic given a boolean expression. g ...

EEE244HW4S07

CSU Sacramento, EEE 244
Excerpt: ... EEE 244 Homework 4 Due Wednesday, 4/11/07 The Problem Parasitic Capacitance between circuit boards and ground planes can be a troublesome source of power consumption and/or increased delay time in circuit operations. The figure above shows the surface charge density distribution (rhos) in nC/cm2 on a 4 cm x 6 cm ground plane located just below a circuit board in an instrument enclosure. The ground plane is at a potential of 5 V with respect to the circuit board, and the parasitic capacitance in this case can be found from C = Q/V where Q is the total charge on the ground plane. You are asked to use the "Cell by Cell" approach to numerical surface integration, which was illustrated using the Trapezoidal rule in class. Write a MATLAB m-file program to find Q = (rhos)ds and calculate the parasitic capacitance , C, for this circuit/ground s plane arrangement, using Simpson's 1/3 rule. Then write one that uses a combination of Simpson's 1/3 and Simpson's 3/8 rules. Include appropriate Romberg error correction ...

test2_study_guide

Mississippi State, ECE 4263
Excerpt: ... ECE 4263 (VLSI) Test 2 Study Guide The test is closed book/closed notes. a. Be able to size a static CMOS gate for equal TPLH, TPHL delay. b. Be able to give the definitions of TPLH, TPHL for a gate, and specify a method for measuring these values. c. Understand the definition of contamination (shortest-path) delay and how to measure it. d. Be able to compute the RC Elmore Delay for a complex static MOS gate using drain/source parasitic capacitance s and gate load capacitance (this means that you understand the RC model of a static CMOS gate) e. Be able to explain how to determine from simulation a method for determining pullup/pulldown inverter ratios that optimize the average delay through a chain of inverters. f. Be able to use the simple K model to model gate delay (delay = no-load delay + K*C load) g. Be able to explain and use the 2D- lookup table for propagation delay through a chain of gates. h. Be able to use/explain a greedy gate sizing algorithm for improving delay for a chain of gates. i. Be ...

Lecture33

University of Florida , EEL 5225
Excerpt: ... EEL5225: Principles of MEMS Transducers (Fall 2003) Instructor: Dr. Hui-Kai Xie Accelerometers Capacitive Position Sensing Circuits for Capacitive Sensing ADI Capacitive Accelerometers Other MEMS Accelerometers Reading: Senturia, Chapter 19, p.497-530 Note: Most of figures in this lecture are copied from Senturia, Microsystem Design, Chapter 19. EEL5225: Principles of MEMS Transducers (Fall 2003) Lecture 33 by 11/24/2003 1 H.K. Xie 11/24/2003 Capacitive Position Sensing Capacitive Position Sensing MEMS Capacitive Sensors: High impedance Small sensing capacitance Very small signal Parasitic capacitance Noise 11/24/2003 EEL5225: Principles of MEMS Transducers (Fall 2003) 2 Differential Capacitive Sensing V0 = Vs + = C1 ( 2Vs ) C1 + C2 C1 C2 Vs C1 + C2 Differential Capacitive Sensing First order cancellation of many effects Temperature variations Common mode rejection 11/24/2003 EEL5225: Principles of MEMS Transducers (Fall 2003) 3 Circuits for Capacitive Sensing Interf ...

clk_dist2

New Mexico, ECE 650
Excerpt: ... VERSITY O F U M B C 1966 UMBC MO 4 (5/1/07) RE COUNT Y UN Digital Systems Clock Distribution II CMPE 650 Clock Signal Duty Cycle This circuit computes the average DC value and stores it on C2. The value on C2 adjusts the input switching threshold to achieve an output duty cycle closer to 50%. Canceling Parasitic Capacitance of Clock Repeaters Adding a device to the clock wire adds parasitic capacitance , which shifts the received clock phase on all devices on the line. This circuit can be used to combat the parasitic capacitance . Clock input VCC R1 R2 100K 100K L1 C1 Cp parasitic capacitance of circuit trace, connector and gate. M AR YLAND BA L TI IVERSITY O F U M B C 1966 UMBC MO 5 (5/1/07) RE COUNT Y UN Digital Systems Clock Distribution II CMPE 650 Canceling Parasitic Capacitance of Clock Repeaters The inductor presents a negative reactance at the clock frequency and partially cancels the parasitic capacitance of the clk receiver circuit. This is called a matching network. Note ...

ee461_lecture_34

Montana, EE 461
Excerpt: ... transmitted signal is called Time Domain Transmission (TDT) - This observation point gives the amount of energy that was successfully transmitted through the interconnect structure. - The inputs to the TDR/TDT oscilloscope are all 50ohms, so connecting the Far-End of the system to a TDT input is a convenient method to terminate the system. EE 461 Digital System Design Spring 2008 Lecture #34 Page 3 TDR/TDT Literature - The following Application Notes give some additional theory on TDR/TDT & some practical methods to use the information. - These are located on the Course Website under "Information" Time Domain Reflectrometry Theory, Agilent Technologies Measuring Parasitic Capacitance & Inductance Using TDR, Agilent Technologies Signal Integrity Analysis using TDR, Agilent Technologies Time Domain Methods for Measuring Crosstalk for PCB Quality Verification, Tektronix EE 461 Digital System Design Spring 2008 Lecture #34 Page 4 ...

ee461_lecture_34

Montana, EE 461
Excerpt: ... transmitted signal is called Time Domain Transmission (TDT) - This observation point gives the amount of energy that was successfully transmitted through the interconnect structure. - The inputs to the TDR/TDT oscilloscope are all 50ohms, so connecting the Far-End of the system to a TDT input is a convenient method to terminate the system. EE 461 Digital System Design Spring 2008 Lecture #34 Page 3 TDR/TDT Literature - The following Application Notes give some additional theory on TDR/TDT & some practical methods to use the information. - These are located on the Course Website under "Information" Time Domain Reflectrometry Theory, Agilent Technologies Measuring Parasitic Capacitance & Inductance Using TDR, Agilent Technologies Signal Integrity Analysis using TDR, Agilent Technologies Time Domain Methods for Measuring Crosstalk for PCB Quality Verification, Tektronix EE 461 Digital System Design Spring 2008 Lecture #34 Page 4 2 ...

lecture-15_mar2-2006

UCSC, EE 171
Excerpt: ... Amplifier: Frequency Response Bode plot Miller effect High frequency response Low frequency response Figure 8.1 Low-pass RC filter. Figure 8.2 Logarithmic frequency scale. Figure 8.3 Bode plot for the low-pass RC filter. Figure 8.4 Bode plot for phase of the low-pass RC filter. Figure 8.5 Circuit for Example 8.1. Figure 8.6 Bode plots of the terms on the right-hand side of Equation (8.19). Figure 8.7 Bode plot of the magnitude of Av for the circuit of Figure 8.5. Figure 8.8 Approximate plots of the terms of Equation (8.20). Figure 8.9 Bode phase plot of the voltage-transfer function for the circuit of Figure 8.5. High frequency FET model with parasitic capacitance s Small signal model should include the parasitic capacitance s of the device to determine the frequency response. High-frequency FET equivalent circuit. We can draw the small signal equivalent circuit for the common source amplifier given below. Common-source amplifier. Using same node equations as before, we can find ...

EE 434 Lect 9 Fall 2006

Iowa State, EE 434
Excerpt: ... to Poly on thin oxide in most processes Dog-bone often needed for minimum-length devices Contacts B' B Acceptable Contact Contacts A B' A' B Acceptable Contact Unacceptable Contact Vulnerable to pin holes Contacts Common Circuit Connection Standard Interconnection Buried Contact Can save area but not allowed in many processes Contacts 2 2 1.5 2 1.5 "Dog Bone" Contact Design Rule Violation Metalization Aluminum widely used for interconnect Copper finding some applications Must not exceed maximum current density around 1ma/u Ohmic Drop must be managed Parasitic Capacitance s must be managed Interconnects from high to low level metals require connections to each level of metal Stacked vias permissible in some processes Multiple Level Interconnects 3-rd level metal connection to n-active without stacked vias Multiple Level Interconnects 3-rd level metal connection to n-active with stacked vias Interconnects Metal is preferred interconnect Because conductivity ...

photran_31-Jan-2005

Purdue, JONES 105
Excerpt: ... Preamp Model 50 load, 50 mV/div preamp, 50 mV/div output, 500 mV/div Response to 0.01 nC pulse 5 Preamp Model 50 load, 200 mV/div preamp, 200 mV/div output, 1 V/div Soft saturation properly modeled Response to 0.05 nC pulse 6 Preamp Model Gain response parameterized as in CDF Note 5362: Hard saturation 27 C Soft saturation 47 C 57 C High gain region 7 Preamp Model Measured parameters: Simulation: 8 Preamp Model Comparison of gain parameters with measured distributions: Small signal differential gain Large signal differential gain SPICE model Gain switching threshold Width of gain switching region 9 Preamp Model Comparison of node voltages: Small differences are not likely to affect small signal gain. 10 Preamp Model Probable unknowns: Supply voltages in the detector Measure them next time the plugs are open Temperature in the detector No simulation of parasitic capacitance Parameters for gain switching diode model Qualitative behavior seems reasonable. ...

photran_31-Jan-2005

Purdue, JONES 105
Excerpt: ... ut, 1 V/div Soft saturation properly modeled Response to 0.05 nC pulse 6 Gain response parameterized as in CDF Note 5362: Hard saturation 27 37 C 47 C 57 C High gain region C Soft saturation 7 Measured parameters: Simulation: 8 Comparison of gain parameters with measured distributions: Small signal differential gain Large signal differential gain SPICE model Gain switching threshold Width of gain switching region 9 Comparison of node voltages: Small differences are not likely to affect small signal gain. 10 Probable unknowns: Supply voltages in the detector Measure them next time the plugs are open Temperature in the detector No simulation of parasitic capacitance Parameters for gain switching diode model Qualitative behavior seems reasonable. Small signal response agrees well with measurements and should be adequately described. 11 SPICE3 simulation now interfaced with photon transport Monte Carlo: Response to 1 MIP through bar at z=0. This is an important achievement! 12 PM ...

intro_637

W. Alabama, ECE 637
Excerpt: ... ECE 637 Integrated VLSI Circuits Introduction EE141 Introduction 1 Course Details Instructor Mohab Anis; manis@vlsi.uwaterloo.ca Text Digital Integrated Circuits, Jan Rabaey, Prentice Hall, 2nd edition Grading Project 35%, Presentation 15%, Final 50% EE141 Introduction 2 Course Outline Introduction this lecture (1) Diode (3) Static behavior; Parasitic capacitance s and dynamic behavior; Secondary effects & SPICE model MOS Transistor (6) Static behavior; Parasitic capacitance s and dynamic behavior; Short channel effects; scaling; SPICE MOS models; Process variations & process impact MOS Inverter (7) Properties; Static behavior; Dynamic behavior; Power, energy consumption and power-delay, energy-delay products; Layout considerations/design rules EE141 Introduction 3 Course Outline (Contd.) Combinational Circuits (8) Implementation styles - static, ratioed, pass transistor; CPL, dynamic logic ; Signal integrity issues in dynamic circuits; Cascading dynamic circuits; Low power, high performanc ...

EE 435 Lect 43 Spring 2009

Iowa State, EE 435
Excerpt: ... T)=VOUT(nT)-(C1/C)VIN(nT) C - 1 C I( z ) = z-1 Switched-capacitor circuits are analyzed in the z-domain rather than in the s-domain Coefficients are precisely controlled with small area even if TCLK is not much smaller than TSIG Assumption of input S/H is really not necessary Often no underlying Active RC circuit (direct synthesis in the discrete domain) SC circuits are discrete-time continuous-amplitude circuits Switched-Capacitor Filters Parasitic Capacitance s Parasitic capacitance s are large, do not match, and most are nonlinear ! Switched-Capacitor Filters Parasitic Capacitance s Parasitics affecting charge transfer are indicated CP=Cs1+Cd2+CT1 VOUT(nT+T) = VOUT(nT) - ([C1+CP]/C)VIN(nT) Can affect the ratio C1/CP by 30% or more Most of the accuracy improvements offered by SC technique lost in parasitics ! Switched-Capacitor Filters Consider: with input S/H VOUT(nT+T) = VOUT(nT) + (C1/C)VIN(nT) C1 C I( z ) = ...

L5_objectives

Excerpt: ... Objectives What affects CMOS circuit performance? And how do we characterize its elements. What are the parasitic capacitance s? What is a SPICE model for a transistor ? What are the rise time and fall time How do we model a load? How do we calculate delays CONCORDIA VLSI DESIGN LAB ...

093098_lecture16

Berkeley, EE 105
Excerpt: ... itic capacitance to the substrate from the drain regions of inverter 1 and the interconnections between the output of inverter 1 and the inputs of inverters 2 and 3. V DD W L p2 s Hand calculation of propagation delays: use approximation that input changes instantaneously VIN VOH tCYCLE VIN VDD V DD W L p1 + CL VOUT VIN 1 W L n1 2 W L n2 VDD W L p3 3 VOL t VOUT VOH 50% VOL t tCYCLE tPHL tPLH VOH s (a) (b) W L n3 For hand calculation, we do a worst case estimate of CG by adding the maximum gate capacitances for inverters 2 and 3 C G = C ox [ ( W L ) p2 + ( W L ) + ( W L ) p3 + ( W L ) ] n2 n3 EECS 105 Fall 1998 Lecture 16 EECS 105 Fall 1998 Lecture 16 Parasitic Capacitance from Drain Depletion Regions s Calculation of Parasitic Depletion Capacitance s The drain n and p regions have depletion regions whose stored charge changes during the transient. Take the worst case and use the zero-bias depletion capacitance (the maximum value) as a linear charge-storage element during th ...

grp30

N.C. State, ECE 546
Excerpt: ... ECE 546 VLSI Final Project Report (Group 30) A 2 GHz 48 bit Multi-Ports SRAM Design in 45 nm CMOS Fabrication Process Chun-Ying Huang, Ho-Hsin Yeh, Seung Kyun Heo Introduction 1 The appealing point of the static circuit is the low power consumption, compared with dynamic circuits. In order to drive the larger parasitic capacitance s in the word lines, the sizes of the transistors are optimized. Fig 7 presents the column decoder and multiplexer circuitry. The sizing of the transistors also needs careful optimization in order to drive the larger parasitic capacitive loads in the bit lines. Fig 8 presents the Flip-Flops used to hold the data in the outputs. The Flip-Flops are implemented with TSPCL D Flip Flops. This circuit is originally the TSPC flip flop. Additional transistor added in TSPC will make this dynamic edge triggered flip flop be susceptible of the noise [2] [3]. According to this SRAM design, only one type of the circuit, which is the edge triggered flip flop, needs the clocking input. The inserti ...

EE 330 Lect 11 Fall 2007

Iowa State, EE 330
Excerpt: ... EE 330 Lecture 11 IC Fabrication Technology - Back-end Processes Devices in Semiconductor Processes Quiz 10 What is the major reason contacts of metal to poly are not allowed in the gate region of a transistor? A A' Unacceptable Contact And the number is . 1 8 3 5 4 6 9 7 2 And the number is . 1 7 4 9 6 3 8 2 5 Quiz 10 What is the major reason contacts of metal to poly are not allowed in the gate region of a transistor? A A' Unacceptable Contact Solution: Pin-holes will degrade yield Review from Last Time Contacts usually of a fixed size All etches reach bottom at about the same time Multiple contacts widely used Contacts not allowed to Poly on thin oxide in most processes Dog-bone often needed for minimum-length devices Review from Last Time Metalization Aluminum widely used for interconnect Copper finding some applications Must not exceed maximum current density around 1ma/u Ohmic Drop must be managed Parasitic Capacitance s must be managed Interco ...