UMass (Amherst), ECE 221

Excerpt: ... ENGIN 112 Intro to Electrical and Computer Engineering Lecture 30 Random Access Memory (RAM) ENGIN112 L30: Random Access Memory November 14, 2003 Overview Memory is a collection of storage cells with associated input and output circuitry Possible to read and write cells Random access memory (RAM) contains words of information Data accessed using a sequence of signals Leads to timing waveforms Decoders are an important part of memories Selects specific data in the RAM Static RAM loses values when circuit power is removed. ENGIN112 L30: Random Access Memory November 14, 2003 Preliminaries RAMs contain a collection of data bytes A collection of bytes is called a word A sixteen bit word contains two bytes Capacity of RAM device is usually described in bytes (e.g. 16 MB) Write operations write data to specific words Read operations read data from specific words Note: new notation for OR gate ENGIN112 L30: Random Access Memory November 14, 2003 RAM ...

Colorado, ECEN 5355

Excerpt: ... Lecture #38: MOS Memory Random access memory Static (SRAM) Dynamic (DRAM) Read only memory ROM, PROM, EPROM Floating Gate memory ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2005 Memory Addressing Bit lines Word lines Memory cell Memory cell Memory cell Memory cell Sense Amplifiers ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2005 Static Random Access Memory (SRAM) Bit lines Word lines Dynamic Random Access Memory (DRAM) Bit lines Word lines Sense Amplifiers ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2005 Sense Amplifiers ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2005 Dynamic Random Access Memory (DRAM) Word lines Bit lines Poly-silicon word line Metal bit line Source and Drain regions Trench capacitors Trench capacitor (a) ECEN5355 Lecture # 38 (b) Bart Van Zeghbroeck, 2005 ...

SPSU, ECET 2210

Excerpt: ... Random Access Memory (RAM) All types of RAM are read/write memory device with the following general characteristics: - Data is arranged in arrays - Information accessed is independent of location which is unlike older serial-access memories such as CCD and magnetic bubble memories. - RAM is volatile (data is lost if power removed) NOTE Some newer RAMs offer non-volatile operation such as CMOS RAM with a Lithium battery as well as ferroelectric RAMs. The two types we will study within the scope of this class are Static and Dynamic RAM (SRAM & DRAM) STATIC RAM (SRAM) Once a word is written to an address, it remains as long as power is applied unless the ADDR is written to again Details on the inputs and outputs of SRAM chips CS - Chip Select is an input that enables/disables general access to the SRAM chip (standby mode) OE - Output Enable controls the Hi-Z output data (just like the ROM case) and also bidirectional data if used WE - Write Enable controls the writing to RAM locations similar to the ...

Penn State, IST 110

Excerpt: ... Quiz B Study CDs & DVDs are examples of optical storage Computer memory (RAM) is an example of random access memory while tape drives are examples of sequential access memory. 800x600 is an example of monitor resolution When you record your voice into your computer using microphone, a digital to analog conversion is occurring. Your Ipod is playing a music file. a digital to analog BIOS stands for: Basic Input Output System RAM is considered volatile memory while a hard drive is non-volatile memory The data bus carries data from the RAM to the CPU The number 101 in BINARY would translate to what number in DECIMAL? 5 ...

Texas A&M, ENGR 111

Excerpt: ... ed for longer time Input D(t) D(t-1) D(t-2) Clock Counters Flip-flops with logic Examples in lab: 74LS161, 74LS393 Use special flipflops JK T toggle Implemented with RS latch + logic Texas Instruments SN74LS393D Toggle FF is D flipflop with ~Q output connected to D input Counter Operation Current D C BA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 D 0 0 0 0 0 0 0 1 Next C B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 A 1 0 1 0 1 0 1 0 Counter Applications Note bit D of counter goes to 1 on the 8th clock cycle Can use counter to divide clock to lower frequency (2x every bit) Can use counter to generate time delays One counter can produce multiple results Bit C runs at twice the frequency as bit D Bit C goes to 1 on the 4th clock cycle SRAM Static Random Access Memory SRAM Static Random Access Memory SRAM Function Cell holds value as long as power applied When RowSelect = 1, cell can be written or read Cell written by precharging bit/~bit lines to requ ...

Arizona, PHYS 405

Excerpt: ... Homework Assignment 8 Worksheet: D-Latch Homework Cogdell: 3.36, 3.40, 3.41, 3.54 Notes 1. Logic which is controlled by other logic or controls other circuitry in a specific order is called sequential logic. The object which dictates the sequence can be either a control clock or a enable/disable signal. 2. Unlike combinatorial logic, sequential logic can remember a state even when the inputs are removed. This feature forms the basis of random access memory or RAM. 3. The circuit shown above is called a D latch. Procedure 1. Draw the circuit shown above. 2. Write down the truth table for each of the four input states. 3. Describe how this circuit works. Can the output change while the gate is high? How does this circuit differ from the SR latch? 1 ...

Berkeley, EE 40

Excerpt: ... Important note regarding Pre-Lab this week This week you will finish the audio amplifier project by building the tone control and amplifier. In order to finish the project you should build the circuit BEFORE COMING TO THE LAB on the circuit board you ...

UPR Mayagüez, INEL 4076

Excerpt: ... Lecture 22: Memories Topics: How are memories constructed? PROM (Programmable Read Only Memories) EPROM (Electronically Programmable ROM) EEPROM (Electrically Erasable PROM) FLASH Memories How to use ROMs RAM ( Random Access Memory ) Shadow RAM Memory Battery Backup Objectives: After this lesson students should understand all basic forms of static memories, how they are constructed and interfaced to a microprocessor based system. References: Students interested in further understanding static memories should read chapter 6.3 of the Miller class book. 21-1 Flash Memory Devices Is a somewhat different type of EEPROM. Can not be erased byte by byte. Faster Erasing sequence (a sector at a time). That's why they are called FLASH! Programming times same as EEPROM. Occupy almost same space as EPROM (higher density than EEPROM) 21-6 What are ROM Used For? Firmware Like an OS for microcontrolled devices such as CD players, VHS, HArd Drives, etc. Tells the microcontrolled device what to do on power on and operation ...

Georgia Tech, CS 3500

Excerpt: ... ns that we will charge one unit of cost to each such operation This is a convention. It is the most reasonable convention in today's computer technology. It is known as the RAM ( random access memory ) model. (Note: The swap procedure can be also realized with a couple of array operations.) Remark on Space Efficiency: The depth of the recursive code is approximately n. Thus the recursive code needs a stack of size approximately n to keep track of the recursive calls. This is additional memory requirement of O(n). On the other hand, the iterative code needs only a couple of counters to keep i, j and a couple of pointers. 9 Time Complexity, measured by the number of COMPARISONS. Note: This is yet another convention. It is a particularly suitable abstraction for the sorting problem. Finding a good abstraction is very important in understanding and solving a problem ! I am solving this recurrence by SUBSTITUTION ! (Full review on recurrences in Lectures 2 and 3, but make sure you understand the steps I am takin ...

Colorado, ECEN 5355

Excerpt: ... Lecture #38: MOS Memory Random access memory Static (SRAM) Dynamic (DRAM) Read only memory ROM, PROM, EPROM Floating Gate memory, Flash ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 Silicon on Insulator (SOI) Trench isolation Source p+ n+ p-type silicon SiO2 insulator silicon substrate Gate Drain n+ Figure 7.7.8 a) Schematic cross-section of an SOI MOSFET and b) TEM micrograph of an SOI MOSFET with 7 nm thick channel. ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 Scaled MOSFET Scaled MOSFET ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 7.7.10 FinFET CMOS Inverter (Cross section) Figure 7.7.2 CMOS inverter ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 CMOS Inverter (Top view) CMOS Latchup pnp npn ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 ECEN5355 Lecture # 38 Bart Van Zeghbroeck, 2008 CMOS Logic families Memory Addressing Bit lines 1 bit Word lin ...

Allan Hancock College, MDL 112

Excerpt: ... Selective etching of (Ba,Sr)TiO3 thin films over mask materials and silicon in an inductively coupled plasma Gwan-Ha Kim and Chang-Il Kim School of electrical and electronics engineering, Chung-Ang University, 221 Heukseuk-Dong, Dongjak-Gu, Seoul 156-756, Korea With the recent increase in integration density of dynamic random access memory (DRAM), a large charge storage density is required. To ensure sufficient accumulated electric charge with a smaller capacitor area, (Ba,Sr)TiO3 (BST) thin film are attracted to the capacitor dielectric for Gbit DRAM because of its large dielectric constant, low leakage current and low dielectric loss. But, there are several problems such as fine pattern transfer and no plasma induced-damage etc. In order to solve these problems, the etch behavior of BST with various gas mixture is performed with inductively coupled plasma. In this study, inductively coupled plasma etching system was used for BST thin films etching. The various plasmas were characterized by optical emission ...