Documents about Silicon Wafers

  • 13 Pages

    HW_3-Solutions2007

    University of Michigan, EECS 414

    Excerpt: ... oints 1 Solution: The final cross section is shown below. The etch will proceeed from the back and will stop as usual on the (111) planes. When the etch reaches the bottom of the square defined by the trench, it will continue to etch towards the top oxide layer, but now a new set of (111) planes will appear inside the square as shown. These planes will go down at an anngle of 54.7 until they reach the top oxide and the etch will stop there. Note that there is a region where you have (111) planes on the inside of the square. 2 2. It was said in lecture that usually anisotropic wet etching of silicon is more desirable than isotropic wet etching. Name 3 uses of isotropic etching. 5 points Solution: Isotropic etching is used for : Removal of damage or polishing Si Creating structures with round surfaces Thinning silicon wafers Delineation of electrical junctions or defects 3. In the top-view diagram below, the shaded part of a p-type (100) Si wafer has a thin p+ (meaning heavily boron dope ...

  • 2 Pages

    EE438L-sp09

    USC, EE 438L

    Excerpt: ... tudent will process his/her 3 Silicon wafer alone under the supervision of the laboratory instructors. The finished wafers are electrically tested for the extraction of the parameters of various devices on the wafer. Grading Policy: 1) 2) 3) 4) 5) Homework Laboratory Work Midterm Final Written Report Final Exam 15% 20% 25% 15% 25% The due dates of the written reports will be strictly enforced and for every day of late submission of your report, you will loose 10% of the report grade. Schedule of the Lectures for EE 438L: Spring 2009 Week 1 Introduction to Semiconductor Industry Concept of clean room, cleaning and contamination removal Safety Issues in Clean Room Silicon Wafers , from sand to polished wafers, silicon defects Thermal Oxidation of Silicon (HW 1) Lithography I (Basic Principles and concepts) Lithography II (Advanced Techniques) (HW 2) Thin Film Technology Diffusion Ion Implantation: (HW 4) Midterm Etching Basic Concept in wet & dry etching CMOS Technology (HW ...

  • 44 Pages

    Lecture_4-Wet_Processing_clean

    CUNY City, EE 300

    Excerpt: ... itical (Fatal) Defect (Particle) Size = 1/2 Minimum Feature Size ITRS Feature Year 2007 2010 2013 Minimum Feature Sizenm 65 45 32 2016 22 2020 14 Three tiered approach clean room wafer cleaning gettering Particle Particle Organics: Oil,Photoresist Organics: Oil,Photoresist Metal/Alkali ions Metal/Alkali ions Native oxide Native oxide Mikael stling KTH IH2655 Spring 2008 Contaminants may consist of particles, organic films (photoresist), heavy metals or alkali ions. Mikael stling KTH IH2655 Spring 2008 Harm of the unwanted impurity Example 2. Effects of alkali ions on MOS threshold voltage 2 s qN A (2 f ) qQM Vth = VFB + 2 f + + Cox Cox If tox10 nm, when QM6.51011 cm-210 ppm), Vth0.3 V Example 3. Request of MOS DRAM refresh time on trap density Nt R G = Typically, = 10-15 cm2, vth= 10-7 cm/s So R100 s requires Nt 1012 cm-3 =0.02 ppb ! Mikael stling KTH vth N t 1 IH2655 Spring 2008 Particles might deposit on silicon wafers and cause ...

  • 1 Pages

    hw3chee

    U. Houston, CHEE 1131

    Excerpt: ... Homework #3 Introduction to Chemical Engineering 1. Describe the steps required to produce polished silicon wafers , starting with the raw material, SiO2. After oxide is placed on the wafer, the resist is put on. Then the reticule is put over the wafer, where light shines through parts of it to expose the certain pattern on the resist, which is photosensitive. The resist is further progressed, and the excess is cleaned off of the wafer. A dry etch eradicates the unprotected oxides, and then the residual resist is cleaned in wet etch to show the patterned layer of oxide. Then the wafer is washed. That makes a polished silicon wafer. 2. Describe how small features (lines, holes, etc.) are made in integrated circuits. By using photolithography, one can use insulating layer to structure the circuit components. The photoresist toughens the wanted designs. Metallization is where the bonds are created on the integrated circuits. 3. Boron is a common dopant (impurity) in silicon. If a typical silicon wafer with a diam ...

  • 1 Pages

    SiliconRun2 Answers

    Cal Poly, IME 156

    Excerpt: ... Silicon Run II Questions 1. Logic circuits, such as AND, OR and NOT gates, consist of integrated circuits using _ as switches. transistors 2. Logic gates are the "building blocks" of integrated circuits. True/False 3. After the silicon wafer circuit ...

  • 1 Pages

    SiliconRun2 Answers

    Cal Poly, IME 156

    Excerpt: ... Silicon Run II Questions 1. Logic circuits, such as AND, OR and NOT gates, consist of integrated circuits using _ as switches. transistors 2. Logic gates are the "building blocks" of integrated circuits. True/False 3. After the silicon wafer circuit ...

  • 4 Pages

    Exam1ReviewFall07

    Wisconsin Milwaukee, BUS ADM 230

    Excerpt: ... Bus Adm 230 Introduction to Information Systems Lectures 401, 402 and 403 - Fall 2007 Review Sheet for Exam 1 Exam 1 will be held on Thursday October 4 during lecture class. In order to prepare adequately for the exam you should Have attended lecture ...