Documents about Silicon Wafers

  • 10 Pages

    083198_lecture4

    Berkeley, EE 105

    Excerpt: ... 4 Process Flow Examples s Three-mask layout: oxide mask (dark field) contact mask (dark field) metal mask (clear field) , , , , , , , , A (a) , , , , , B A s Process (highly simplified): 1. Grow 500 nm of thermal oxide and pattern using oxide ...

  • 81 Pages

    SILICON

    BYU, ECE 224

    Excerpt: ... The Creation of a New Computer Chip Silicon Design Page 1 Concept A group of people from marketing, design, applications, manufacturing and finance develop the basic concept, features and rough specifications for a new product. Silicon Design Pa ...

  • 1 Pages

    Poster_1

    UVA, JFG 6

    Excerpt: ... [15]. Figure 4 shows a top view of the two heat treated copper samples. Critical challenges: This project is using the university's DVD system for deposition of the metal film. In this project, it is thought that it would be best to deposit a pure metal layer with no detectable contamination. Then, subsequent heat treating would introduce the oxygen into the developing nanostructures. It also seems advantageous, for eventual applications, if the metal films can be synthesized on a silicon wafer from which the native oxide has been removed. Initial auger electron spectroscopy (AES) study of DVD deposited silicon layers [16] reveals the presence of significant amounts of oxygen and carbon contamination in as-deposited films (Figure 9a). (It is anticipated that similar contamination levels would be found in copper films deposited by the DVD technique.) In addition, AES of the silicon wafers found measurable amounts of oxygen and carbon on the wafer surface [16], and an attempt to remove those contaminants via a ...

  • 3 Pages

    e495out02

    Sveriges lantbruksuniversitet, E 495

    Excerpt: ... McGraw-Hill "The Science and Engineering of Microelectronic Fabrication", Stephen Campbell, Oxford Univ. Press. "Silicon Processing, vol. 1", S. Wolf and R.N. Tauber, (Lattice Press). Prerequisite: The only prerequisites the students need are an understanding of basic transistor and diode operation. ENSC 222/ENSC 225 (Electronic Design I) or equivalent. Lecture Schedule ! Lecture Monday, 17:30 - 19:20, Wednesday 17:30 - 19:20 AQ5030 (Note lectures held usual on Monday, with Wednesday one of lab days). Week 1: Clean Room Technology and Silicon Wafer Production ! Basic outline of fabrication process: with to real structures. ! Theory behind clean room operations: ! History of semiconductor devices: diodes, transistors, Germanium/Silicon transition, monolithic integrated circuits ! Basic operation of Transistors, diodes ! Projected trends in Fabrication ! Theory and operations for contamination elimination, and safety issues. ! Silicon wafers ; Crystallography, Production and Defects: ! Basic silicon wafer par ...

  • 4 Pages

    e495outy

    Sveriges lantbruksuniversitet, E 495

    Excerpt: ... rication", Stephen Campbell, Oxford Univ. Press. "Silicon Processing, vol. 1", S. Wolf and R.N. Tauber, (Lattice Press). Prerequisite: The only prerequisites the students need are an understanding of basic transistor and diode operation. ENSC 222/ENSC 225 (Electronic Design I) or equivalent. Lecture Monday, Wednesday 16:30 - 20:20 pm, AQ4120 Lecture Schedule Week 1: Clean Room Technology and Silicon Wafer Production Basic outline of fabrication process: with to real structures. Theory behind clean room operations: History of semiconductor devices: diodes, transistors, Germanium/Silicon transition, monolithic integrated circuits Basic operation of Transistors, diodes Projected trends in Fabrication Theory and operations for contamination elimination, and safety issues. Silicon wafers ; Crystallography, Production and Defects: Basic silicon wafer parameters, solid solubility of dopants in silicon, defects, and basic economics of operations. Week 2: Thermal Oxidation ...

  • 4 Pages

    e495out1

    Sveriges lantbruksuniversitet, E 495

    Excerpt: ... rication", Stephen Campbell, Oxford Univ. Press. "Silicon Processing, vol. 1", S. Wolf and R.N. Tauber, (Lattice Press). Prerequisite: The only prerequisites the students need are an understanding of basic transistor and diode operation. ENSC 222/ENSC 225 (Electronic Design I) or equivalent. Lecture Monday, 18:30 - 20:20, Wednesday 18:30 - 19:20 AQ4120 Lecture Schedule Week 1: Clean Room Technology and Silicon Wafer Production Basic outline of fabrication process: with to real structures. Theory behind clean room operations: History of semiconductor devices: diodes, transistors, Germanium/Silicon transition, monolithic integrated circuits Basic operation of Transistors, diodes Projected trends in Fabrication Theory and operations for contamination elimination, and safety issues. Silicon wafers ; Crystallography, Production and Defects: Basic silicon wafer parameters, solid solubility of dopants in silicon, defects, and basic economics of operations. Week 2: Thermal Oxidation Basic the ...

  • 13 Pages

    HW_3-Solutions2007

    University of Michigan, EECS 414

    Excerpt: ... oints 1 Solution: The final cross section is shown below. The etch will proceeed from the back and will stop as usual on the (111) planes. When the etch reaches the bottom of the square defined by the trench, it will continue to etch towards the top oxide layer, but now a new set of (111) planes will appear inside the square as shown. These planes will go down at an anngle of 54.7 until they reach the top oxide and the etch will stop there. Note that there is a region where you have (111) planes on the inside of the square. 2 2. It was said in lecture that usually anisotropic wet etching of silicon is more desirable than isotropic wet etching. Name 3 uses of isotropic etching. 5 points Solution: Isotropic etching is used for : Removal of damage or polishing Si Creating structures with round surfaces Thinning silicon wafers Delineation of electrical junctions or defects 3. In the top-view diagram below, the shaded part of a p-type (100) Si wafer has a thin p+ (meaning heavily boron dope ...

  • 2 Pages

    EE438L-sp09

    USC, EE 438L

    Excerpt: ... tudent will process his/her 3 Silicon wafer alone under the supervision of the laboratory instructors. The finished wafers are electrically tested for the extraction of the parameters of various devices on the wafer. Grading Policy: 1) 2) 3) 4) 5) Homework Laboratory Work Midterm Final Written Report Final Exam 15% 20% 25% 15% 25% The due dates of the written reports will be strictly enforced and for every day of late submission of your report, you will loose 10% of the report grade. Schedule of the Lectures for EE 438L: Spring 2009 Week 1 Introduction to Semiconductor Industry Concept of clean room, cleaning and contamination removal Safety Issues in Clean Room Silicon Wafers , from sand to polished wafers, silicon defects Thermal Oxidation of Silicon (HW 1) Lithography I (Basic Principles and concepts) Lithography II (Advanced Techniques) (HW 2) Thin Film Technology Diffusion Ion Implantation: (HW 4) Midterm Etching Basic Concept in wet & dry etching CMOS Technology (HW ...

  • 44 Pages

    Lecture_4-Wet_Processing_clean

    CUNY City, EE 300

    Excerpt: ... itical (Fatal) Defect (Particle) Size = 1/2 Minimum Feature Size ITRS Feature Year 2007 2010 2013 Minimum Feature Sizenm 65 45 32 2016 22 2020 14 Three tiered approach clean room wafer cleaning gettering Particle Particle Organics: Oil,Photoresist Organics: Oil,Photoresist Metal/Alkali ions Metal/Alkali ions Native oxide Native oxide Mikael stling KTH IH2655 Spring 2008 Contaminants may consist of particles, organic films (photoresist), heavy metals or alkali ions. Mikael stling KTH IH2655 Spring 2008 Harm of the unwanted impurity Example 2. Effects of alkali ions on MOS threshold voltage 2 s qN A (2 f ) qQM Vth = VFB + 2 f + + Cox Cox If tox10 nm, when QM6.51011 cm-210 ppm), Vth0.3 V Example 3. Request of MOS DRAM refresh time on trap density Nt R G = Typically, = 10-15 cm2, vth= 10-7 cm/s So R100 s requires Nt 1012 cm-3 =0.02 ppb ! Mikael stling KTH vth N t 1 IH2655 Spring 2008 Particles might deposit on silicon wafers and cause ...

  • 17 Pages

    Lithography1

    Johns Hopkins, ECE 495

    Excerpt: ... 520/580.495 PHOTOLITHOGRAPHY Andreas G. Andreou Lecture notes adapted from handout notes for Microelectronics: An Integrated Approach http:/www.prenhall.com/howe/microelectronics/ by R. T. Howe and C.G. Sodini A.G. Andreou 2000 1 IC Fabrication T ...

  • 1 Pages

    P9826_HW4_2009

    UWO, P 9826

    Excerpt: ... For HWA#4, I would like to ask you to download SRIM from the Internet and install it in your computer. Please use it to answer the following questions: In late 90s, IBM and other players in the IC industry introduced the concept of SOI (silicon on in ...

  • 1 Pages

    hw3chee

    U. Houston, CHEE 1131

    Excerpt: ... Homework #3 Introduction to Chemical Engineering 1. Describe the steps required to produce polished silicon wafers , starting with the raw material, SiO2. After oxide is placed on the wafer, the resist is put on. Then the reticule is put over the wafer, where light shines through parts of it to expose the certain pattern on the resist, which is photosensitive. The resist is further progressed, and the excess is cleaned off of the wafer. A dry etch eradicates the unprotected oxides, and then the residual resist is cleaned in wet etch to show the patterned layer of oxide. Then the wafer is washed. That makes a polished silicon wafer. 2. Describe how small features (lines, holes, etc.) are made in integrated circuits. By using photolithography, one can use insulating layer to structure the circuit components. The photoresist toughens the wanted designs. Metallization is where the bonds are created on the integrated circuits. 3. Boron is a common dopant (impurity) in silicon. If a typical silicon wafer with a diam ...

  • 21 Pages

    Oxidation

    Johns Hopkins, ECE 495

    Excerpt: ... 520/580.495 Silicon Oxidation Andreas G. Andreou Lecture notes adapted from Microfabrication handout notes by Norman Sheppard A.G. Andreou 2000 In this lecture we'll cover the processes of oxidation. References: R.C. Jaeger, Introduction to Microel ...

  • 10 Pages

    Oxidation

    Johns Hopkins, ECE 495

    Excerpt: ... 520/580.495 Silicon Oxidation Andreas G. Andreou Lecture notes adapted from Microfabrication handout notes by Norman Sheppard A.G. Andreou 2000 In this lecture we'll cover the processes of oxidation. References: R.C. Jaeger, Introduction to Microel ...

  • 1 Pages

    SiliconRun2 Answers

    Cal Poly, IME 156

    Excerpt: ... Silicon Run II Questions 1. Logic circuits, such as AND, OR and NOT gates, consist of integrated circuits using _ as switches. transistors 2. Logic gates are the "building blocks" of integrated circuits. True/False 3. After the silicon wafer circuit ...

  • 1 Pages

    SiliconRun2 Answers

    Cal Poly, IME 156

    Excerpt: ... Silicon Run II Questions 1. Logic circuits, such as AND, OR and NOT gates, consist of integrated circuits using _ as switches. transistors 2. Logic gates are the "building blocks" of integrated circuits. True/False 3. After the silicon wafer circuit ...

  • 2 Pages

    Cleanroom

    Purdue, PHYS 3

    Excerpt: ... Figure : Coordinate Measuring Machine Used with optical video probe for precision alignment of silicon wafers . Used with touch trigger probe for part and fixture inspection. Figure : Electrical Testing Facility. Two 64-channel probe cards are used to test for continuity and shorts. Single probes are used for leakage current and depletion voltage measurements. Figure : K&S wirebonder used for electrical conection of traces between silicon wafers . ...

  • 4 Pages

    Exam1ReviewFall07

    Wisconsin Milwaukee, BUS ADM 230

    Excerpt: ... Bus Adm 230 Introduction to Information Systems Lectures 401, 402 and 403 - Fall 2007 Review Sheet for Exam 1 Exam 1 will be held on Thursday October 4 during lecture class. In order to prepare adequately for the exam you should Have attended lecture ...