UCSD, ECE 25
Excerpt: ... ECE 25 Introduction Lab 2 3-Bit Exclusive-Or Gate The goal of this lab is to generate our first design using the programmable chip by implementing a 3-bit XOR gate . We also generate the same gate by using the NAND gates introduced in Lab 1. Prelab due Friday Before Lab turn in BEFORE lecture. Goal: Use Project Navigator to implement a 3-bit X-OR gate using two 2-input XOR gate s. This requires learning the tool. Both a written and video tutorial from the company that makes the boards are available on the class Web site. Following these tutorials, print out both the schematic of the 3-bit XOR gate and the timing diagram from Modelsim which shows all 8 possible output states. Remember that the inputs and outputs of your circuit need to be labeled using the format listed in the written tutorial ("Using Project Navigator") on the Lab Web Site. Failure to follow the labeling procedure will result in a zero grade for the Pre-lab. You also need to hand draw out a schematic for 3-bit XOR gate using only 2-bit N ...
UCSD, ECE 25
Excerpt: ... ECE 25 Lab 2 3-Bit Exclusive-Or Gate Introduction The goal of this lab is to generate our first design using the programmable chip by implementing a 3-bit XOR gate . We also generate the same gate by using the NAND gates introduced in Lab 1. Prelab due Friday Before Lab turn in BEFORE lecture. Goal: Use Project Navigator to implement a 3-bit X-OR gate using two 2-input XOR gate s. This requires learning the tool. Both a written and video tutorial from the company that makes the boards are available on the class Web site. Following these tutorials, print out both the schematic of the 3-bit XOR gate and the timing diagram from Modelsim which shows all 8 possible output states. Remember that the inputs and outputs of your circuit need to be labeled using the format listed in the written tutorial ("Using Project Navigator") on the Lab Web Site. Also remember that the tutorial is an example of a schematic, however it is not the same one that you are being asked to create here; after completing the tutorial, ...
Berkeley, CS 152
Excerpt: ... le you work. This editor should only be used to maintain your online notebook. 2. When starting a new entry, type date at a unix prompt. Copy and paste it into your notebook. 3. Write down your goal for that entry. 4. Make note of accomplishments, bugs, or insights you may develop as you work. 5. Copy the output of Powerview at key points in development. 6. At the end of a session, type date at a unix prompt. Copy and paste it into your notebook. Problem 1: Timing Characteristics This problem will give you an opportunity to design a few simple circuits and measure their timing characteristics using Viewsim and Viewwave. In Viewsim, set the ticksize to 10ns (use command: stepsize N). Turn in schematics and Viewwave waveforms with the appropriate delays marked for each problem. 1.a: First measure the timing delays of an unloaded XOR gate (Low to High and High to Low) using Viewsim and Viewwave. 1.b: Use Viewdraw to create a circuit that implements the XOR function, using ve NAND gates (ie. ...
Rensselaer Polytechnic Institute, ECSE 2610
Excerpt: ... imised form is: F = (W+Z').(W+Y').(W'+Y+Z).(W'+X'+Y).(X'+Y'+Z) The Sop from is preferrable, due to lesser number of gates needed. -2) A significant hint in the question is the use of the circuit to check parity. The simplest parity checker is the XOR gate . the truth table of the XOR gate is: 0 0 1 1 0 1 0 1 0 1 1 0 Hence, the circuit can be thought of as checking for an odd number of 1s in the input consisting of 2 bits. To extend this idea to multiple inputs, just cascade a number od XOR gate s. For 5 inputs, XOR the first 2 inputs, then XOR the output of this gate with the third input and so on. This however will produce an odd parity checker. Eventually, an Inverter must be used before the actual output can be observed. Alternatively, a truth table for 5 inputs can be constructed, and the circuit impemented using AND/Or gates. ...
Texas A&M, ECEN 248
Excerpt: ... LAB COMPONENTS TO BE ISSUED FOR ECEN 248 COMPONENTS TO BE ISSUED Comp. Name Comp. Number Quantity Lab # 1 Introduction to Combination Design NOT Gate AND Gate OR Gate NOR Gate NAND Gate DIP Switches XOR Gate AND Gate OR Gate DIP Switches XOR Gate LED Bank NOT Gate AND Gate XOR Gate OR gate BCD to 7Segment Driver DIP Switches 7-Segment Display AND Gate XOR Gate 4-bit Full Adder 2:1 Multiplexer DIP Switches LED Bank SN74ALS04BN SN74ALS08N SN74ALS32N SN74AHCT02N SN74ALS00AN SDA08H1BD SN74ALS86N SN74ALS08N SN74ALS32N SDA08H1BD SN74ALS86N SSA-LXH1225ID SN74ALS04BN SN74ALS08N SN74ALS86N SN74ALS32N SN74LS247N 1 1 1 1 1 1 1 2 2 1 2 1 2 2 2 2 1 Scheduled Week Jan 26-Jan 30 and Feb 2-Feb 6 Lab # 2 Implementation of Binary Adders Lab # 3 Logic Minimization using Karnaughmaps Feb 9 Feb 13 Feb 16 Feb 20 SDA08H1BD LDS-A512RI SN74ALS08N SN74ALS86N CD74HC283E SN74HCT257N SDA08H1BD SSA-LXH1225ID 1 1 2 2 2 Lab # 4 4-bit Arithmetic Logic Unit Feb 23 Feb 27 2 2 1 Note: Labs from Lab#5 onwards doesn't need any comp ...
Minnesota, D 1315
Excerpt: ... 74LS86 Quad 2-Input XOR Gate s Positive Logic Y = A B = AB + AB ...
Allan Hancock College, CSE 5301
Excerpt: ... (conjugate gradient or Levenberg-Marquardt) to design an XOR gate . Aim at the minimal total number of synapses. Once the learning is nished, replace the output activation function with a unipolar step function and verify that the perceptron really acts as an XOR gate . Sketch the detailed structure of the obtained XOR perceptron. 2 2.3 Image coding algorithm with a two-layer perceptron Implement in MATLAB an image coding algorithm using a multi-layer perceptron and an advanced learning algorithm: Demo images can be found in $MATLAB/toolbox/matlab/demos/*.mat To examine the demo images run: load file_name whos image(X), colormap(map), title(caption) imageext For initial experimentation use a 6080 pixel sub-image from any image available in MATLAB. The block-matrix conversion functions blkM2vc.m, vc2blkM.m are in http:/www.csse.monash.edu.au/app/CSE5301/Mtlb Use either the Levenberg-Marquardt or a conjugate gradient algorithm. Determine the speed of training and the SNR ratio. ...
Berkeley, CS 152
Excerpt: ... or should only be used to maintain your online notebook. 2. When starting a new entry, type date at a unix prompt. Copy and paste it into your notebook. 3. Write down your goal for that entry. 4. Make note of accomplishments, bugs, or insights you may develop as you work. 5. Copy the output of waveforms (HDL Bencher output, for instance) at key points in development. 6. At the end of a session, type date at a unix prompt. Copy and paste it into your notebook. Problem 1: Timing Characteristics This problem will give you an opportunity to design a few simple circuits and measure their timing characteristics using Xilinx ECS schematic editor and Modelsim. Although you can do behavioral simulation to test functionality, you should make sure to use post-place-and-route simulation for actual timing. Make sure to turn in your Schematics and Waveform outputs in your lab report. 1.a: First measure the timing delays of an XOR gate and of a two-input NAND gate (Low to High and High to Low, load-dependent del ...
Berkeley, EE 100
Excerpt: ... EECS 100 Spring 2003 Problem Set #4 Solution Note: There are other possibilities of constructing circuits below. Shown here are the common and simple ones. 1. Devise an XOR using only NAND gates: A out B 2. Devise a NAND using only NOR gates: A out B 3. Devise a NOR using only NAND gates: A out B 1 4. Devise a full adder using only NAND gates: outn = an r bn r cn cn+1 = anbn + ancn + bncn To obtain outn, one has to connect two XOR gate s together and replace them with NAND logic blocks devised in question 1. To obtain cn+1, one has to connect anbn, ancn, and bncn to AND gates, and combine the resulting signals in OR gates. Then, replace AND and OR gates with appropriate NAND logic blocks. XOR gate s from part (1) an bn cn outn an bn an cn bn cn AND gates OR gates cn+1 2 ...
SUNY Oswego, ISC 320
Excerpt: ... ;= ; Example Circuit #1 ; ; An example circuit to be loaded for use with ; the "electronic.clp" example program. Note ; that OR gate #1 receives both inputs from the ; same source with one of the inputs negated. ; Therefore, the output of this OR gate should ; always be 1 and the value of source #1 is ; has no effect on the value of the LEDs. ; ; LEGEND ; - ; S = Source ; P = Splitter ; N = NOT Gate ; O = OR Gate ; X = XOR Gate ; L = LED ; ; ; /-N1>-\ /-L1 ; S1>-P1>-| O1>-P2>-| ; \-/ | ; | ; | ; \-\ ; X2>-L2 ; S2>-/ ; ;= (definstances circuit (S-1 of SOURCE) (S-2 of SOURCE) ...
Southern Illinois University Edwardsville, ECE 382
Excerpt: ... se Button ( RMB ) (also called Menu Button ). Mentor Graphics also has provisions for SOFTKEYS that allows you to perform operations using the keyboard. The Softkeys are displayed near the bottom of the Session window. They correspond to the function keys that are on your keyboard. There are four levels of key sequences: 1) Pressing only the function key. 2) Pressing the function key simultaneously with the Shift (s) key 3) Pressing the function key with the Ctrl (c) key. 4) Pressing the function key with the Alt (a) key. The characters "s", "c", "a" that is displayed vertically between F6 and F7 Softkeys indicate the key strokes for each row of function key actions. 2.1 Schematic Editor Schematic editor allows you to develop schematics of Analog and Digital circuits. The design that you will enter is a simple XOR gate circuit shown in Fig.2. Follow these instructions and enter the circuit. Fig.2 . : XOR gate 1. Click on the OPEN SHEET icon on the palette menu or select FILE>OPEN>SHEET from the pull-down m ...
Michigan State University, ECE 410
Excerpt: ... works have the same input signals (b, c, a) and each of the operations is complemented within the other network, i.e., all series combinations in pMOS are parallel combinations in nMOS. Homework 1 Solutions p. 4 Problem 6 (Design Challenge) a) As discussed in lecture, the XOR and XNOR CMOS schematics are very similar; they have exactly the same structure but two of the inputs are different. Based on this, construct a gatelevel schematic (no transistors, just gate symbols) for a circuit that uses only one XOR gate to implement both XOR and XNOR functions. The symbol for the CMOS XOR gate is shown below, having inputs a, a (NOT a), b, and b (NOT b). A signal S should be used to select between the XOR and XNOR function. You can use any additional INV, MUX, NAND and NOR gates needed to implement this function. The completed gate should only have inputs M, N, and S and output Z such that: if S = 0, Z = M XOR N if S = 1, Z = M XNOR N a a b b XOR s 0 1 2:1 MUX out out XOR symbol 2:1 MUX ...
Sveriges lantbruksuniversitet, CMPT 150
Excerpt: ... CMPT 150 In-Lab assignment, Logic Works version BUILDING CIRCUIT DIAGRAMS 1. Launch LogicWorks 4.0/5.0. 2. The screen display includes a menu bar, two tool bars, a status bar, a timing window and a parts palette, in addition to the main screen on which a digital design is placed. 3. Select the View pulldown menu, and then click on each of the options to determine where each of the tool bars, display bar, timing window, and parts palette are located. 4. Close the simulation tool bar and the timing window. You will not need these for now. 5. At the top of the parts palette window, the phrase ALL LIBRARIES should be displayed. Change this to read Simulation Gates.clf . A list of gate level components will appear in the display underneath. 6. This tutorial will construct a circuit that implements the boolean functions: s = (x y ) z c = xy + z(x y ) 7. From the expressions, we will require XOR gate s, AND gates and OR gates. In particular,we will use only 2-input gates. 8. Scroll down the pa ...
IUPUI, N 301
Excerpt: ... e associated output values 5 Gates Six types of gates NOT AND OR XOR NAND NOR Typically, logic diagrams are black and white with gates distinguished only by their shape We use color for emphasis (and fun) 6 NOT Gate A NOT gate accepts one input signal (0 or 1) and returns the opposite signal as output Figure 4.1 Various representations of a NOT gate 7 AND Gate An AND gate accepts two input signals If both are 1, the output is 1; otherwise, the output is 0 Figure 4.2 Various representations of an AND gate 8 OR Gate An OR gate accepts two input signals If both are 0, the output is 0; otherwise, the output is 1 Figure 4.3 Various representations of a OR gate 9 XOR Gate An XOR gate accepts two input signals If both are the same, the output is 0; otherwise, the output is 1 Figure 4.4 Various representations of an XOR gate 10 XOR Gate Note the difference between the XOR gate and the OR gate; they differ only in one input situation When both input signals are 1, the OR gate ...
Sveriges lantbruksuniversitet, CMPT 150
Excerpt: ... nctions: s = (x y ) z c = xy + z(x y ) 8. From the expressions, we will require XOR gate s, AND gates and OR gates. In particular, we will use only 2-input gates. 9. Scroll down the parts palette window until the XOR-2 component is located. Note that components are listed in alphabetical order. The number following the gate name indicates the number of inputs. 10. Double-Click on the XOR-2 component name and move your cursor onto the design screen (the one with the grid displayed). You will notice that your cursor changes to the graphical representation of a 2 input XOR gate . Position this image somewhere near the centre and top of the design screen, and click your left mouse button. 11. A copy of the XOR gate will be placed on the design sheet, but you will continue to have a XOR gate attached to your cursor. Place this second XOR gate to the right of the first, making sure that no signal leads are touching, and left click your mouse. 12. A second XOR gate will now be on your design sheet, and a t ...