• 364 Pages lec-all-n
    Lec-all-n

    School: W. Alabama

    E&CE 427: Digital System Engineering Mark Aagaard May 26, 2002 E&CE 427: 2002-Winter 0 2 Contents 1 VHDL Design LEC-02: Introduction to VHDL . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .

  • 21 Pages final
    Final

    School: W. Alabama

    E&CE 427 Final 2004t3 (Fall) Instructions and General Information 100 marks total Time limit: 3 hours Calculators are allowed No books, no notes, no computers If you need extra paper, request some from a proctor. Write neatly. The proctors and instr

  • 6 Pages lab-1
    Lab-1

    School: W. Alabama

    ECE 427 LAB #1 Due: Monday, September 23, 2002 11:59pm It is recommended that you read all of Handout #1 and pages 1 to 7 of Handout #2, "Intro to Synopsys", thoroughly before attempting the lab. Read all instructions and follow them carefully. Stud

  • 13 Pages midterm-sol
    Midterm-sol

    School: W. Alabama

    E&CE 427 Midterm Solution 2004t3 (Fall) Q1 (25 Marks) Short Answers Briey answer each of the following questions. Answers will be marked according to correctness, clarity, and conciseness. You may write in point-form; you do not need to write in com

  • 19 Pages toy_old
    Toy_old

    School: W. Alabama

    ECE 427 Project Deliverable Dataow Diagram Main Project (Bonus) Main Project (Regular) Due Date Friday, October 17, 2003 6:00pm Friday, November 7, 2003 11:59pm Friday, November 14, 2003 11:59pm The TOY CPU is a 16-instruction, 16-bit, microproces

  • 569 Pages 427lab1
    427lab1

    School: W. Alabama

    %!PSAdobe3.0 %Title: lab1.dvi %Creator: HPPS41A.DRV Version 4.10 %CreationDate: 05/03/99 16:03:53 %For: cgebotys %BoundingBox: 13 13 599 780 %Pages: 3 %PageOrder: Special %Requirements: %DocumentNeededFonts: (atend) %DocumentSuppliedFonts

  • 6 Pages lab-s00
    Lab-s00

    School: W. Alabama

    Professor C.Gebotys and R.Muresan .May/00 ECE427 LAB - INSTRUCTION SPECIFICATIONS _ Implement a register file of 16, 16bit registers (D0-D15). LT EQ GT a three bit condition register with the bit flag value '1' for condition 'true' and bit value '0'

  • 5 Pages lab2
    Lab2

    School: W. Alabama

    ECE 427 LAB #2 Due: Monday, October 4, 2004 11:59pm 1 Background Reading In addition to the handouts for Lab 1, it is recommended that you complete Tut-02x and read the Timing Simulation handout before attempting Lab 2. 2 Instructions Read all inst

  • 2 Pages all
    All

    School: W. Alabama

    Jan 31, 02 9:30 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package queue_pkg is subtype data is std_logic_vector(3 downto 0); function to_data(i : integer) return data; end queue_pkg; package body queue_pkg is function to_da

  • 87 Pages test2
    Test2

    School: W. Alabama

    116 40 90 65 92 61 110 41 148 120 49 68 120 181 53 167 76 179 127 109 35 82 178 137 134 80 72 106 147 136 141 176 163 86 175 100 109 88 97 84 130 158 75 68 116 150 171 47 71 112 112 162 89 51 138 168 106 187 102 165 80 201 193 106 180 92 198 113 76 7

  • 7 Pages lec-13-n
    Lec-13-n

    School: W. Alabama

    LEC-13 Preliminaries 250 LEC-13: Introduction to Performance Analysis Lecture Notes Sections: 4.2 4.4.3 University of Waterloo Dept of Electrical and Computer Engineering E&CE 427 Digital Systems Engineering 2002t3Fall Change Log .. . (*CHANGE

  • 659 Pages notes
    Notes

    School: W. Alabama

    E&CE 327: Digital Systems Engineering Course Notes (with Solutions) Mark Aagaard 2008t1Winter University of Waterloo Dept of Electrical and Computer Engineering Contents I Course Notes 1 VHDL 1.1 Introduction to VHDL . . . . . . . . . . . . . . . .

  • 4 Pages sol-6-2
    Sol-6-2

    School: W. Alabama

    P6.2 CRITICAL PATH AND FALSE PATH clock skew clock period setup time hold time 70 P6.2 Critical Path and False Path Find the critical path through the following circuit: b c d Answer: a f g e h i j l m k 71 a b c d f g e h i j k m l a b c 0 0

  • 2 Pages asn-09a-n
    Asn-09a-n

    School: W. Alabama

    ASN-09a Preliminaries 307 ASN-09a: Timing Analysis (II) Lecture Notes Sections: 5.7.5 5.7.8 University of Waterloo Dept of Electrical and Computer Engineering E&CE 427 Digital Systems Engineering 2002t3Fall 5.7.5 5.7.5.1 Short Answer Wires in F

  • 21 Pages asn-02-s-up2
    Asn-02-s-up2

    School: W. Alabama

    ASN-02 Preliminaries 1 ASN-02 Preliminaries 2 ASN-02: VHDL Semantics (*CHANGE ver2 (2002/09/16): First changes *) (*CHANGE ver3 (2002/09/29): Second changes *) (*CHANGE ver4 (2002/10/14): Third changes *) Changelog Lecture Notes Sections: 1.8.7

  • 332 Pages se_gui
    Se_gui

    School: W. Alabama

    Advanced Verification and Debugging ModelSim SE Graphical Interface Reference Version 6.0c GR-2 Copyright Mentor Graphics Corporation 2005 All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporatio

  • 1 Page elev
    Elev

    School: W. Alabama

    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;

  • 19 Pages ch-08-sol-1up
    Ch-08-sol-1up

    School: W. Alabama

    Chapter 8 Problems on Faults, Testing, and Testability P8.1 Based on Smith q14.9: Testing Cost A modern (circa 1995) production tester costs US$510 million. This cost is depreciated over the life of the tester (usually ve years in the States due to

  • 10 Pages ch-08-sol
    Ch-08-sol

    School: W. Alabama

    P8.2 TESTING COST AND TOTAL COST 92 3. The dimensions of the die to be tested are 20mm10mm. The wafers are 200mm in diameter. Fabricating a wafer with die costs $3000. The yield is 70%. Assume that the number of die per wafer is equal to wafer area

  • 10 Pages lec-24-up2
    Lec-24-up2

    School: W. Alabama

    E&CE 427: 2001-Fall: Lec-24 2 Lec-01 Introduction and overview Lec-02 VHDL syntax and semantics Lec-03 Design patterns Lec-04 Dataow diagrams Lec-05 State machine design in VHDL Lec-07 Design ow; from high-level model to register-transfer level Le

  • 3 Pages webequ~1
    Webequ~1

    School: W. Alabama

    1 Price-Performance-Power Equations 1.1 Performance f = 1 clockperiod 1 (Amdahl0s Law) Speed U p = (1F ractionenhanced)+ Speedup enhanced CPU time for a program = (# P clock cycles f or program) clock cycle time of = ( i IiCP Ii) clock cycle tim

  • 19 Pages final
    Final

    School: W. Alabama

    E&CE 427 Final Exam (Preliminary Solution) 2001 Fall Mark Aagaard NOTES: NOTE ON SOLUTION: This is a preliminary version of the solution. It is provided to give a rough indication of the solutions. Some additions and corrections were made by hand t

  • 35 Pages ee_cmd_help
    Ee_cmd_help

    School: W. Alabama

    # ATTENTION ENGINEERS! # Do NOT edit this file and check it in. The Docs group is responsible # for maintaining this file. Send all changes to docs@model.com. # # help command command help # The entries in this file have the form of a Tcl list.

  • 2543 Pages tutorial
    Tutorial

    School: W. Alabama

    %!PSAdobe3.0 %Title:(manual2001W.pdf) %Version:12 %DocumentData:Clean7Bit %LanguageLevel:2 %BoundingBox:00612792 %Pages:9 %DocumentProcessColors:(atend) %DocumentSuppliedResources:(atend) %EndComments %BeginDefaults %EndDefaults %BeginProlog %EndProl

  • 111 Pages makeup
    Makeup

    School: W. Alabama

    %!PS-Adobe-2.0 %Creator: dvips(k) 5.86 Copyright 1999 Radical Eye Software %Title: makeup.dvi %Pages: 12 %PageOrder: Ascend %BoundingBox: 0 0 596 842 %DocumentFonts: Times-Roman %EndComments %DVIPSWebPage: (www.radicaleye.com) %DVIPSCommandLine: dvip

  • 130 Pages cb-5
    Cb-5

    School: W. Alabama

    %!PS-Adobe-2.0 %Title: VHDL Cookbook\321Model_Org %Creator: Microsoft Word %CreationDate: Tuesday, 22 January 1991 %Pages: 7 %BoundingBox: ? ? ? ? %PageBoundingBox: 28 30 566 811 %For: petera %BeginProcSet: "(AppleDict md)" 68 0 %Title: "Laser Prep -

  • 3 Pages ModelSimSE_ds_7_04_2
    ModelSimSE_ds_7_04_2

    School: W. Alabama

    Advanced Verification and Debugging ModelSim SE D A T A S H E E T Major product features: High-performance RTL and gate-level optimizations Optimized native compiled architecture Single kernel simulator (SKS) technology PSL supported a

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