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Berkeley - EE 143
  • 30 Pages Tsuprem_simu
    Tsuprem_simu

    School: Berkeley

    TSUPREM4 Process Simulation Results for EE143 (Microfabrication) Lab Spring 2002 EE143 Microfabrication Week 1, Spring 2002 Initial 3" <100> WF Si substrate EE143 Microfabrication Week 1, Spring 2002 Boron Implantation (11B, 3.0x1012 cm-2, 60

  • 2 Pages teaching
    Teaching

    School: Berkeley

    College of Engineering Department of Electrical Engineering and Computer Sciences University of California, Berkeley EE143 teaches the senior EECS student the fundamentals of integrated circuit processing. Upon completion of this course, the student

  • 6 Pages iv7b
    Iv7b

    School: Berkeley

    PROJECT:NONAME LOT:1 WAFER:1 DIE:1 DEV:1 USER: ; COMMENT:; SETUP:"MOSFET" ID: D UNIT: SMU1 START: 0.05 STOP: 5 PNTS: 2 STEP: 4.95 ID: G UNIT: SMU2 START: 0 STOP: 12 PNTS: 121 STEP: 0.1 ID: S UNIT: SMU3 START: 0 STOP: 1 PNTS: 1 STEP:

  • 1 Page Grading_of_Prelab_Quiz
    Grading_of_Prelab_Quiz

    School: Berkeley

    EE143 Pre-Lab Quiz Grading Policy The following criteria will be used to evaluate the Pre-lab quizzes for students 1) No late quizzes will be allowed. Students who come to lab without a prepared pre-lab quiz will receive zero credit. Prepared Quiz is

  • 29 Pages Section 2 - Lithography
    Section 2 - Lithography

    School: Berkeley

    Section 2: Lithography Jaeger Chapter 2 Litho Reader EE143 Ali Javey The lithographic process EE143 Ali Javey Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon dioxide barrier layer Positive photoresist applie

  • 12 Pages Section 3 - Etching
    Section 3 - Etching

    School: Berkeley

    Section 3: Etching Jaeger Chapter 2 Reader Etch Process - Figures of Merit Etch rate Etch rate uniformity Selectivity Anisotropy EE143 Ali Javey Bias and anisotropy dm hf substrate df dm etching mask film Bias B d f - dm Complete Isotropic E

  • 45 Pages Section 4 - Thermal Oxidation
    Section 4 - Thermal Oxidation

    School: Berkeley

    Section 4: Thermal Oxidation Jaeger Chapter 3 EE143 - Ali Javey Properties of SiO2 Thermal SiO2 is amorphous. Weight Density = 2.20 gm/cm3 Molecular Density = 2.3E22 molecules/cm3 Crystalline SiO2 [Quartz] = 2.65 gm/cm3 SiO2 <Si> (1) Excellent E

  • 22 Pages Section 5 - Thin Film Deposition - part1
    Section 5 - Thin Film Deposition - Part1

    School: Berkeley

    Section 5: Thin Film Deposition part 1 : sputtering and evaporation Jaeger Chapter 6 EE143 Ali Javey Vacuum Basics 1. Units 1 atmosphere = 760 torr = 1.013x105 Pa 1 bar = 105 Pa = 750 torr 1 torr = 1 mm Hg 1 mtorr = 1 micron Hg 1Pa = 7.5 mt

  • 14 Pages Section 5 - Thin Film Deposition - part2
    Section 5 - Thin Film Deposition - Part2

    School: Berkeley

    Section 5: Thin Film Deposition Part 2: Chemical Methods Jaeger Chapter 6 EE143 Ali Javey Chemical Vapor Deposition (CVD) source chemical reaction film substrate More conformal deposition vs. PVD t Shown here is 100% conformal deposition t step

  • 34 Pages Section 6 - Ion Implantation
    Section 6 - Ion Implantation

    School: Berkeley

    Section 6: Ion Implantation Jaeger Chapter 5 EE143 Ali Javey Ion Implantation - Overview Wafer is Target in High Energy Accelerator Impurities "Shot" into Wafer Preferred Method of Adding Impurities to Wafers Wide Range of Impurity Species (Al

  • 19 Pages Section 7 - Diffusion - part 1
    Section 7 - Diffusion - Part 1

    School: Berkeley

    Section 7: Diffusion Jaeger Chapter 4 EE143 Ali Javey Surface Diffusion: Dopant Sources (a) Gas Source: AsH3, PH3, B2H6 BN Si BN Si (b) Solid Source (c) Spin-on-glass (d) Liquid Source. SiO2+dopant oxide EE143 Ali Javey Fick's First Law of Dif

  • 11 Pages Section 7 - Diffusion - part 2
    Section 7 - Diffusion - Part 2

    School: Berkeley

    Section 4: Diffusion part 2 Jaeger Chapter 4 EE143 Ali Javey Example : High Concentration Arsenic diffusion profile becomes box-like EE143 Ali Javey Summary of High-Concentration Diffusion If doping conc < ni: Use constant diffusivity solutions

  • 20 Pages Section 8 - Metallization
    Section 8 - Metallization

    School: Berkeley

    Section 8: Metallization Jaeger Chapter 7 EE143 Ali Javey Multilevel Metallization EE143 Ali Javey Multilevel Metallization Components FOX Si substrate ( InteMetal Oxide e.g. BPSG. Low-K dieletric) (e.g. PECVD Si Nitride) EE143 Ali Javey I

  • 7 Pages Section 9 - CMP
    Section 9 - CMP

    School: Berkeley

    Section 9: CMP EE143 Ali Javey Slide 9-1 Multilevel Interconnects Nonplanar Metallization EE143 Ali Javey Planar Metallization Slide 9-2 Surface Planarization Benefits for Lithography Processes: Lower Depth-of-Focus requirement Reduced opti

  • 8 Pages Section 10 - Layout
    Section 10 - Layout

    School: Berkeley

    Section 10: Layout Jaeger, Chapter 9 EE143 Ali Javey Slide 10-1 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter

  • 21 Pages Section 11 - Process Integration
    Section 11 - Process Integration

    School: Berkeley

    Section 11: Process Integration Jaeger Chapters 9, 11 EE143 Ali Javey Slide 11-1 Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE)

  • 63 Pages Section 12 - Devices
    Section 12 - Devices

    School: Berkeley

    Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon crystal in a two-dimensional

  • 47 Pages Section 2 - Lithography
    Section 2 - Lithography

    School: Berkeley

    Section 2: Lithography Jaeger Chapter 2 EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon dioxide barrier layer Positive photoresi

  • 3 Pages sems
    Sems

    School: Berkeley

  • 1 Page schedule
    Schedule

    School: Berkeley

    Weekly Lab Schedule (13 weeks) 1. Laboratory Sign-up (Prelab #1) 2. Orientation (Safety, Cleaning and General Information) (Prelab #2) 3. Photolithography: Mask I ACTV (Prelab #3) 4. Gate Oxidation (Prelab #4) 5. Poly-Si Deposition (Microlab) (Prelab

  • 3 Pages addendum
    Addendum

    School: Berkeley

    March 22, 2000 Addendum to Lab Report 1 Please read through the following additions to the existing lab report assignment. Q.2: There are 11 major processing steps for the devices we made in lab. These are shown below. For the MEMS process, the EXAC

  • 28 Pages chip_layout
    Chip_layout

    School: Berkeley

    Chip Layout: Device Sizes: Layout dimensions dimensions are in micrometers (1 m = 1 micrometer). All contact holes are 5 m x 5 m. Metal pads are 100 m x 100 m. The devices are listed below by device number: 1a) Resolution Test Patterns (1 per mask):

  • 23 Pages nmos_fab_process_desc
    Nmos_fab_process_desc

    School: Berkeley

    1 NMOS Fabrication Process Description Last modified by Alex Chediak on March 6, 2000. Please send comments and suggestions to him. Process Flow (Process Overview) Week 1: Starting Materials Week 2: Initial Oxidation - 5200 Week 3: Active Area Pho

  • 1 Page prelab01
    Prelab01

    School: Berkeley

    Prelab #1 Please arrange to sign up for a lab. A sign up sheet will be posted early in the morning following the first lecture. Lab sizes are limited to 8 students and the afternoon labs fill quickly so students are encouraged to sign up early. Updat

  • 1 Page prelab02
    Prelab02

    School: Berkeley

    Prelab #2 Description Although we do not start processing this week, this lab is very important. You will be learning your way around the laband the lab equipment and, most importantly, lab safety. In this lab you will accomplish the following:

  • 1 Page prelab03
    Prelab03

    School: Berkeley

    Prelab #3 Description This week we begin processing wafers. The wafers have already received their initial oxidation. This week, we will define the device active areas. Understand how the initial oxidation and the definition of the device active area

  • 1 Page prelab04
    Prelab04

    School: Berkeley

    Prelab #4 Last week we defined the active area where all devices will be built. This week, we grow the gate oxide using dry oxidation. Understand how the gate oxidation fits into the process flow. Read the above and all the associated links (the unde

  • 1 Page prelab05
    Prelab05

    School: Berkeley

    Prelab #5 This week of lab the TAs will deposit polysilicon on your wafers using a low pressure chemical vapor deposition (LPCVD) process. No student processing will occur this week. Instead, there will be a tour of the microlab located on the 4th fl

  • 1 Page prelab06
    Prelab06

    School: Berkeley

    Prelab #6 In this week's lab, we will we do the second of 4 lithography steps followed by an etching. This will define the gate polysilicon layer. Understand how poly definition fits into the process flow. Read the above and all the associated links

  • 1 Page prelab07
    Prelab07

    School: Berkeley

    Prelab #7 This week we will work with the furnaces to begin forming source and drain diffusions. Specifically, we will be depositing N+ dopants using spin-on-glass and high temperature anneal followed by a wet oxidation and a diffusion step. Understa

  • 1 Page prelab08
    Prelab08

    School: Berkeley

    Prelab #8 This week we will do another lithography followed by an etching step define contacts. Understand how the these step fit into the process flow. Since we have already done the lithography and oxide etch in prior labs, this week should go pret

  • 1 Page prelab09
    Prelab09

    School: Berkeley

    Prelab #9 This week we will evaporate aluminum on to our wafers. Understand how the these step fit into the process flow. This lab will take some time due to the delays associated with evacuating the evaporation process chamber. Read the above and al

  • 1 Page prelab10
    Prelab10

    School: Berkeley

    Prelab #10 This week we will define and sinter aluminum to finish our wafers. Understand how these steps fit into the process flow. This lab will take some time due to the lithography alignment and the furnace operation. Read the above and all the as

  • 1 Page prelab11
    Prelab11

    School: Berkeley

    Prelab #11 Last week we finished wafer processing and will move into the second half of the lab, device characterization. This week your first lab report on wafer processing is due. Before coming to class, you should understand the Metrics software i

  • 1 Page prelab12
    Prelab12

    School: Berkeley

    Prelab #12 Just like last week, you should understand the Metrics software interface to the measurement equipment. Metrics will be used to collect device measurement data. Students should also understand what parameters we are attempting to measure a

  • 1 Page prelab13
    Prelab13

    School: Berkeley

    Prelab #13 The device characterization lab report is due next week unless otherwise notified. Just like the past two weeks, you should understand the Metrics software interface to the measurement equipment. Metrics will be used to collect device meas

  • 12 Pages quizzes
    Quizzes

    School: Berkeley

    College of Engineering Department of Electrical Engineering and Computer Sciences University of California, Berkeley Below are your weekly quizzes. You should print out a copy of the quiz and complete it before your lab section. Bring in the complete

  • 35 Pages Section 6 - Ion Implantation
    Section 6 - Ion Implantation

    School: Berkeley

    Section 6: Ion Implantation Jaeger Chapter 5 EE143 Ali Javey Ion Implantation - Overview Wafer is Target in High Energy Accelerator Impurities Shot into Wafer Preferred Method of Adding Impurities to Wafers Wide Range of Impurity Species (Almo

  • 7 Pages Section 10 - Layout
    Section 10 - Layout

    School: Berkeley

    Section 10: Layout EE143 Ali Javey Slide 10-1 Layout Design Rules (1) Absolute-Value Design Rules * Use absolute distances (2) -based Design Rules EE143 Ali Javey Slide 10-2 2 Metal-Si Contact Hole 2 (same rule for Metal-poly) 2 Min. con

  • 3 Pages hw 5 solution
    Hw 5 Solution

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #5 SOLUTION 1. You would like to oxidize a 1-m radius cylindrical polysilicon rod as shown below via thermal oxidation at 1000C to form a 1-m-thick oxide sheath. 1 m 1 m Si SiO2 Si ? m P

  • 6 Pages hw 6 solutions
    Hw 6 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #6 SOLUTION 1. The cross-section below is to be etched via reactive ion etching (RIE). For this problem, assume that the RIE etch is 100% anisotropic and that it etches polysilicon at th

  • 4 Pages hw 7 solutions
    Hw 7 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #7 SOLUTION 1. An ion implanter with an accelerating voltage of 50 kV is used to implant the following ions into Si to an ion dose of 1015 ions/cm2: (1) B+; (2) B2+; (3) B2+ ; (4) (BF2)2

  • 5 Pages hw 8 solutions
    Hw 8 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #8 SOLUTION 1. The following pages comprise an actual pwell CMOS process flow with poly-to-poly capacitors. No details are spared in this flow; even equipment names are given, as are dia

  • 4 Pages hw 9 solutions
    Hw 9 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #9 SOLUTION 1. Referring to the layout and process flow in HW#8, answer the following questions. a) Why did we etch the oxide before well drive-in in step 5.2? To create p-well pattern f

  • 4 Pages hw 10 solutions
    Hw 10 Solutions

    School: Berkeley

    Course: Microfabrication Technology

  • 3 Pages Midterm 2 Solutions 03
    Midterm 2 Solutions 03

    School: Berkeley

    Course: Microfabrication Technology

    EE143 Midterm Exam #2 Solutions Problem 1 (a) (i )Let translational error be (xt, yt). After subtracting the translational error, we have: Top x y Right +3 -xt +3 - yt Center 0 0 Left -2 -xt +1 - yt Fall 2003 Bottom Since thermal run out/in error is antis

  • 9 Pages Midterm 2 04
    Midterm 2 04

    School: Berkeley

    Course: Microfabrication Technology

  • 11 Pages Midterm 2 Solutions 11
    Midterm 2 Solutions 11

    School: Berkeley

    Course: Microfabrication Technology

    EE143 Microfabrication Technology Spring 2011 Prof. J. Bokor Midterm Exam 2 Name: -=~- Signature: _ SID: _ l' CLOSED BOOK. TWO 8 1/2" X 11" SHEET OF NOTES, AND SCIENTIFIC POCKET CALCULATOR PERMITTED. MAKE SURE THE EXAM PAPER HAS PAGES. DO ALL WORK ON THE

  • 12 Pages Midterm 10
    Midterm 10

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 C. Nguyen MIDTERM EXAM March 18, 2010 NAME _ INSTRUCTIONS Read all of the instructions and all of the questions before beginning the exam. There are 4 problems on this midterm exam, totaling 100 points. The tentative credit for each part is given

  • 12 Pages Midterm 1 Solutions 12
    Midterm 1 Solutions 12

    School: Berkeley

    Course: Microfabrication Technology

    EE143 Microfabrication Technology Spring 2012 Prof. 1. Bokor Midterm Exam 1 Name: -~- Signature: _ SID: _ CLOSED BOOK. ONE 8 112" X 11" SHEET OF NOTES, AND SCIENTIFIC POCKET CALCULATOR PERMITTED. MAKE SURE THE EXAM PAPER HAS 12 PAGES. DO ALL WORK ON THE E

  • 10 Pages MIdterm 2 Solutions 12
    MIdterm 2 Solutions 12

    School: Berkeley

    Course: Microfabrication Technology

    EE143 Microfabrication Technology Spring 2012 Prof. J. Bokor Midterm Exam 2 Name: So lu+i 0 (\5 , -=~=-~- Signature: SID: _ - CLOSED BOOK. ONE 8 112" X 11" SHEET OF NOTES, AND SCIENTIFIC POCKET CALCULATOR PERMITTED. MAKE SURE THE EXAM PAPER HAS 10 PAGES.

  • 3 Pages Midterm 1 Solutions 04
    Midterm 1 Solutions 04

    School: Berkeley

    Course: Microfabrication Technology

    EE143 Fall 2004 Midterm 1 solutions Problem 1 (i ) Three lithography steps are used in this process flow. Mask 1: Pattern Poly-1 hinge plate Mask 2: Pattern the staple anchor openings through bottom PSG Mask 3: Pattern the Poly-2 staple (ii) Four CVD step

  • 18 Pages Final Exam 10
    Final Exam 10

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 C. Nguyen FINAL EXAM May 10, 2010 NAME _ INSTRUCTIONS Read all of the instructions and all of the questions before beginning the exam. There are 5 problems on this Final Exam, totaling 143 points. The tentative credit for each part is given to he

  • 15 Pages Final Exam Solutions 11
    Final Exam Solutions 11

    School: Berkeley

    Course: Microfabrication Technology

    -EE143 Microfabrication Technology Spring 2011 Prof. J. Bokor Final Exam Name: -~-Signature: - SID: -CLOSED BOOK. THREE 8 112" X 11" SHEET OF NOTES, AND SCIENTIFIC POCKET CALCULATOR PERMITTED. MAKE SURE THE EXAM PAPER HAS 15 PAGES. DO ALL WORK ON THE EXAM

  • 3 Pages Midterm 1 Solutions 03
    Midterm 1 Solutions 03

    School: Berkeley

    Course: Microfabrication Technology

    Midterm Exam #1 Solutions Problem 1 (a) Cross-section along B-B EE143, Fall F2003 Poly-Si Gate oxide Al SiO2 (FOX) p (channel stop) CVD SiO2 p (channel stop) p- substrate (b) Cross-section along C-C Al CVD SiO2 CVD SiO2 SiO2 (FOX) p (channel stop) n+ p (c

  • 14 Pages Exam 1 Solutions 08
    Exam 1 Solutions 08

    School: Berkeley

    Course: Microfabrication Technology

    UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 143 Professor Ali Javey Fall 2008 Exam 1 Answer Key Name: _ SID: 1337 _ Closed book. One sheet of notes is allowed. There are a total of 13 pag

  • 1 Page hw 4 solutions
    Hw 4 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #4 SOLUTION Issued: Thursday, Feb. 18, 2010 Due: Thursday, Feb. 25, 2010, 7:00 p.m. in the EE 143 homework box in 240 Cory 1. In HW#2, you created a process flow for fabricating a pn dio

  • 5 Pages hw 3 solutions
    Hw 3 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #3 Solution I. Lithography 1. Consider the overhead-view NMOS device pattern below obtained after S/D and gate lithography. Circle the misaligned areas. For each misalignment, state whet

  • 50 Pages Section 12 - Devices
    Section 12 - Devices

    School: Berkeley

    Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon crystal in a two-dimensional

  • 2 Pages idvg8b
    Idvg8b

    School: Berkeley

    PROJECT:NONAME LOT:1 WAFER:1 DIE:1 DEV:1 USER: ; COMMENT:; SETUP:"MOSFET" ID: D UNIT: SMU1 START: 0.05 STOP: 7 PNTS: 71 STEP: 0.1 ID: G UNIT: SMU2 START: 0 STOP: 3 PNTS: 61 STEP: 0.05 ID: S UNIT: SMU3 START: 0 STOP: 1 PNTS: 1 STEP:

  • 2 Pages idvg8c
    Idvg8c

    School: Berkeley

    PROJECT:NONAME LOT:1 WAFER:1 DIE:1 DEV:1 USER: ; COMMENT:; SETUP:"MOSFET" ID: D UNIT: SMU1 START: 0.05 STOP: 7 PNTS: 71 STEP: 0.1 ID: G UNIT: SMU2 START: 0 STOP: 3 PNTS: 61 STEP: 0.05 ID: S UNIT: SMU3 START: 0 STOP: 1 PNTS: 1 STEP:

  • 2 Pages idvg9c
    Idvg9c

    School: Berkeley

    PROJECT:NONAME LOT:1 WAFER:1 DIE:1 DEV:1 USER: ; COMMENT:; SETUP:"MOSFET" ID: D UNIT: SMU1 START: 0.05 STOP: 7 PNTS: 71 STEP: 0.1 ID: G UNIT: SMU2 START: 0 STOP: 3 PNTS: 61 STEP: 0.05 ID: S UNIT: SMU3 START: 0 STOP: 1 PNTS: 1 STEP:

  • 3 Pages rvg8c
    Rvg8c

    School: Berkeley

    PROJECT:NONAME LOT:1 WAFER:1 DIE:1 DEV:1 USER: ; COMMENT:; SETUP:"MOSFET" ID: D UNIT: SMU1 START: 0.05 STOP: 7 PNTS: 71 STEP: 0.1 ID: G UNIT: SMU2 START: 0 STOP: 12 PNTS: 121 STEP: 0.1 ID: S UNIT: SMU3 START: 0 STOP: 1 PNTS: 1 STEP:

  • 25 Pages EE143_2
    EE143_2

    School: Berkeley

    EE 143 Optical Lithography Lecture, A.R. Neureuther, Sp 2006 Ver: 02/01/2009 Qualitative Explanation of image degradation by lens Mask + 2 +1 0 lens wafer plane -1 parallel optical beam grating with spatial frequency 1/P S -2 P sin = n n

  • 14 Pages EE143_1
    EE143_1

    School: Berkeley

    EE 143 Optical Lithography Lecture, A.R. Neureuther, Sp 2006 Ver: 02/01/2009 Optical Projection Printing and Modeling Overview of optical lithography, concepts, trends Basic Parameters and Effects (1-14) Resolution Depth of Focus; Proximity, MEEF,

  • 13 Pages EE143_3
    EE143_3

    School: Berkeley

    EE 143 Optical Lithography Lecture, A.R. Neureuther, Sp 2006 Ver: 02/01/2009 OPC Scatterbars or Assist Features Main Feature The isolated main pattern now acts somewhat more like a periodic line and space pattern which has a higher quality image es

  • 2 Pages W08_Quiz
    W08_Quiz

    School: Berkeley

    EE143 Week 8: Suggest Pre-Lab Quiz Solution 2006/02/20 Shong Yin (1) What layer will we be cutting through today? Intermediate oxide (2) What etchant (and what concentration) will we be using? What is the nominal etchrate? Assuming 1400 of the layer and u

  • 8 Pages Characterization schemes
    Characterization Schemes

    School: Berkeley

    2A & 2B 4155B - SHEET Mode SMU4 F1P SMU1 S1P SMU1 F1P SMU4 S1P S2P SMU2 F2P SMU3 Settings Stimulus F1P (SMU4) Current Measure Current Sweep Sweep Start -0.1 Stop 0.1 Compliance 5 F2P (SMU3) S1P (SMU1) S2P (SMU1) Voltage Current Current Voltage Voltage Con

  • 1 Page W05_Student_Instructions
    W05_Student_Instructions

    School: Berkeley

    Week 5 Student Checklist Created: Vidya Varadrajan, Fall 2005 Modified: Shong Yin, Spring 2006 Student checklist In this week, you will be going to the microlab for a tour of the available tools in the Microfabrication Facility at Cory Hall. The Head TA w

  • 1 Page EE143_Lab_Assignments
    EE143_Lab_Assignments

    School: Berkeley

    Updated01/31/08 JohnWyrwas M AndrewStucki Guanxi Chen Willis Lin Arun Gupta Kenneth Leung Henry H. Chen Shin-Yeuan Wang Bao Ngoc Tong PeterMatheu W AlanDeguzman Mark William Landry Michael Chung Wang PeterMatheu Th KevinXiahuiWang Eric Christopher Stone C

  • 34 Pages CourseInfo
    CourseInfo

    School: Berkeley

    EE143 Microfabrication Technology Professor: Ali Javey ajavey@eecs.berkeley.edu 506 Cory Hall (510) 643-7263 SangHoon Lee, leesh@me.berkeley.edu Peter Matheu, peter_matheu@berkeley.edu John Wyrwas, jwyrwas@eecs.berkeley.edu http:/www-inst.eecs.berkeley.ed

  • 4 Pages W02_Lab_Tutorial
    W02_Lab_Tutorial

    School: Berkeley

    EE 143 Fall 06 Lab Tutorial EE 143 Fall 06 Lab Tutorial Goal I am here to: - discuss the lab-works before you enter and work in the lab - help you understand the lab better EE 143 Microfabrication Technology Fall 2006 - Lab Tutorial September 1, 2006 - he

  • 10 Pages Sp09_midterm1_with_solutions
    Sp09_midterm1_with_solutions

    School: Berkeley

    UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE143 Spring 2009 Professor Ali Javey Exam 1 Name: _ SID: _ Closed book. One sheet of notes is allowed. There are a total of 10 pages on this exam,

  • 4 Pages hw 1 solutions
    Hw 1 Solutions

    School: Berkeley

    Course: Microfabrication Technology

  • 5 Pages hw 2 solutions
    Hw 2 Solutions

    School: Berkeley

    Course: Microfabrication Technology

    EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #2 Solution I. Process Flow/Layout to Cross-Section 1. Consider the cross-section of a device shown below: a. What kind of device is this? A pn diode b. Generate a possible process flowc

  • 12 Pages Midterm 1 Solutions 11
    Midterm 1 Solutions 11

    School: Berkeley

    Course: Microfabrication Technology

    EE143 Microfabrication Technology Midterm Exam 1 Name: -~- Signature: SID: _ _ CLOSED BOOK. ONE 8 112" X 11" SHEET OF NOTES, AND SCIENTIFIC POCKET CALCULATOR PERMITTED. TIME ALLOTTED: 80 MINUTES b. Why is contact printing unsuitable for high-volume manufa

  • 8 Pages Quintel
    Quintel

    School: Berkeley

    Quintel Mask Aligner (quintel) 1.0 1.0 Title Quintel Q4000 Mask Aligner 2.0 2.0 Purpose The Quintel Q4000 MA (Mask Aligner) is a top and bottom side contact lithography printer with the video-view split field microscope used for fine line lithograph

  • 13 Pages EE143_Midterm1_Solns_Sp08
    EE143_Midterm1_Solns_Sp08

    School: Berkeley

  • 1 Page HW1
    HW1

    School: Berkeley

    HW1,EE143Spring2008 Due:Tuesday,Feb.5 Answerthefollowingquestionsasconciselyaspossible. a. Name(i)oneelemental,(ii)oneIIIV,andoneIIVIcompoundsemiconductor b. Whatisthedifferencebetweenacrystallineandpolycrystallinematerial? c. Giveaworddefinitionof

  • 57 Pages Sec2-Lithography-3
    Sec2-Lithography-3

    School: Berkeley

    Section 2: Lithography Jaeger Chapter 2 Litho Reader EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon dioxide barrier layer Posit

  • 22 Pages Sec5-ThinFilmDeposition-part1
    Sec5-ThinFilmDeposition-part1

    School: Berkeley

    Section 6: Thin Film Deposition part 1 : sputtering and evaporation Jaeger Chapter 6 EE143 Ali Javey Vacuum Basics 1. Units 1 atmosphere = 760 torr = 1.013x105 Pa 1 bar = 105 Pa = 750 torr 1 torr = 1 mm Hg 1 mtorr = 1 micron Hg 1Pa = 7.5 mt

  • 19 Pages Sec7-Diffusion-part1
    Sec7-Diffusion-part1

    School: Berkeley

    Section 7: Diffusion Jaeger Chapter 4 EE143 Ali Javey Dopant Diffusion Sources (a) Gas Source: AsH3, PH3, B2H6 BN Si BN Si (b) Solid Source (c) Spin-on-glass (d) Liquid Source. SiO2+dopant oxide EE143 Ali Javey Ficks First Law of Diffusion N

  • 7 Pages Sec9-CMP
    Sec9-CMP

    School: Berkeley

    Section 9: CMP EE143 Ali Javey Slide 9-1 Multilevel Interconnects Nonplanar Metallization Planar Metallization EE143 Ali Javey Slide 9-2 Surface Planarization Benefits for Lithography Processes: Lower Depth-of-Focus requirement Reduced opt

  • 2 Pages syllabus_Sp08_rev.012808
    Syllabus_Sp08_rev.012808

    School: Berkeley

    UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Professor Ali Javey 506 Cory Hall, ajavey@eecs.berkeley.edu MICROFABRICATION TECHNOLOGY EECS143, Spring 2008 T.A.s: SangHoon Lee: leesh@me.ber

  • 69 Pages Sec12-Devices
    Sec12-Devices

    School: Berkeley

    Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Sili Silicon crystal in li a two-dim

  • 44 Pages Sec4-ThermalOxidation
    Sec4-ThermalOxidation

    School: Berkeley

    Section 4: Thermal Oxidation Jaeger Chapter 3 EE143 - Ali Javey Properties of SiO2 Thermal SiO2 is amorphous. Weight Density = 2.20 gm/cm3 Molecular Density = 2.3E22 molecules/cm3 Crystalline SiO2 [Quartz] = 2.65 gm/cm3 SiO2 <Si> (1) Excellent E

  • 23 Pages Sec3-Etching
    Sec3-Etching

    School: Berkeley

    Section 3: Etching Jaeger Chapter 2 Reader Etch Process - Figures of Merit Etch rate Etch rate uniformity Selectivity Anisotropy EE143 Ali Javey Bias and anisotropy dm hf substrate df dm etching mask film Bias B d f dm Complete Isotropic Et

  • 7 Pages Sec10-Layout
    Sec10-Layout

    School: Berkeley

    Section 10: Layout EE143 Ali Javey Slide 10-1 Layout Design Rules (1) Absolute-Value Design Rules * Use absolute distances (2) -based Design Rules EE143 Ali Javey Slide 10-2 2 Metal-Si Contact Hole 2 2 (same rule for Metal-poly) Min. contac

  • 13 Pages Sec5-ThinFilmDeposition-part2
    Sec5-ThinFilmDeposition-part2

    School: Berkeley

    Section 5: Thin Film Deposition Part 2: Chemical Methods Jaeger Chapter 6 EE143 Ali Javey Chemical Vapor Deposition (CVD) source chemical reaction film substrate More conformal deposition vs. PVD t Shown here is 100% conformal deposition t step

  • 35 Pages Sec6-IonImplantation
    Sec6-IonImplantation

    School: Berkeley

    Section 6: Ion Implantation Jaeger Chapter 5 EE143 Ali Javey Ion Implantation - Overview Wafer is Target in High Energy Accelerator Impurities Shot into Wafer Preferred Method of Adding Impurities to Wafers Wide Range of Impurity Species (Almo

  • 1 Page W03_Student_Instructions
    W03_Student_Instructions

    School: Berkeley

    Week 3 Student Checklist Student checklist Read and get basic understanding of the overall Process Flow. This can be found at the lab webpage: http:/www-inst.eecs.berkeley.edu/~ee143/sp06/lab/fabrication_process_flow.pdf Read the detailed Process F

  • 1 Page W03_Student_Measurement
    W03_Student_Measurement

    School: Berkeley

    EE143 Lab Week 3 Measurement Checklist: 1) Lithography Time (sec) Softbake: Exposure: Developer: Hardbake: Linewidth (um) Nominal Measured % Overetch 2 3 4 8 Notes: 1 tick mark in the right eyepiece of microscope is 1um under 100X 2) Etch: Oxide Etch

  • 27 Pages lec1_Sec1-Intro_to_Materials-1
    Lec1_Sec1-Intro_to_Materials-1

    School: Berkeley

    EECS143 Microfabrication Technology Professor Ali Javey Introduction to Materials Lecture 1 Evolution of Devices Yesterdays Transistor (1947) Todays Transistor (2006) Why Semiconductors? Conductors e.g Metals Insulators e.g. Sand (SiO2) Sem

  • 1 Page signature_form
    Signature_form

    School: Berkeley

    EECS 143 Lab Report 1 Academic Honesty Form Fall 2008 By signing below, I attest that I have read and have adhered to the policies and guidelines discussed in the EECS Departmental Policy on Academic Dishonesty, as found at: http:/www-inst.eecs.berk

  • 2 Pages expected_mems_data
    Expected_mems_data

    School: Berkeley

    Expected MEMS data

  • 1 Page EE143_Lab_Assignments
    EE143_Lab_Assignments

    School: Berkeley

    Updated01/31/08 JohnWyrwas M AndrewStucki Guanxi Chen Willis Lin Arun Gupta Kenneth Leung Henry H. Chen Shin-Yeuan Wang Bao Ngoc Tong PeterMatheu W AlanDeguzman Mark William Landry Michael Chung Wang PeterMatheu Th KevinXiahuiWang Eric Christopher

  • 47 Pages Sec2-Lithography
    Sec2-Lithography

    School: Berkeley

    Section 2: Lithography Jaeger Chapter 2 EE143 Ali Javey Slide 5-1 The lithographic process EE143 Ali Javey Slide 5-2 Photolithographic Process (a) (b) (c) (d) (e) (f) (g) Substrate covered with silicon dioxide barrier layer Positive photoresi

  • 3 Pages Sample_Exam_1_Answers
    Sample_Exam_1_Answers

    School: Berkeley

    a) The intrinsic carrier concentration is calculated by integrating the Fermi function / density of states function product. Using this fact, explain why the intrinsic carrier concentration increases with increasing temperature. The Fermi function br

  • 1 Page EE143quiz1-wed-ans
    EE143quiz1-wed-ans

    School: Berkeley

    EE 143: Lab Quiz 1 Fall 2008, University of California, Berkeley 1. Which type of photoresist (positive or negative) do we use in this lab? What happens to this type of resist in the areas that are exposed to light? (2 points) 2. a) Which type of o

  • 1 Page EE143quiz1-fri-ans
    EE143quiz1-fri-ans

    School: Berkeley

    .renniht ti sekam gnihcte-revo os ,dnalsi na si enil eht snaem tsiser evitageN over-etched under-etched Name: Fall 2008, University of California, Berkeley EE 143: Lab Quiz 1 1. Why was it important to soak the wafers in Piranha before putting th

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