• 11 Pages day9_6up
    Day9_6up

    School: Caltech

    CS137: Electronic Design Automation Bit-Level Addition LUT Cascades Today For Sums Day 9: January 30, 2006 Parallel Prefix Applications 1 FSMs SATADD Data Forwarding Pointer Jumping Applications 2 CALTECH CS137 Winter2006 - DeHon CA

  • 61 Pages day4
    Day4

    School: Caltech

    CS137: Electronic Design Automation Day 4: January 14, 2004 Two-Level Logic-Synthesis CALTECH CS137 Winter2004 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements CALTECH CS137 Winter20

  • 30 Pages Day10
    Day10

    School: Caltech

    CS137: Electronic Design Automation Day 10: May 5, 2004 Processor Verification CALTECH CS137 Spring2004 - DeHon Today Specification/Implementation Abstraction Functions Correctness Condition Verification Self-Consistency CALTECH CS137 Spring

  • 56 Pages day13
    Day13

    School: Caltech

    CS137: Electronic Design Automation Day 13: March 1, 2003 Scheduling Introduction CALTECH CS137 Winter2004 - DeHon Today Scheduling Basic problem variants branching bounds and pruning CALTECH CS137 Winter2004 - DeHon General Problem Resou

  • 36 Pages Day13
    Day13

    School: Caltech

    CS137: Electronic Design Automation Day 13: May 17, 2004 Modern SAT Solvers (Chaff) 1 CALTECH CS137 Spring2004 - DeHon Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts 2 CALTECH CS137 Spring2004 - DeHon Problem

  • 5 Pages day15_6up
    Day15_6up

    School: Caltech

    CS137: Electronic Design Automation Devadas Wrighton Today SAT Partitioning Day 15: November 4, 2005 SAT for Partitioning 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Partitioning Problem Given: netlist of interconnect c

  • 21 Pages day1_2up
    Day1_2up

    School: Caltech

    CS137: Electronic Design Automation Day 1: January 5, 2004 Introduction CALTECH CS137 Winter2004 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millions->billions of devices used in everything billion dollar busines

  • 9 Pages day22_6up
    Day22_6up

    School: Caltech

    CS137: Electronic Design Automation Routing Pathfinder Today Day 22: December 2, 2005 Routing 2 (Pathfinder) graph based global routing simultaneous global/detail 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Global Rou

  • 2 Pages assign1
    Assign1

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Assignment #1 Wednesday, January 5 Due: Friday, January 16, 11:59pm. Resources You are free to use any books, ar

  • 4 Pages assign5
    Assign5

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #5 Monday, November 21 Due: Wednesday, December 7, 11:59pm PST. Resources You are free to use any books,

  • 39 Pages Day6
    Day6

    School: Caltech

    CS137: Electronic Design Automation Day 6: April 19, 2002 Static Timing Analysis CALTECH CS137 Spring2004 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus Delay-justified paths Tim

  • 50 Pages day6
    Day6

    School: Caltech

    CS137: Electronic Design Automation Day 6: January 26, 2004 Sequential Optimization (FSM Encoding) CALTECH CS137 Winter2004 - DeHon Today Encoding Input Output State Encoding exact two-level CALTECH CS137 Winter2004 - DeHon Input Encoding

  • 18 Pages Day13_2up
    Day13_2up

    School: Caltech

    CS137: Electronic Design Automation Day 13: May 17, 2004 Modern SAT Solvers (Chaff) 1 CALTECH CS137 Spring2004 - DeHon Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts 2 CALTECH CS137 Spring2004 - DeHon 1 Proble

  • 14 Pages day20_6up
    Day20_6up

    School: Caltech

    CS137: Electronic Design Automation Scheduling Today Force-Directed SAT/ILP Branch-and-Bound Day 20: November 23, 2005 Scheduling Variants and Approaches 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Last Time Resourc

  • 7 Pages day12_6up
    Day12_6up

    School: Caltech

    CS137: Electronic Design Automation Previously Cover (map) LUTs for minimum delay solve optimally Day 12: October 28, 2005 Covering and Retiming Retiming for minimum clock period solve optimally 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137

  • 25 Pages Day9
    Day9

    School: Caltech

    CS137: Electronic Design Automation Day 9: May 2, 2004 FSM Equivalence Checking CALTECH CS137 Spring2004 - DeHon Today Sequential Verification DFA equivalence Issues Extracting STG Valid state reduction Incomplete Specification Solutions

  • 53 Pages day3
    Day3

    School: Caltech

    CS137: Electronic Design Automation Day 3: January 12, 2004 Clustering (LUT Mapping, Delay) CALTECH CS137 Winter2004 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioning

  • 42 Pages day12
    Day12

    School: Caltech

    CS137 Electronic Design Automation Day 9: February 25, 2004 Placement II Andr DeHon, Michael Wrighton Today Continue with Placement Improving Quality Avoiding local minima Simulated Annealing Exhaustive (Branch-and-bound) Techniques: DeH

  • 39 Pages Day5
    Day5

    School: Caltech

    CS137: Electronic Design Automation Day 5: April 12, 2004 Covering and Retiming 1 CALTECH CS137 Spring2004 - DeHon Previously Cover (map) LUTs for minimum delay solve optimally Retiming for minimum clock period solve optimally Simultaneous

  • 38 Pages day14
    Day14

    School: Caltech

    CS137: Electronic Design Automation Day 14: March 3, 2004 Scheduling Heuristics and Approximation CALTECH CS137 Winter2004 - DeHon Today Scheduling Force-Directed List-Scheduling Approximation Algorithms CALTECH CS137 Winter2004 - DeHon Last

  • 74 Pages day2
    Day2

    School: Caltech

    CS137: Electronic Design Automation Day 2: January 7, 2004 Covering CALTECH CS137 Winter2004 - DeHon Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique show off special cas

  • 15 Pages Day10_2up
    Day10_2up

    School: Caltech

    CS137: Electronic Design Automation Day 10: May 5, 2004 Processor Verification CALTECH CS137 Spring2004 - DeHon Today Specification/Implementation Abstraction Functions Correctness Condition Verification Self-Consistency CALTECH CS137 Spring

  • 18 Pages day3_6up
    Day3_6up

    School: Caltech

    CS137: Electronic Design Automation Simplifying Structure K-LUT can implement any K-input function Day 3: September 29, 2005 Clustering (LUT Mapping, Delay) 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 4 Today How do we map

  • 25 Pages day9_2up
    Day9_2up

    School: Caltech

    CS137: Electronic Design Automation Day 9: February 9, 2004 Partitioning (Intro, KLFM) CALTECH CS137 Winter2004 - DeHon Today Partitioning why important practical attack variations and issues CALTECH CS137 Winter2004 - DeHon 1 Motivation (1

  • 2 Pages project
    Project

    School: Caltech

    CS137b California Institute of Technology Department of Computer Science Electronic Design Automation CS137b, Spring 2004 Spring 2004 Spring Project Monday, March 29 Project The center point for the Spring term will be a major, student chosen des

  • 9 Pages day13_6up
    Day13_6up

    School: Caltech

    CS137: Electronic Design Automation Partitioning Today why important practical attack variations and issues Day 13: October 31, 2005 Partitioning (Intro, KLFM) 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Motivation (1)

  • 31 Pages day4_2up
    Day4_2up

    School: Caltech

    CS137: Electronic Design Automation Day 4: January 14, 2004 Two-Level Logic-Synthesis CALTECH CS137 Winter2004 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements CALTECH CS137 Winter20

  • 11 Pages day21_6up
    Day21_6up

    School: Caltech

    CS137: Electronic Design Automation Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer Day 21: November 28, 2005 Routing 1 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Routing Problem Wher

  • 13 Pages Day3_2up
    Day3_2up

    School: Caltech

    CS137: Electronic Design Automation Day 3: April 5, 2004 Concept Generation CALTECH CS137 Spring2004 - DeHon Today Specifications/requirements/goals Concept Generation CALTECH CS137 Spring2004 - DeHon Specification Before can start solving N

  • 9 Pages day6_6up
    Day6_6up

    School: Caltech

    CS137: Electronic Design Automation Today Topological Worst Case not adequate (too conservative) Day 6: October 10, 2005 Static Timing Analysis and Multi-Level Speedup Sensitization Conditions Timed Calculus Delay-justified paths Timed-PODEM

  • 4 Pages assign2
    Assign2

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Assignment #2 Wednesday, January 21 Due: Friday, February 6, 11:59pm. Resources You are free to use any books, a

  • 9 Pages day5_6up
    Day5_6up

    School: Caltech

    CS137: Electronic Design Automation Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Day 5: October 7, 2005 Multi-level Synthesis Boolean Division Higher quality division Speed

  • 11 Pages day5_2up
    Day5_2up

    School: Caltech

    CS137: Electronic Design Automation Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Day 5: January 21, 2004 Multi-level Synthesis Boolean Division Higher quality division Spee

  • 4 Pages assign2
    Assign2

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #2 Monday, October 10 Due: Friday, October 21, 11:59pm. Resources You are free to use any books, articles

  • 31 Pages day15_2up
    Day15_2up

    School: Caltech

    CS137: Electronic Design Automation Day 15: March 8, 2002 Routing 1 CALTECH CS137 Winter2004 - DeHon Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer CALTECH CS137 Winter2004 - DeHon 1 Routing Problem Where

  • 13 Pages day2_2up
    Day2_2up

    School: Caltech

    CS137: Electronic Design Automation Why covering now? Nice/simple cost model problem can be solved well somewhat clever solution Day 2: September 28, 2005 Covering general/powerful technique show off special cases harder/easier cases show

  • 34 Pages day7_2up
    Day7_2up

    School: Caltech

    CS137: Electronic Design Automation Day 7: February 3, 2002 Retiming CALTECH CS137 Winter2004 - DeHon Today Retiming Cycle time (clock period) C-slow Initial states Register minimization Necessary delays (time permitting) CALTECH CS137 Wint

  • 9 Pages day14_6up
    Day14_6up

    School: Caltech

    CS137: Electronic Design Automation Today Alternate views of partitioning Two things we can solve optimally Day 14: November 2, 2005 Partitioning 2 (spectral, network flow, replication) 1 CALTECH CS137 Fall2005 - DeHon (but dont exactly solve o

  • 2 Pages assign5
    Assign5

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Assignment #5 Monday, March 8 Due: Wednesday, March 17, 4:59pm. Resources You are free to use any books, article

  • 7 Pages day16_6up
    Day16_6up

    School: Caltech

    CS137: Electronic Design Automation Today Placement Problem Partitioning Placement Quadrisection Refinement Day 16: November 9, 2005 Placement (Intro, Constructive) 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Placement

  • 19 Pages day14_2up
    Day14_2up

    School: Caltech

    CS137: Electronic Design Automation Day 14: March 3, 2004 Scheduling Heuristics and Approximation CALTECH CS137 Winter2004 - DeHon Today Scheduling Force-Directed List-Scheduling Approximation Algorithms CALTECH CS137 Winter2004 - DeHon Last

  • 8 Pages day9_6up
    Day9_6up

    School: Caltech

    CS137: Electronic Design Automation Today Faults in Logic Error Detection Schemes Optimization Problem Day 9: October 17, 2005 Fault Detection CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon Problem Gates, wires, memories: bui

  • 22 Pages day8_2up
    Day8_2up

    School: Caltech

    CS137: Electronic Design Automation Day 8: February 4, 2004 Fault Detection CALTECH CS137 Winter2004 - DeHon Today Faults in Logic Error Detection Schemes Optimization Problem CALTECH CS137 Winter2004 - DeHon 1 Problem Gates, wires, memorie

  • 2 Pages assign1
    Assign1

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #1 Wednesday, September 28 Due: Friday, October 7, 11:59pm. Resources You are free to use any books, arti

  • 8 Pages day8_6up
    Day8_6up

    School: Caltech

    outline Background Reliable State Machines Dr. Gary R Burke California Institute of Technology Jet Propulsion Laboratory 10/14/2005 Caltech 1 JPL MER example JPL FPGA/ASIC Process Procedure Guidelines State machines Traditional Highly Rel

  • 3 Pages final
    Final

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2002 Winter 2002 Assignment #4 Monday, March 11 Due: Wednesday, March 20, 5:00pm. Resources You are free to use any books, articl

  • 70 Pages day11_audio
    Day11_audio

    School: Caltech

    CS137: Electronic Design Automation Day 11: October 21, 2005 Retiming 1 CALTECH CS137 Fall2005 - DeHon Today Retiming Cycle time (clock period) C-slow Initial states Register minimization Necessary delays (time permitting) 2 CALTECH CS137 F

  • 52 Pages day10_audio
    Day10_audio

    School: Caltech

    CS137: Electronic Design Automation Day 10: October 19, 2005 Modern SAT Solvers ({z}Chaff, GRASP,miniSAT) 1 CALTECH CS137 Fall2005 - DeHon Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts Learning 2 CALTECH CS13

  • 51 Pages day9_audio
    Day9_audio

    School: Caltech

    CS137: Electronic Design Automation Day 9: October 17, 2005 Fault Detection CALTECH CS137 Fall2005 - DeHon Today Faults in Logic Error Detection Schemes Optimization Problem CALTECH CS137 Fall2005 - DeHon Problem Gates, wires, memories: bui

  • 49 Pages day7_audio
    Day7_audio

    School: Caltech

    CS137: Electronic Design Automation Day 7: October 12, 2005 Sequential Optimization (FSM Encoding) 1 CALTECH CS137 Fall 2005 - DeHon Today Encoding Input Output State Encoding "exact" two-level 2 CALTECH CS137 Fall 2005 - DeHon Input Encod

  • 49 Pages day6_audio
    Day6_audio

    School: Caltech

    CS137: Electronic Design Automation Day 6: October 10, 2005 Static Timing Analysis and Multi-Level Speedup 1 CALTECH CS137 Fall2005 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus

  • 56 Pages day5_audio
    Day5_audio

    School: Caltech

    CS137: Electronic Design Automation Day 5: October 7, 2005 Multi-level Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Boolean Divisio

  • 61 Pages day4_audio
    Day4_audio

    School: Caltech

    CS137: Electronic Design Automation Day 4: October 5, 2005 Two-Level Logic-Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements 2 CALTECH CS137 Fall200

  • 103 Pages day3_audio
    Day3_audio

    School: Caltech

    CS137: Electronic Design Automation Day 3: September 29, 2005 Clustering (LUT Mapping, Delay) 1 CALTECH CS137 Fall2005 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioni

  • 45 Pages day1_audio
    Day1_audio

    School: Caltech

    CS137: Electronic Design Automation Day 1: September 26, 2005 Introduction CALTECH CS137 Fall2005 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millionsbillions of devices used in everything billion dollar business

  • 41 Pages day12_audio
    Day12_audio

    School: Caltech

    CS137: Electronic Design Automation Day 12: October 28, 2005 Covering and Retiming 1 CALTECH CS137 Fall2005 - DeHon Previously Cover (map) LUTs for minimum delay solve optimally Retiming for minimum clock period solve optimally 2 CALTECH CS1

  • 53 Pages day13_audio
    Day13_audio

    School: Caltech

    CS137: Electronic Design Automation Day 13: October 31, 2005 Partitioning (Intro, KLFM) 1 CALTECH CS137 Fall2005 - DeHon Today Partitioning why important practical attack variations and issues 2 CALTECH CS137 Fall2005 - DeHon Motivation (1)

  • 40 Pages day11
    Day11

    School: Caltech

    CS137: Electronic Design Automation Day 11: May 13, 2002 Dual Objective Dynamic Programming CALTECH CS137 Spring2002 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for .and linear placement Two Dimens

  • 50 Pages day22_audio
    Day22_audio

    School: Caltech

    CS137: Electronic Design Automation Day 22: December 2, 2005 Routing 2 (Pathfinder) 1 CALTECH CS137 Fall2005 - DeHon Today Routing Pathfinder graph based global routing simultaneous global/detail 2 CALTECH CS137 Fall2005 - DeHon Global Rout

  • 64 Pages day21_audio
    Day21_audio

    School: Caltech

    CS137: Electronic Design Automation Day 21: November 28, 2005 Routing 1 1 CALTECH CS137 Fall2005 - DeHon Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer 2 CALTECH CS137 Fall2005 - DeHon Routing Problem Wher

  • 54 Pages day19_audio
    Day19_audio

    School: Caltech

    CS137: Electronic Design Automation Day 19: November 21, 2005 Scheduling Introduction 1 CALTECH CS137 Fall2005 - DeHon Today Scheduling Basic problem Variants List scheduling approximation 2 CALTECH CS137 Fall2005 - DeHon General Problem Re

  • 41 Pages day18_audio
    Day18_audio

    School: Caltech

    CS137: Electronic Design Automation Day 18: November 14, 2005 Dual Objective Dynamic Programming 1 CALTECH CS137 Fall2005 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for and linear placement Two Di

  • 41 Pages day17_audio
    Day17_audio

    School: Caltech

    CS137: Electronic Design Automation Day 17: November 11, 2005 Placement (Simulated Annealing) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo

  • 40 Pages day16_audio
    Day16_audio

    School: Caltech

    CS137: Electronic Design Automation Day 16: November 9, 2005 Placement (Intro, Constructive) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Problem PartitioningPlacement Quadrisection Refinement 2 CALTECH CS137 Fall2005 - DeHon Placement

  • 26 Pages day15_audio
    Day15_audio

    School: Caltech

    CS137: Electronic Design Automation Day 15: November 4, 2005 SAT for Partitioning 1 CALTECH CS137 Fall2005 - DeHon Today SAT Partitioning Devadas Wrighton 2 CALTECH CS137 Fall2005 - DeHon Partitioning Problem Given: netlist of interconnect c

  • 53 Pages day14_audio
    Day14_audio

    School: Caltech

    CS137: Electronic Design Automation Day 14: November 2, 2005 Partitioning 2 (spectral, network flow, replication) 1 CALTECH CS137 Fall2005 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but dont exactly solve ou

  • 39 Pages day15_audio
    Day15_audio

    School: Caltech

    CS137: Electronic Design Automation Day 15: February 13, 2006 Processor Verification CALTECH CS137 Winter2006 - DeHon 1 Today Specification/Implementation Abstraction Functions Correctness Condition Verification Self-Consistency CALTECH CS1

  • 1 Page day14_audio
    Day14_audio

    School: Caltech

  • 27 Pages day13_audio
    Day13_audio

    School: Caltech

    CS137: Electronic Design Automation Day 13: February 8, 2006 NC CALTECH CS137 Winter2006 - DeHon 1 Things we've seen Add two N-bit numbers in O(log(N) time on O(N) processors (gates) Sort N elements in O(log(N) time on O(N) processors Evaluate

  • 41 Pages day12
    Day12

    School: Caltech

    CS137: Electronic Design Automation Day 12: February 6, 2006 Sorting CALTECH CS137 Winter2006 - DeHon 1 Today Sequential Sorting Building on Parallel Prefix Systolic Sort Priority Queue Streaming Sort Mesh Sort (Shear Sort) Sorting Net

  • 9 Pages day8_6up
    Day8_6up

    School: Caltech

    CS137: Electronic Design Automation Today Problem Parallelism Cellular Automata Idea Details Avoid Local Minima Update locations Primary Sources Wrighton&DeHon FPGA2003 Wrighton MS Thesis 2003 Day 8: January 27, 2006 Cellular Placement

  • 2 Pages project
    Project

    School: Caltech

    CS137b California Institute of Technology Department of Computer Science Electronic Design Automation CS137b, Winter 2006 Winter 2006 Winter Project Wednesday, January 3 Project The center point for the Winter term will be a major, student chosen

  • 7 Pages day12_6up
    Day12_6up

    School: Caltech

    CS137: Electronic Design Automation Today Sequential Sorting Building on Parallel Prefix Systolic Day 12: February 6, 2006 Sorting Sort Priority Queue 1 Streaming Sort Mesh Sort (Shear Sort) Sorting Networks Parallel Merge Sort 2 CALTE

  • 7 Pages day15_6up
    Day15_6up

    School: Caltech

    CS137: Electronic Design Automation Today Specification/Implementation Abstraction Functions Correctness Condition Verification Self-Consistency Day 15: February 13, 2006 Processor Verification 1 CALTECH CS137 Winter2006 - DeHon CALTECH CS137

  • 5 Pages day13_6up
    Day13_6up

    School: Caltech

    CS137: Electronic Design Automation Things weve seen Add two N-bit numbers in O(log(N) time on O(N) processors (gates) Sort N elements in O(log(N) time on O(N) processors Evaluate an FSM on N inputs in O(log(N) time on O(N) processors Find the I

  • 9 Pages day2_6up
    Day2_6up

    School: Caltech

    CS137: Electronic Design Automation Today Idea Challenges Path Selection Victimization Allocation Day 2: January 6, 2006 Spatial Routing 1 Methodology Quality, Timing Parallelism Mesh FPGA Implementation 2 CALTECH CS137 Winter2006 - De

  • 5 Pages day14_6up
    Day14_6up

    School: Caltech

    CS137: Electronic Design Automation Today Sequential Verification DFA equivalence Issues Day 9: February 10, 2006 FSM Equivalence Checking Extracting STG Valid state reduction Incomplete Specification Solutions State PODEM State/path exp

  • 7 Pages day4_6up
    Day4_6up

    School: Caltech

    CS137: Electronic Design Automation Today Specifications/requirements/goals Concept Generation Day 4: Jan 18, 2006 Concept Generation CALTECH CS137 Winter2006 - DeHon CALTECH CS137 Winter2006 - DeHon Specification Before can start solving Ne

  • 61 Pages day9
    Day9

    School: Caltech

    CS137: Electronic Design Automation Day 9: January 30, 2006 Parallel Prefix 1 CALTECH CS137 Winter2006 - DeHon Today Bit-Level Addition LUT Cascades For Sums Applications FSMs SATADD Data Forwarding Pointer Jumping Applications 2 CAL

  • 48 Pages day8
    Day8

    School: Caltech

    CS137: Electronic Design Automation Day 8: January 27, 2006 Cellular Placement 1 CALTECH CS137 Winter2006 - DeHon Today Problem Parallelism Cellular Automata Idea Details Avoid Local Minima Update locations Primary Sources Wrighton&DeHon

  • 41 Pages day12_audio
    Day12_audio

    School: Caltech

    CS137: Electronic Design Automation Day 12: February 6, 2006 Sorting CALTECH CS137 Winter2006 - DeHon 1 Today Sequential Sorting Building on Parallel Prefix Systolic Sort Priority Queue Streaming Sort Mesh Sort (Shear Sort) Sorting Net

  • 46 Pages day10_audio
    Day10_audio

    School: Caltech

    CS137: Electronic Design Automation Day 10: February 1, 2006 Dynamic Programming CALTECH CS137 Winter2006 - DeHon 1 CS137b: Day2 Dynamic Programming Solution Solution described is general instance of dynamic programming Require: optimal solu

  • 61 Pages day9_audio
    Day9_audio

    School: Caltech

    CS137: Electronic Design Automation Day 9: January 30, 2006 Parallel Prefix 1 CALTECH CS137 Winter2006 - DeHon Today Bit-Level Addition LUT Cascades For Sums Applications FSMs SATADD Data Forwarding Pointer Jumping Applications 2 CAL

  • 49 Pages day8_audio
    Day8_audio

    School: Caltech

    CS137: Electronic Design Automation Day 8: January 27, 2006 Cellular Placement 1 CALTECH CS137 Winter2006 - DeHon Today Problem Parallelism Cellular Automata Idea Details Avoid Local Minima Update locations Primary Sources Wrighton&DeHon

  • 41 Pages day4_audio
    Day4_audio

    School: Caltech

    CS137: Electronic Design Automation Day 4: Jan 18, 2006 Concept Generation CALTECH CS137 Winter2006 - DeHon Today Specifications/requirements/goals Concept Generation CALTECH CS137 Winter2006 - DeHon Specification Before can start solving Ne

  • 1 Page day2_audio
    Day2_audio

    School: Caltech

    <?xml version="1.0" encoding="UTF-8"?> <Error><Code>NoSuchKey</Code><Message>The specified key does not exist.</Message><Key>e73117ab171233b099073e487f10c3af13c8fa24.ppt</Key><RequestId>7 3F157396720B73C</RequestId><HostId>eIm5VR2FphnxqoPC2tkF3Mucrt/

  • 42 Pages day4
    Day4

    School: Caltech

    CS137: Electronic Design Automation Day 4: Jan 18, 2006 Concept Generation CALTECH CS137 Winter2006 - DeHon Today Specifications/requirements/goals Concept Generation CALTECH CS137 Winter2006 - DeHon Specification Before can start solving Ne

  • 46 Pages day10
    Day10

    School: Caltech

    CS137: Electronic Design Automation Day 10: February 1, 2006 Dynamic Programming CALTECH CS137 Winter2006 - DeHon 1 CS137b: Day2 Dynamic Programming Solution Solution described is general instance of dynamic programming Require: optimal solu

  • 39 Pages day15
    Day15

    School: Caltech

    CS137: Electronic Design Automation Day 15: February 13, 2006 Processor Verification CALTECH CS137 Winter2006 - DeHon 1 Today Specification/Implementation Abstraction Functions Correctness Condition Verification Self-Consistency CALTECH CS1

  • 8 Pages day10_6up
    Day10_6up

    School: Caltech

    CS137: Electronic Design Automation CS137b: Day2 Dynamic Programming Solution Solution described is general instance of dynamic programming Require: Day 10: February 1, 2006 Dynamic Programming optimal solution to subproblems is optimal soluti

  • 37 Pages day2_2up
    Day2_2up

    School: Caltech

    CS137: Electronic Design Automation Day 2: January 7, 2004 Covering CALTECH CS137 Winter2004 - DeHon Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique show off special cas

  • 21 Pages day7_2up
    Day7_2up

    School: Caltech

    CS137: Electronic Design Automation Day 7: January 28, 2002 Partitioning 2 (spectral, network flow, replication) CALTECH CS137 Winter2002 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but dont exactly solve our

  • 49 Pages day7
    Day7

    School: Caltech

    CS137: Electronic Design Automation Day 7: October 12, 2005 Sequential Optimization (FSM Encoding) 1 CALTECH CS137 Fall 2005 - DeHon Today Encoding Input Output State Encoding "exact" two-level 2 CALTECH CS137 Fall 2005 - DeHon Input Encod

  • 9 Pages day19_6up
    Day19_6up

    School: Caltech

    CS137: Electronic Design Automation Scheduling Today Basic problem Variants List scheduling approximation Day 19: November 21, 2005 Scheduling Introduction 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 General Problem Re

  • 53 Pages day14
    Day14

    School: Caltech

    CS137: Electronic Design Automation Day 14: November 2, 2005 Partitioning 2 (spectral, network flow, replication) 1 CALTECH CS137 Fall2005 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but don't exactly solve o

  • 54 Pages day13
    Day13

    School: Caltech

    CS137: Electronic Design Automation Day 13: October 31, 2005 Partitioning (Intro, KLFM) 1 CALTECH CS137 Fall2005 - DeHon Today Partitioning why important practical attack variations and issues 2 CALTECH CS137 Fall2005 - DeHon Motivation (1)

  • 2 Pages ideas
    Ideas

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Big Ideas in EDA Wednesday, March 10 Human time (brainpower, productivity) is the limiting resource to developi

  • 23 Pages day16_2up
    Day16_2up

    School: Caltech

    CS137: Electronic Design Automation Day 16: March 10, 2004 Routing 2 (Pathfinder) CALTECH CS137 Winter2004 - DeHon Today Routing Pathfinder graph based global routing simultaneous global/detail CALTECH CS137 Winter2004 - DeHon Global Routin

  • 48 Pages day9
    Day9

    School: Caltech

    CS137: Electronic Design Automation Day 9: October 17, 2005 Fault Detection CALTECH CS137 Fall2005 - DeHon Today Faults in Logic Error Detection Schemes Optimization Problem CALTECH CS137 Fall2005 - DeHon Problem Gates, wires, memories: bui

  • 41 Pages day18
    Day18

    School: Caltech

    CS137: Electronic Design Automation Day 18: November 14, 2005 Dual Objective Dynamic Programming 1 CALTECH CS137 Fall2005 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for and linear placement Two Di

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