• 41 Pages day17_audio
    Day17_audio

    School: Caltech

    CS137: Electronic Design Automation Day 17: November 11, 2005 Placement (Simulated Annealing) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo

  • 40 Pages day16_audio
    Day16_audio

    School: Caltech

    CS137: Electronic Design Automation Day 16: November 9, 2005 Placement (Intro, Constructive) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Problem PartitioningPlacement Quadrisection Refinement 2 CALTECH CS137 Fall2005 - DeHon Placement

  • 53 Pages day14_audio
    Day14_audio

    School: Caltech

    CS137: Electronic Design Automation Day 14: November 2, 2005 Partitioning 2 (spectral, network flow, replication) 1 CALTECH CS137 Fall2005 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but dont exactly solve ou

  • 53 Pages day13_audio
    Day13_audio

    School: Caltech

    CS137: Electronic Design Automation Day 13: October 31, 2005 Partitioning (Intro, KLFM) 1 CALTECH CS137 Fall2005 - DeHon Today Partitioning why important practical attack variations and issues 2 CALTECH CS137 Fall2005 - DeHon Motivation (1)

  • 52 Pages day10_audio
    Day10_audio

    School: Caltech

    CS137: Electronic Design Automation Day 10: October 19, 2005 Modern SAT Solvers ({z}Chaff, GRASP,miniSAT) 1 CALTECH CS137 Fall2005 - DeHon Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts Learning 2 CALTECH CS13

  • 49 Pages day6_audio
    Day6_audio

    School: Caltech

    CS137: Electronic Design Automation Day 6: October 10, 2005 Static Timing Analysis and Multi-Level Speedup 1 CALTECH CS137 Fall2005 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus

  • 61 Pages day4_audio
    Day4_audio

    School: Caltech

    CS137: Electronic Design Automation Day 4: October 5, 2005 Two-Level Logic-Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements 2 CALTECH CS137 Fall200

  • 103 Pages day3_audio
    Day3_audio

    School: Caltech

    CS137: Electronic Design Automation Day 3: September 29, 2005 Clustering (LUT Mapping, Delay) 1 CALTECH CS137 Fall2005 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioni

  • 45 Pages day1_audio
    Day1_audio

    School: Caltech

    CS137: Electronic Design Automation Day 1: September 26, 2005 Introduction CALTECH CS137 Fall2005 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millionsbillions of devices used in everything billion dollar business

  • 27 Pages day13_audio
    Day13_audio

    School: Caltech

    CS137: Electronic Design Automation Day 13: February 8, 2006 NC CALTECH CS137 Winter2006 - DeHon 1 Things we've seen Add two N-bit numbers in O(log(N) time on O(N) processors (gates) Sort N elements in O(log(N) time on O(N) processors Evaluate

  • 61 Pages day9_audio
    Day9_audio

    School: Caltech

    CS137: Electronic Design Automation Day 9: January 30, 2006 Parallel Prefix 1 CALTECH CS137 Winter2006 - DeHon Today Bit-Level Addition LUT Cascades For Sums Applications FSMs SATADD Data Forwarding Pointer Jumping Applications 2 CAL

  • 41 Pages day4_audio
    Day4_audio

    School: Caltech

    CS137: Electronic Design Automation Day 4: Jan 18, 2006 Concept Generation CALTECH CS137 Winter2006 - DeHon Today Specifications/requirements/goals Concept Generation CALTECH CS137 Winter2006 - DeHon Specification Before can start solving Ne

  • 42 Pages day4
    Day4

    School: Caltech

    CS137: Electronic Design Automation Day 4: Jan 18, 2006 Concept Generation CALTECH CS137 Winter2006 - DeHon Today Specifications/requirements/goals Concept Generation CALTECH CS137 Winter2006 - DeHon Specification Before can start solving Ne

  • 46 Pages day10
    Day10

    School: Caltech

    CS137: Electronic Design Automation Day 10: February 1, 2006 Dynamic Programming CALTECH CS137 Winter2006 - DeHon 1 CS137b: Day2 Dynamic Programming Solution Solution described is general instance of dynamic programming Require: optimal solu

  • 61 Pages day9
    Day9

    School: Caltech

    CS137: Electronic Design Automation Day 9: January 30, 2006 Parallel Prefix 1 CALTECH CS137 Winter2006 - DeHon Today Bit-Level Addition LUT Cascades For Sums Applications FSMs SATADD Data Forwarding Pointer Jumping Applications 2 CAL

  • 41 Pages day12
    Day12

    School: Caltech

    CS137: Electronic Design Automation Day 12: February 6, 2006 Sorting CALTECH CS137 Winter2006 - DeHon 1 Today Sequential Sorting Building on Parallel Prefix Systolic Sort Priority Queue Streaming Sort Mesh Sort (Shear Sort) Sorting Net

  • 7 Pages day12_6up
    Day12_6up

    School: Caltech

    CS137: Electronic Design Automation Today Sequential Sorting Building on Parallel Prefix Systolic Day 12: February 6, 2006 Sorting Sort Priority Queue 1 Streaming Sort Mesh Sort (Shear Sort) Sorting Networks Parallel Merge Sort 2 CALTE

  • 9 Pages day2_6up
    Day2_6up

    School: Caltech

    CS137: Electronic Design Automation Today Idea Challenges Path Selection Victimization Allocation Day 2: January 6, 2006 Spatial Routing 1 Methodology Quality, Timing Parallelism Mesh FPGA Implementation 2 CALTECH CS137 Winter2006 - De

  • 11 Pages day9_6up
    Day9_6up

    School: Caltech

    CS137: Electronic Design Automation Bit-Level Addition LUT Cascades Today For Sums Day 9: January 30, 2006 Parallel Prefix Applications 1 FSMs SATADD Data Forwarding Pointer Jumping Applications 2 CALTECH CS137 Winter2006 - DeHon CA

  • 7 Pages day12_6up
    Day12_6up

    School: Caltech

    CS137: Electronic Design Automation Previously Cover (map) LUTs for minimum delay solve optimally Day 12: October 28, 2005 Covering and Retiming Retiming for minimum clock period solve optimally 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137

  • 36 Pages Day13
    Day13

    School: Caltech

    CS137: Electronic Design Automation Day 13: May 17, 2004 Modern SAT Solvers (Chaff) 1 CALTECH CS137 Spring2004 - DeHon Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts 2 CALTECH CS137 Spring2004 - DeHon Problem

  • 25 Pages day9_2up
    Day9_2up

    School: Caltech

    CS137: Electronic Design Automation Day 9: February 9, 2004 Partitioning (Intro, KLFM) CALTECH CS137 Winter2004 - DeHon Today Partitioning why important practical attack variations and issues CALTECH CS137 Winter2004 - DeHon 1 Motivation (1

  • 2 Pages assign5
    Assign5

    School: Caltech

    CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Assignment #5 Monday, March 8 Due: Wednesday, March 17, 4:59pm. Resources You are free to use any books, article

  • 8 Pages day9_6up
    Day9_6up

    School: Caltech

    CS137: Electronic Design Automation Today Faults in Logic Error Detection Schemes Optimization Problem Day 9: October 17, 2005 Fault Detection CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon Problem Gates, wires, memories: bui

  • 11 Pages day5_2up
    Day5_2up

    School: Caltech

    CS137: Electronic Design Automation Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Day 5: January 21, 2004 Multi-level Synthesis Boolean Division Higher quality division Spee

  • 8 Pages day8_6up
    Day8_6up

    School: Caltech

    outline Background Reliable State Machines Dr. Gary R Burke California Institute of Technology Jet Propulsion Laboratory 10/14/2005 Caltech 1 JPL MER example JPL FPGA/ASIC Process Procedure Guidelines State machines Traditional Highly Rel

  • 37 Pages day2_2up
    Day2_2up

    School: Caltech

    CS137: Electronic Design Automation Day 2: January 7, 2004 Covering CALTECH CS137 Winter2004 - DeHon Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique show off special cas

  • 7 Pages day18_6up
    Day18_6up

    School: Caltech

    CS137: Electronic Design Automation Linear Today Cover and Place GAMA Optimal Tree-based Day 18: November 14, 2005 Dual Objective Dynamic Programming Area and Time covering for .and linear placement Two Dimensional Lily 1 CALTECH CS137 F

  • 9 Pages day10_6up
    Day10_6up

    School: Caltech

    CS137: Electronic Design Automation Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts Day 10: October 19, 2005 Modern SAT Solvers ({z}Chaff, GRASP,miniSAT) Learning 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 F

  • 27 Pages day3_2up
    Day3_2up

    School: Caltech

    CS137: Electronic Design Automation Day 3: January 12, 2004 Clustering (LUT Mapping, Delay) CALTECH CS137 Winter2004 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioning

  • 53 Pages day11
    Day11

    School: Caltech

    CS137: Electronic Design Automation Day 11: February 11, 2002 Scheduling Introduction CALTECH CS137 Winter2002 - DeHon Today Scheduling Basic problem variants branching bounds and pruning CALTECH CS137 Winter2002 - DeHon General Problem R

  • 41 Pages Day2
    Day2

    School: Caltech

    CS137: Electronic Design Automation Day 2: March 31, 2004 Dual Objective Dynamic Programming CALTECH CS137 Spring2004 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for .and linear placement Two Dimen

  • 39 Pages day8
    Day8

    School: Caltech

    CS137: Electronic Design Automation Day 8: May 1, 2002 Static Timing Analysis CALTECH CS137 Spring2002 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus Delay-justified paths Timed-

  • 52 Pages day4
    Day4

    School: Caltech

    CS137: Electronic Design Automation Day 4: January 16, 2002 Clustering (LUT Mapping, Delay) CALTECH CS137 Winter2002 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioning

  • 35 Pages day8
    Day8

    School: Caltech

    CS137: Electronic Design Automation Day 8: January 30, 2002 Placement (Intro, Constructive) CALTECH CS137 Winter2002 - DeHon Placement Problem: Pick locations for all building blocks minimizing energy, delay, area really: minimize wire length

  • 32 Pages day10
    Day10

    School: Caltech

    CS137: Electronic Design Automation Day 10: February 6, 2002 Placement (Simulated Annealing.) CALTECH CS137 Winter2002 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo

  • 44 Pages day6
    Day6

    School: Caltech

    CS137: Electronic Design Automation Day 6: January 23, 2002 Partitioning (Intro, KLFM) CALTECH CS137 Winter2002 - DeHon Today Partitioning why important practical attack variations and issues CALTECH CS137 Winter2002 - DeHon Motivation (1)

  • 43 Pages day17
    Day17

    School: Caltech

    CS137: Electronic Design Automation Day 17: March 11, 2002 Sequential Optimization (FSM Encoding) CALTECH CS137 Winter2002 - DeHon Today Encoding Input Output State Encoding "exact" two-level CALTECH CS137 Winter2002 - DeHon Input Encoding

  • 28 Pages day5
    Day5

    School: Caltech

    CS137: Electronic Design Automation Day 5: April 15, 2002 Systolic Algorithms CALTECH CS137 Spring2002 - DeHon Today Systolic Style Systolic Algorithms and Structures Filters Matching Matrix Multiply and Transitive Closure Dynamic Programmin

  • 32 Pages day12
    Day12

    School: Caltech

    CS137: Electronic Design Automation Day 12: February 13, 2002 Scheduling Heuristics and Approximation CALTECH CS137 Winter2002 - DeHon Today Scheduling Force-Directed List-Scheduling Approximation Algorithms CALTECH CS137 Winter2002 - DeHon

  • 22 Pages day17_2up
    Day17_2up

    School: Caltech

    CS137: Electronic Design Automation Day 17: March 11, 2002 Sequential Optimization (FSM Encoding) CALTECH CS137 Winter2002 - DeHon Today Encoding Input Output State Encoding "exact" two-level CALTECH CS137 Winter2002 - DeHon 1 Input Encod

  • 18 Pages day8_2up
    Day8_2up

    School: Caltech

    CS137: Electronic Design Automation Day 8: January 30, 2002 Placement (Intro, Constructive) CALTECH CS137 Winter2002 - DeHon Placement Problem: Pick locations for all building blocks minimizing energy, delay, area really: minimize wire length

  • 29 Pages day13_2up
    Day13_2up

    School: Caltech

    CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1 CALTECH CS137 Winter2002 - DeHon Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer CALTECH CS137 Winter2002 - DeHon 1 Routing Problem W

  • 16 Pages day10_2up
    Day10_2up

    School: Caltech

    CS137: Electronic Design Automation Day 10: February 6, 2002 Placement (Simulated Annealing.) CALTECH CS137 Winter2002 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo

  • 40 Pages day16
    Day16

    School: Caltech

    CS137: Electronic Design Automation Day 16: November 9, 2005 Placement (Intro, Constructive) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Problem PartitioningPlacement Quadrisection Refinement 2 CALTECH CS137 Fall2005 - DeHon Placement

  • 23 Pages day16_2up
    Day16_2up

    School: Caltech

    CS137: Electronic Design Automation Day 16: March 10, 2004 Routing 2 (Pathfinder) CALTECH CS137 Winter2004 - DeHon Today Routing Pathfinder graph based global routing simultaneous global/detail CALTECH CS137 Winter2004 - DeHon Global Routin

  • 52 Pages day5
    Day5

    School: Caltech

    CS137: Electronic Design Automation Day 5: October 7, 2005 Multi-level Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Boolean Divisio

  • 38 Pages day11
    Day11

    School: Caltech

    CS137: Electronic Design Automation Day 11: February 18, 2004 Placement (Intro, Constructive) CALTECH CS137 Winter2004 - DeHon Today Placement Problem PartitioningPlacement Quadrisection Refinement CALTECH CS137 Winter2004 - DeHon Placement

  • 26 Pages day15
    Day15

    School: Caltech

    CS137: Electronic Design Automation Day 15: November 4, 2005 SAT for Partitioning 1 CALTECH CS137 Fall2005 - DeHon Today SAT Partitioning Devadas Wrighton 2 CALTECH CS137 Fall2005 - DeHon Partitioning Problem Given: netlist of interconnect c

  • 61 Pages day4
    Day4

    School: Caltech

    CS137: Electronic Design Automation Day 4: October 5, 2005 Two-Level Logic-Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements 2 CALTECH CS137 Fall200

  • 11 Pages day4_6up
    Day4_6up

    School: Caltech

    CS137: Electronic Design Automation Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements Day 4: October 5, 2005 Two-Level Logic-Synthesis 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 -

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