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Caltech | CS 137
100 sample documents related to CS 137
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Caltech CS 137
CS137: Electronic Design Automation Day 10: February 6, 2002 Placement (Simulated Annealing.) CALTECH CS137 Winter2002 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo -
Caltech CS 137
CS137: Electronic Design Automation Day 16: March 6, 2002 Multi-level Synthesis CALTECH CS137 Winter2002 - DeHon Today Multilevel Synthesis/Optimization Why Transforms Division/extraction Boolean Division Don\'t care CALTECH CS137 Winter2002 -
Caltech CS 137
CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1 CALTECH CS137 Winter2002 - DeHon Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer CALTECH CS137 Winter2002 - DeHon 1 Routing Problem W -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2002 Winter 2002 Assignment #3 Monday, February 11 Part A Due: Friday, February 22, 11:59pm. Part B Due: Friday, March 8, 11:59pm -
Caltech CS 137
CS137: Electronic Design Automation Day 1: January 7, 2002 Introduction CALTECH CS137 Winter2002 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millions->billions of devices used in everything billion dollar busines -
Caltech CS 137
CS137: Electronic Design Automation Day 12: February 13, 2002 Scheduling Heuristics and Approximation CALTECH CS137 Winter2002 - DeHon Today Scheduling Force-Directed List-Scheduling Approximation Algorithms CALTECH CS137 Winter2002 - DeHon -
Caltech CS 137
CS137: Electronic Design Automation Day 14: February 27, 2002 Routing 2 (Pathfinder) CALTECH CS137 Winter2002 - DeHon Today Routing Pathfinder graph based global routing simultaneous global/detail CALTECH CS137 Winter2002 - DeHon 1 Global -
Caltech CS 137
CS137: Electronic Design Automation Day 4: January 16, 2002 Clustering (LUT Mapping, Delay) CALTECH CS137 Winter2002 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioning -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2002 Winter 2002 Assignment #4 Monday, March 11 Due: Wednesday, March 20, 5:00pm. Resources You are free to use any books, articl -
Caltech CS 137
CS137: Electronic Design Automation Day 7: January 28, 2002 Partitioning 2 (spectral, network flow, replication) CALTECH CS137 Winter2002 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but dont exactly solve our -
Caltech CS 137
CS137: Electronic Design Automation Day 6: January 23, 2002 Partitioning (Intro, KLFM) CALTECH CS137 Winter2002 - DeHon Today Partitioning why important practical attack variations and issues CALTECH CS137 Winter2002 - DeHon 1 Motivation (1 -
Caltech CS 137
CS137: Electronic Design Automation Day 11: February 11, 2002 Scheduling Introduction CALTECH CS137 Winter2002 - DeHon Today Scheduling Basic problem variants branching bounds and pruning CALTECH CS137 Winter2002 - DeHon 1 General Problem -
Caltech CS 137
CS137b California Institute of Technology Department of Computer Science Electronic Design Automation CS137b, Spring 2002 Spring 2002 Spring Project Monday, April 1 Project The center point for the Spring term will be a major, student chosen desi -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2002 Winter 2002 Assignment #2 Monday, January 28 Due: Friday, February 8, 11:59pm. Resources You are free to use any books, arti -
Caltech CS 137
CS137: Electronic Design Automation Day 15: March 4, 2002 Two-Level Logic-Synthesis CALTECH CS137 Winter2002 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements CALTECH CS137 Winter2002 -
Caltech CS 137
CS137: Electronic Design Automation Day 2: January 9, 2002 Covering CALTECH CS137 Winter2002 - DeHon Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique show off special cas -
Caltech CS 137
CS137: Electronic Design Automation Day 8: January 30, 2002 Placement (Intro, Constructive) CALTECH CS137 Winter2002 - DeHon Placement Problem: Pick locations for all building blocks minimizing energy, delay, area really: minimize wire length -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2002 Winter 2002 Assignment #1 Wednesday, January 9 Due: Friday, January 25, 11:59pm. Resources You are free to use any books, ar -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2002 Winter 2002 Big Ideas in EDA Wednesday, March 13 Human time (brainpower, productivity) is the limiting resource to developi -
Caltech CS 137
CS137: Electronic Design Automation Day 18: March 13, 2002 Retiming CALTECH CS137 Winter2002 - DeHon Today Retiming cycle time (clock period) C-slow initial states register minimization Necessary delays (time permitting) CALTECH CS137 Winte -
Caltech CS 137
CS137: Electronic Design Automation Day 17: March 11, 2002 Sequential Optimization (FSM Encoding) CALTECH CS137 Winter2002 - DeHon Today Encoding Input Output State Encoding \"exact\" two-level CALTECH CS137 Winter2002 - DeHon 1 Input Encod -
Caltech CS 137
CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1 CALTECH CS137 Winter2002 - DeHon Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer CALTECH CS137 Winter2002 - DeHon Routing Problem Wher -
Caltech CS 137
CS137: Electronic Design Automation Day 12: February 13, 2002 Scheduling Heuristics and Approximation CALTECH CS137 Winter2002 - DeHon Today Scheduling Force-Directed List-Scheduling Approximation Algorithms CALTECH CS137 Winter2002 - DeHon -
Caltech CS 137
CS137: Electronic Design Automation Day 10: May 8, 2002 Processor Verification CALTECH CS137 Spring2002 - DeHon Today Specification/Implementation Abstraction Functions Correctness Condition Verification Self-Consistency CALTECH CS137 Spring -
Caltech CS 137
CS137: Electronic Design Automation Day 5: April 15, 2002 Systolic Algorithms CALTECH CS137 Spring2002 - DeHon Today Systolic Style Systolic Algorithms and Structures Filters Matching Matrix Multiply and Transitive Closure Dynamic Programmin -
Caltech CS 137
CS137: Electronic Design Automation Day 7: January 28, 2002 Partitioning 2 (spectral, network flow, replication) CALTECH CS137 Winter2002 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but dont exactly solve our -
Caltech CS 137
CS137: Electronic Design Automation Day 17: March 11, 2002 Sequential Optimization (FSM Encoding) CALTECH CS137 Winter2002 - DeHon Today Encoding Input Output State Encoding \"exact\" two-level CALTECH CS137 Winter2002 - DeHon Input Encoding -
Caltech CS 137
CS137: Electronic Design Automation Day 6: January 23, 2002 Partitioning (Intro, KLFM) CALTECH CS137 Winter2002 - DeHon Today Partitioning why important practical attack variations and issues CALTECH CS137 Winter2002 - DeHon Motivation (1) -
Caltech CS 137
CS137: Electronic Design Automation Day 15: March 4, 2002 Two-Level Logic-Synthesis CALTECH CS137 Winter2002 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements CALTECH CS137 Winter2002 -
Caltech CS 137
CS137: Electronic Design Automation Day 10: February 6, 2002 Placement (Simulated Annealing.) CALTECH CS137 Winter2002 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo -
Caltech CS 137
CS137: Electronic Design Automation Day 6: April 17, 2002 Parallel Prefix CALTECH CS137 Spring2002 - DeHon Today Parallel Prefix Sample Applications CALTECH CS137 Spring2002 - DeHon Key Result Can compute cascaded result sequence on any assoc -
Caltech CS 137
CS137: Electronic Design Automation Day 9: May 6, 2002 FSM Equivalence Checking CALTECH CS137 Spring2002 - DeHon Today Sequential Verification DFA equivalence Issues Extracting STG Valid state reduction Incomplete Specification Solutions -
Caltech CS 137
CS137: Electronic Design Automation Day 8: January 30, 2002 Placement (Intro, Constructive) CALTECH CS137 Winter2002 - DeHon Placement Problem: Pick locations for all building blocks minimizing energy, delay, area really: minimize wire length -
Caltech CS 137
CS137: Electronic Design Automation Day 2: January 9, 2002 Covering CALTECH CS137 Winter2002 - DeHon Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique show off special cas -
Caltech CS 137
CS137: Electronic Design Automation Day 4: January 16, 2002 Clustering (LUT Mapping, Delay) CALTECH CS137 Winter2002 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioning -
Caltech CS 137
CS137: Electronic Design Automation Day 1: January 7, 2002 Introduction CALTECH CS137 Winter2002 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millions->billions of devices used in everything billion dollar busines -
Caltech CS 137
CS137: Electronic Design Automation Day 8: May 1, 2002 Static Timing Analysis CALTECH CS137 Spring2002 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus Delay-justified paths Timed- -
Caltech CS 137
CS137: Electronic Design Automation Day 14: February 27, 2002 Routing 2 (Pathfinder) CALTECH CS137 Winter2002 - DeHon Today Routing Pathfinder graph based global routing simultaneous global/detail CALTECH CS137 Winter2002 - DeHon Global Rou -
Caltech CS 137
CS137: Electronic Design Automation Day 18: March 13, 2002 Retiming CALTECH CS137 Winter2002 - DeHon Today Retiming cycle time (clock period) C-slow initial states register minimization Necessary delays (time permitting) CALTECH CS137 Winte -
Caltech CS 137
CS137: Electronic Design Automation Day 11: February 11, 2002 Scheduling Introduction CALTECH CS137 Winter2002 - DeHon Today Scheduling Basic problem variants branching bounds and pruning CALTECH CS137 Winter2002 - DeHon General Problem R -
Caltech CS 137
CS137: Electronic Design Automation Day 2: April 03, 2002 Force Directed CALTECH CS137 Spring2002 - DeHon Components/Issues Optimization Target (Cost Model) Forces Avoid Collapse Spreading, repulsion Initial Position Sensitivity Moves Te -
Caltech CS 137
CS137: Electronic Design Automation Today Placement Improving Quality Day 17: November 11, 2005 Placement (Simulated Annealing.) Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bound) 1 CALTECH CS137 Fall2005 - -
Caltech CS 137
CS137: Electronic Design Automation Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts Day 10: October 19, 2005 Modern SAT Solvers ({z}Chaff, GRASP,miniSAT) Learning 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 F -
Caltech CS 137
CS137: Electronic Design Automation Linear Today Cover and Place GAMA Optimal Tree-based Day 18: November 14, 2005 Dual Objective Dynamic Programming Area and Time covering for .and linear placement Two Dimensional Lily 1 CALTECH CS137 F -
Caltech CS 137
CS137: Electronic Design Automation Encoding Input Output Today Day 7: October 12, 2005 Sequential Optimization (FSM Encoding) State Encoding \"exact\" two-level 1 CALTECH CS137 Fall 2005 - DeHon CALTECH CS137 Fall 2005 - DeHon 2 Input Encod -
Caltech CS 137
CS137: Electronic Design Automation Day 1: September 26, 2005 Introduction CALTECH CS137 Fall2005 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millions billions of devices used in everything billion dollar busines -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #3 Monday, October 24 Assignment #3A Due: Friday, October 28, 11:59pm. Assignment #3B Due: Friday, Nov -
Caltech CS 137
outline Background Reliable State Machines Dr. Gary R Burke California Institute of Technology Jet Propulsion Laboratory 10/14/2005 Caltech 1 JPL MER example JPL FPGA/ASIC Process Procedure Guidelines State machines Traditional Highly Rel -
Caltech CS 137
CS137: Electronic Design Automation Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Day 5: October 7, 2005 Multi-level Synthesis Boolean Division Higher quality division Speed -
Caltech CS 137
CS137: Electronic Design Automation Today Topological Worst Case not adequate (too conservative) Day 6: October 10, 2005 Static Timing Analysis and Multi-Level Speedup Sensitization Conditions Timed Calculus Delay-justified paths Timed-PODEM -
Caltech CS 137
CS137: Electronic Design Automation Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer Day 21: November 28, 2005 Routing 1 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Routing Problem Wher -
Caltech CS 137
CS137: Electronic Design Automation Partitioning Today why important practical attack variations and issues Day 13: October 31, 2005 Partitioning (Intro, KLFM) 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Motivation (1) -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #2 Monday, October 10 Due: Friday, October 21, 11:59pm. Resources You are free to use any books, articles -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #1 Wednesday, September 28 Due: Friday, October 7, 11:59pm. Resources You are free to use any books, arti -
Caltech CS 137
CS137: Electronic Design Automation Today Faults in Logic Error Detection Schemes Optimization Problem Day 9: October 17, 2005 Fault Detection CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon Problem Gates, wires, memories: bui -
Caltech CS 137
CS137: Electronic Design Automation Today Placement Problem Partitioning Placement Quadrisection Refinement Day 16: November 9, 2005 Placement (Intro, Constructive) 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Placement -
Caltech CS 137
CS137: Electronic Design Automation Today Alternate views of partitioning Two things we can solve optimally Day 14: November 2, 2005 Partitioning 2 (spectral, network flow, replication) 1 CALTECH CS137 Fall2005 - DeHon (but dont exactly solve o -
Caltech CS 137
CS137: Electronic Design Automation Why covering now? Nice/simple cost model problem can be solved well somewhat clever solution Day 2: September 28, 2005 Covering general/powerful technique show off special cases harder/easier cases show -
Caltech CS 137
CS137: Electronic Design Automation Simplifying Structure K-LUT can implement any K-input function Day 3: September 29, 2005 Clustering (LUT Mapping, Delay) 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 4 Today How do we map -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Fall 2005 Fall 2005 Assignment #5 Monday, November 21 Due: Wednesday, December 7, 11:59pm PST. Resources You are free to use any books, -
Caltech CS 137
CS137: Electronic Design Automation Routing Pathfinder Today Day 22: December 2, 2005 Routing 2 (Pathfinder) graph based global routing simultaneous global/detail 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Global Rou -
Caltech CS 137
CS137: Electronic Design Automation Devadas Wrighton Today SAT Partitioning Day 15: November 4, 2005 SAT for Partitioning 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - DeHon 2 Partitioning Problem Given: netlist of interconnect c -
Caltech CS 137
CS137: Electronic Design Automation Retiming Today Cycle time (clock period) C-slow Initial states Register minimization Necessary delays (time permitting) Day 11: October 21, 2005 Retiming 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall -
Caltech CS 137
CS137: Electronic Design Automation Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements Day 4: October 5, 2005 Two-Level Logic-Synthesis 1 CALTECH CS137 Fall2005 - DeHon CALTECH CS137 Fall2005 - -
Caltech CS 137
CS137: Electronic Design Automation Day 4: October 5, 2005 Two-Level Logic-Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements 2 CALTECH CS137 Fall200 -
Caltech CS 137
CS137: Electronic Design Automation Day 10: October 19, 2005 Modern SAT Solvers ({z}Chaff, GRASP,miniSAT) 1 CALTECH CS137 Fall2005 - DeHon Today SAT Davis-Putnam Data Structures Optimizations Watch2 VSIDS ?restarts Learning 2 CALTECH CS13 -
Caltech CS 137
Reliable State Machines Dr. Gary R Burke California Institute of Technology Jet Propulsion Laboratory 10/14/2005 Caltech 1 outline Background JPL MER example JPL FPGA/ASIC Process Procedure Guidelines State machines Traditional Highly Reli -
Caltech CS 137
CS137: Electronic Design Automation Day 17: November 11, 2005 Placement (Simulated Annealing) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Improving Quality Avoiding local minima Techniques: Simulated Annealing Exhaustive (Branch-and-bo -
Caltech CS 137
CS137: Electronic Design Automation Day 1: September 26, 2005 Introduction CALTECH CS137 Fall2005 - DeHon Apple Pie Intro (1) How do we design modern computational systems? Millionsbillions of devices used in everything billion dollar business -
Caltech CS 137
CS137: Electronic Design Automation Day 2: September 28, 2005 Covering 1 CALTECH CS137 Fall2005 - DeHon Why covering now? Nice/simple cost model problem can be solved well somewhat clever solution general/powerful technique show off special -
Caltech CS 137
CS137: Electronic Design Automation Day 22: December 2, 2005 Routing 2 (Pathfinder) 1 CALTECH CS137 Fall2005 - DeHon Today Routing Pathfinder graph based global routing simultaneous global/detail 2 CALTECH CS137 Fall2005 - DeHon Global Rout -
Caltech CS 137
CS137: Electronic Design Automation Day 15: November 4, 2005 SAT for Partitioning 1 CALTECH CS137 Fall2005 - DeHon Today SAT Partitioning Devadas Wrighton 2 CALTECH CS137 Fall2005 - DeHon Partitioning Problem Given: netlist of interconnect c -
Caltech CS 137
CS137: Electronic Design Automation Day 21: November 28, 2005 Routing 1 1 CALTECH CS137 Fall2005 - DeHon Today Custom/Semi-custom Routing Slicing Channel Routing Over-the-Cell/Multilayer 2 CALTECH CS137 Fall2005 - DeHon Routing Problem Wher -
Caltech CS 137
CS137: Electronic Design Automation Day 20: November 23, 2005 Scheduling Variants and Approaches 1 CALTECH CS137 Fall2005 - DeHon Today Scheduling Force-Directed SAT/ILP Branch-and-Bound 2 CALTECH CS137 Fall2005 - DeHon Last Time Resourc -
Caltech CS 137
CS137: Electronic Design Automation Day 3: September 29, 2005 Clustering (LUT Mapping, Delay) 1 CALTECH CS137 Fall2005 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons for non-LUTs for delay-oriented partitionin -
Caltech CS 137
CS137: Electronic Design Automation Day 5: October 7, 2005 Multi-level Synthesis 1 CALTECH CS137 Fall2005 - DeHon Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Boolean Divisio -
Caltech CS 137
CS137: Electronic Design Automation Day 19: November 21, 2005 Scheduling Introduction 1 CALTECH CS137 Fall2005 - DeHon Today Scheduling Basic problem Variants List scheduling approximation 2 CALTECH CS137 Fall2005 - DeHon General Problem Re -
Caltech CS 137
CS137: Electronic Design Automation Day 11: October 21, 2005 Retiming 1 CALTECH CS137 Fall2005 - DeHon Today Retiming Cycle time (clock period) C-slow Initial states Register minimization Necessary delays (time permitting) 2 CALTECH CS137 F -
Caltech CS 137
CS137: Electronic Design Automation Day 18: November 14, 2005 Dual Objective Dynamic Programming 1 CALTECH CS137 Fall2005 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for and linear placement Two Di -
Caltech CS 137
CS137: Electronic Design Automation Day 9: October 17, 2005 Fault Detection CALTECH CS137 Fall2005 - DeHon Today Faults in Logic Error Detection Schemes Optimization Problem CALTECH CS137 Fall2005 - DeHon Problem Gates, wires, memories: bui -
Caltech CS 137
CS137: Electronic Design Automation Day 13: October 31, 2005 Partitioning (Intro, KLFM) 1 CALTECH CS137 Fall2005 - DeHon Today Partitioning why important practical attack variations and issues 2 CALTECH CS137 Fall2005 - DeHon Motivation (1) -
Caltech CS 137
CS137: Electronic Design Automation Day 14: November 2, 2005 Partitioning 2 (spectral, network flow, replication) 1 CALTECH CS137 Fall2005 - DeHon Today Alternate views of partitioning Two things we can solve optimally (but don\'t exactly solve o -
Caltech CS 137
CS137: Electronic Design Automation Day 7: October 12, 2005 Sequential Optimization (FSM Encoding) 1 CALTECH CS137 Fall 2005 - DeHon Today Encoding Input Output State Encoding \"exact\" two-level 2 CALTECH CS137 Fall 2005 - DeHon Input Encod -
Caltech CS 137
CS137: Electronic Design Automation Day 16: November 9, 2005 Placement (Intro, Constructive) 1 CALTECH CS137 Fall2005 - DeHon Today Placement Problem PartitioningPlacement Quadrisection Refinement 2 CALTECH CS137 Fall2005 - DeHon Placement -
Caltech CS 137
CS137: Electronic Design Automation Day 12: October 28, 2005 Covering and Retiming 1 CALTECH CS137 Fall2005 - DeHon Previously Cover (map) LUTs for minimum delay solve optimally Retiming for minimum clock period solve optimally 2 CALTECH CS1 -
Caltech CS 137
CS137: Electronic Design Automation Day 6: October 10, 2005 Static Timing Analysis and Multi-Level Speedup 1 CALTECH CS137 Fall2005 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus -
Caltech CS 137
CS137: Electronic Design Automation Day 2: March 31, 2004 Dual Objective Dynamic Programming CALTECH CS137 Spring2004 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for .and linear placement Two Dimen -
Caltech CS 137
CS137: Electronic Design Automation Day 3: January 12, 2004 Clustering (LUT Mapping, Delay) CALTECH CS137 Winter2004 - DeHon Today How do we map to LUTs? What happens when delay dominates? Lessons. for non-LUTs for delay-oriented partitioning -
Caltech CS 137
CS137: Electronic Design Automation Day 2: March 31, 2004 Dual Objective Dynamic Programming CALTECH CS137 Spring2004 - DeHon Today Cover and Place Linear GAMA Optimal Tree-based Area and Time covering for .and linear placement Two Dimen -
Caltech CS 137
CS137: Electronic Design Automation Day 6: January 26, 2004 Sequential Optimization (FSM Encoding) CALTECH CS137 Winter2004 - DeHon Today Encoding Input Output State Encoding \"exact\" two-level CALTECH CS137 Winter2004 - DeHon Input Encodin -
Caltech CS 137
CS137: Electronic Design Automation Day 6: April 19, 2002 Static Timing Analysis CALTECH CS137 Spring2004 - DeHon Today Topological Worst Case not adequate (too conservative) Sensitization Conditions Timed Calculus Delay-justified paths Tim -
Caltech CS 137
CS137: Electronic Design Automation Day 9: May 2, 2004 FSM Equivalence Checking CALTECH CS137 Spring2004 - DeHon Today Sequential Verification DFA equivalence Issues Extracting STG Valid state reduction Incomplete Specification Solutions -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Assignment #3 Monday, February 9 Assignment #3 Due: Friday, February 20, 11:59pm. Assignment #4 Due: Friday, -
Caltech CS 137
CS137: Electronic Design Automation Day 5: April 12, 2004 Covering and Retiming 1 CALTECH CS137 Spring2004 - DeHon Previously Cover (map) LUTs for minimum delay solve optimally Retiming for minimum clock period solve optimally Simultaneous -
Caltech CS 137
CS137: Electronic Design Automation Day 2: January 7, 2004 Covering CALTECH CS137 Winter2004 - DeHon Why covering now? Nice/simple cost model problem can be solved well (somewhat clever solution) general/powerful technique show off special cas -
Caltech CS 137
CS137: Electronic Design Automation Today Multilevel Synthesis/Optimization Why Transforms - defined Division/extraction How we support transforms Day 5: January 21, 2004 Multi-level Synthesis Boolean Division Higher quality division Spee -
Caltech CS 137
CS137a California Institute of Technology Department of Computer Science Electronic Design Automation CS137a, Winter 2004 Winter 2004 Assignment #2 Wednesday, January 21 Due: Friday, February 6, 11:59pm. Resources You are free to use any books, a -
Caltech CS 137
CS137: Electronic Design Automation Day 3: April 5, 2004 Concept Generation CALTECH CS137 Spring2004 - DeHon Today Specifications/requirements/goals Concept Generation CALTECH CS137 Spring2004 - DeHon Specification Before can start solving N -
Caltech CS 137
CS137: Electronic Design Automation Day 4: January 14, 2004 Two-Level Logic-Synthesis CALTECH CS137 Winter2004 - DeHon Today Two-Level Logic Optimization Problem Definitions Basic Algorithm: Quine-McClusky Improvements CALTECH CS137 Winter20 -
Caltech CS 137
CS137b California Institute of Technology Department of Computer Science Electronic Design Automation CS137b, Spring 2004 Spring 2004 Spring Project Monday, March 29 Project The center point for the Spring term will be a major, student chosen des
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