lecture23 - CIS 450 Computer Architecture and Organization...

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CIS 450 – Computer Architecture and Organization Lecture 23: Memory Systems Mitch Neilsen (neilsen@ksu.edu ) 219D Nichols Hall
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Topics ± Simple Virtual Memory System Example ± Intel P6 address translation ± x86-64 extensions ± Linux memory management ± Linux page fault handling ± Memory mapping
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Simple Memory System Example Addressing ± 14-bit virtual addresses ± 12-bit physical address ± Page size = 64 bytes 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 VPO PPO PPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset)
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Simple Memory System Page Table ± Only show first 16 entries (out of 256) VPN PPN Valid VPN PPN Valid 00 28 1 08 13 1 01 0 09 17 1 02 33 1 0A 09 1 03 02 1 0B 0 04 0 0C 0 05 16 1 0D 2D 1 06 0 0E 11 1 07 0 0F 0D 1
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Simple Memory System TLB TLB ± 16 entries ± 4-way associative 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPO VPN TLBI TLBT Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 0 03 0 09 0D 1 00 0 07 02 1 1 03 2D 1 02 0 04 0 0A 0 20 2– 00 8– 6– 3– 0 30 7– 3 0 D10 A 3 410 0
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Simple Memory System Cache Cache ± 16 lines ± 4-byte line size ± Direct mapped 11 10 9 8 7 6 5 4 3 2 1 0 PPO PPN CO CI CT Idx Tag Valid B0 B1 B2 B3 Idx Tag Valid B0 B1 B2 B3 0 1 9 1 9 91 12 31 1 8 2 4 1 3 A0 05 18 9 1 1 5 0––––9 2 D 0–––– 2 1B 1 00 02 04 08 A 2D 1 93 15 DA 3B 3 3 6 0––––B 0 B 43 214 3 6 D 8 F 0 9C1 20 5 0D 1 36 72 F0 1D D 16 1 04 96 34 15 63 10 E1 318 3 7 7 1 B D 3 71 611 1 C 2 D F 0 3F1 40
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Address Translation Example #1 Virtual Address 0x03D4 VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Physical Address Offset ___ CI___ CT ____ Hit? __ Byte: ____ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPO VPN TLBI TLBT 11 10 9 8 7 6 5 4 3 2 1 0 PPO PPN CO CI CT 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0x0F 3 0x03 Y NO 0x0D 0 0 0 1 0 1 01 1 0 1 0 0 0x5 0x0D Y 0x36
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Address Translation Example #2 Virtual Address 0x0B8F VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Physical Address Offset ___ CI___ CT ____ Hit? __ Byte: ____ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPO VPN TLBI TLBT 11 10 9 8 7 6 5 4 3 2 1 0 PPO PPN CO CI CT 1 1 1 1 0 0 0 1 1 1 0 1 0 0 0x2E 2 0x0B NO YES TBD
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Address Translation Example #3 Virtual Address 0x0020 VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Physical Address Offset ___ CI___ CT ____ Hit? __ Byte: ____ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPO VPN TLBI TLBT 11 10 9 8 7 6 5 4 3 2 1 0 PPO PPN CO CI CT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0x00 0 0x00 NO NO 0x28 0 0 0 0 0 0 00 0 1 1 1 0 0x8 0x28 NO MEM
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Multi-Level Page Tables Given: ± 4KB (2 12 ) page size ± 48-bit address space ± 4-byte PTE Problem: ± Would need a 256 GB page table! z 2 48 * 2 -12 * 2 2 = 2 38 bytes Common solution ± Multi-level page tables ± Example: 2-level page table z Level 1 table: each PTE points to a page table (memory resident) z Level 2 table: Each PTE points to a page (paged in and out like other data) Level 1 Table ... Level 2 Tables ...
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A Two-Level Page Table Hierarchy Level 1 page table ... Level 2 page tables VP 0 ...
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lecture23 - CIS 450 Computer Architecture and Organization...

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