Lab4 - Lab Assignment 4 Carry Look-ahead Adder/Subtractor...

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Lab Assignment 4 Carry Look-ahead Adder/Subtractor and Hazard Free Design Due February 28, Thursday, 1:00pm Introduction: This lab assignment consists of two parts: (1) Implementation of a carry look-ahead excess-3 adder/subtractor , and (2) Hazard analysis and implementation of hazard-free circuits. Part 1: Carry look-ahead excess-3 adder/subtractor In Part 2 of your Lab 3 assignment, you have implemented an excess-3 adder using a 4-bit binary adder and a constant-3 adder/subtractor that you have designed. In this part of the lab, you will be designing a carry look-ahead adder/subtractor for excess-3 numbers of 4 decimal digits. The interesting part of a binary carry look-ahead adder is that it can in some sense precompute the carries of each bit, thus drastically speeding up the overall adder through enabling a number of operations to happen concurrently. One of the questions that this lab assignment tries to get you to address is whether the same idea of precomputation of carries is applicable to decimal adders, say ones that are encoded in excess-3 representation. The write-up explains how to approach this problem so that you can design a circuit that can speedily add (or subtract) two 4- digit decimal numbers. The challenges for you will be concentrated in two parts; primarily, you need to think about how the excess-3 representation (instead of binary) impacts the applicability of the carry look ahead techniques we outline here and are described in detail in the textbook. Secondly, you need to think about how to incorporate subtraction capabilities in your circuit in addition to addition . You will find that the second part of your previous lab assignment should be of help with some of these issues. Carry look-ahead binary adder You have learned from your textbook that a single bit full adder (FA) takes as inputs two operands x i , y i and the carry c i , and produces as outputs the sum s i and carry c i+1 . An n -bit binary adder can be implemented as a serial connection of FAs, arranged such that the output carry of each FA serves as the input carry for the next-higher significant FA. This type of adder is denoted as ripple-carry adder , since any change in the least significant bits c 0 , x 0 , or y 0 has to ripple through all the FAs. One important feature of an adder is its delay, that is, the time it takes for it to output the sum and carry. For a ripple-carry adder, each FA needs to wait for the next-lower significant FA for generating the carry, thus imposing a significant limitation on the speed of this type of adder. The purpose of designing a carry look-ahead adder is to reduce the delay of the carry chain in a ripple-carry adder. This technique takes advantage of the fact that the major part of the expressions of each carry in the chain can be precomputed. Let’s take as an example a 4-bit adder that computes x 3 x 2 x 1 x 0 + y 3 y 2 y 1 y 0 + c 0 . We first define two functions as follows: (1) the carry-generate function g i = x i y i , and (2) the
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This note was uploaded on 04/09/2008 for the course CSE 140L taught by Professor Orailoglu during the Spring '08 term at UCSD.

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Lab4 - Lab Assignment 4 Carry Look-ahead Adder/Subtractor...

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