W08 314 HW10 Solutions

W08 314 HW10 Solutions - EECS 314 Winter 2008 HW 10...

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Part 1 Determine the intermediate logic signals to solve the problem incrementally, and verify the net operation: Input A Output A Input B Output B Output C 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 1 The behavior matches the OR function. Part 2 Input A Output A Input B Output B Output middle NAND Output C 0 1 0 10 1 1 0 0 11 0 0 1 1 01 0 1 0 1 0 The behavior matches the NOR function. EECS 314 Winter 2008 HW 10 Solutions Problem 1
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Part 3 Input A Output A Input B Output B Output C 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 The behavior matches the AND function. EECS 314 Winter 2008 HW 10 Solutions Problem 1
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Homework 10 Problem 2 Solution Part 1: R S Q Q Comments 0 1 1 0 1 0 0 1 0 0 0 1 Initially, Q=0 0 0 1 0 Initially, Q=1 This is a set-reset latch. When S=1 and R=0, the output Q is “set” to 1. When S=0 and R=1, the output Q is “reset” to 0. When both S=0 and R=0, the output doesn’t change. S=1, R=0 When either of the two inputs a NOR gate is 1, the output is always 0. Therefore, Q is always 0 because the input S is 1. Q is also the input to the upper NOR gate. Therefore, the inputs to that gate are 00 and the output Q is 1. S=0, R=1 When either of the two inputs a NOR gate is 1, the output is always 0. Therefore, Q is always 0 because R is 1. Q is also the input to the lower NOR gate. Therefore, the inputs to that gate are 00 and the output Q is 1. S=0, R=0, Q=0 initially Q is the input to the lower NOR gate. Therefore, the input to that gate is 00, and the output Q is 1. Q is the input to the upper NOR gate, making the two inputs 01. Therefore, the output Q remains 0, as expected. R S Q Q
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S=0, R=0, Q=1 initially Q is the input to the lower NOR gate. Therefore, the input to that gate is 01, and the output Q is 0. Q is the input to the upper NOR gate, making the two inputs 00. Therefore, the output Q remains 1, as expected. Part 2: Time Interval 1 The value of R=1 and S=0. This “resets” the latch, making Q=0 and Q =1. Time Interval 2 The value of S=1 and R=0. This “sets” the latch, making Q=1 and Q =0. Time Interval 6 The value of R=1 and S=0. This “resets” the latch, making Q=0 and Q =1. Time Interval 7 The value of R=0 and S=0. The outputs stay stable, so Q=0 and Q =1. The SR latch eliminates switch bounce.
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EECS 314 Homework 10 Problem 3 Solution Part 1 During time interval a, V IN is 0V (LOW). Diode will be forward biased and will act like a short circuit with an offset voltage of 0.7 V. Therefore, the output voltage will be equal to voltage of forward biased diode which is 0.7V which we assume to be within error margin for logic LOW. So output is 0.7V (LOW). During time interval b, V IN is 5V (HIGH). Diode will be reverse biased and will act like an open circuit. No current flows in the circuit which means no voltage drop across resistor. Therefore, the output voltage will be equal to 5V (HIGH).
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W08 314 HW10 Solutions - EECS 314 Winter 2008 HW 10...

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