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Exam 2 Practice

# Exam 2 Practice - Exam#2 Practice PROBLEM 2(1 point What is...

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Exam #2 – Practice PROBLEM 2 (1 point) What is used to select one of many inputs? A. Decoder B. MUX or multiplexer C. Full adder D. Inverter E. R-S latch PROBLEM 3 (1 point) Circle ALL of the following elements which are sequential logic circuits: Decoder Full Adder Master-Slave Flip-Flop D-Latch Register Inverter (NOT gate) R-S Latch Multiplexer (MUX) None of these PROBLEM 8 (4 points) The following figure shows the waveforms of input Data “D” and Write Enable “WE” of a gated D latch. Draw the output signal of the latch (assuming it’s initial value is 0). If the output during a period cannot be determined, write “error” in that section. PROBLEM 10 (1 point) The PC is incremented so that during the next instruction cycle, the next instruction will be processed. This happens during the PROBLEM 11 (1 point) In the FETCH phase, an instruction is transferred from memory to the PROBLEM 14 (5 points) Draw a gate level circuit (using just AND and OR gates with appropriate inverting/NOT inputs) to implement the following truth table with inputs X, Y, and Z, and outputs U and V. (The table does not necessarily represent any particular operation! It’s fine not to draw all the connection lines as long as all inputs and outputs are clearly labeled.) D out WE 1

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