pdr5 - CS 223 DIGITAL DESIGN LAB#5 Group 1 YALIN ARSLAN...

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CS 223 - DIGITAL DESIGN LAB#5 Group 1 YALÇIN ARSLAN MURAT GÜNDOĞMUŞ 21000584 21000213 18.11.2013
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b-) Behavioral Verilog Module of the FSM module cw_fsm(EN, CW, Clk, BCD, AN); input EN, CW, Clk; output reg [6:0]BCD; output reg [3:0]AN; parameter K_0 = 7'b0011100; parameter K_1 = 7'b1100010; parameter S_0 = 3, S_1 = 2, S_2 = 1, S_3 = 0, S_4 = 7, S_5 = 6, S_6 = 5, S_7 = 4; reg [2:0] State, StateNext; // CombLogic always @(State,CW) begin case (State) S_0: begin BCD <= K_0; AN <= 4'b0111; if (CW == 0) StateNext <= S_1; else StateNext <= S_7; end S_1: begin BCD <= K_0; AN <= 4'b1011; if(CW == 0) StateNext <= S_2; else StateNext <= S_0; end S_2: begin BCD <= K_0; AN <= 4'b1101; if(CW == 0) StateNext <= S_3; else StateNext <= S_1; end S_3: begin
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BCD <= K_0; AN <= 4'b1110; if(CW == 0) StateNext <= S_4; else StateNext <= S_2; end S_4: begin BCD <= K_1; AN <= 4'b1110; if(CW == 0) StateNext <= S_5; else StateNext <= S_3; end S_5: begin BCD <= K_1; AN <= 4'b1101; if(CW == 0) StateNext <= S_6; else StateNext <= S_4; end S_6: begin BCD <= K_1; AN <= 4'b1011; if(CW == 0) StateNext <= S_7; else StateNext <= S_5; end S_7: begin BCD <= K_1; AN <= 4'b0111; if(CW == 0) StateNext <= S_0; else StateNext <= S_6; end default: begin StateNext <= S_0; end endcase end // StateReg always @(posedge Clk) begin if (EN == 1 )
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  • Fall '13
  • MehmetBaray

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