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Lecture10 - The Memory Hierarchy The Memory Hierarchy Topics Topics& Storage technologies and trends& Locality of reference& Caching in

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Unformatted text preview: The Memory Hierarchy The Memory Hierarchy Topics Topics & Storage technologies and trends & Locality of reference & Caching in the memory hierarchy – 2 – Random-Access Memory (RAM) Random-Access Memory (RAM) Key features Key features & RAM is packaged as a chip. & Basic storage unit is a cell (one bit per cell). & Multiple RAM chips form a memory. Static RAM ( Static RAM ( SRAM SRAM ) & Each cell stores bit with a six-transistor circuit. & Retains value indefinitely, as long as it is kept powered. & Relatively insensitive to disturbances such as electrical noise. & Faster and more expensive than DRAM. Dynamic RAM ( Dynamic RAM ( DRAM DRAM ) & Each cell stores bit with a capacitor and transistor. & Value must be refreshed every 10-100 ms. & Sensitive to disturbances. & Slower and cheaper than SRAM. – 3 – SRAM vs DRAM Summary SRAM vs DRAM Summary Tran. Access per bit time Persist? Sensitive? Cost Applications SRAM 6 1X Yes No 100x cache memories DRAM 1 10X No Yes 1X Main memories, frame buffers – 4 – Nonvolatile Memories Nonvolatile Memories DRAM and SRAM are volatile memories DRAM and SRAM are volatile memories & Lose information if powered off. Nonvolatile memories retain value even if powered off. Nonvolatile memories retain value even if powered off. & Generic name is read-only memory ( ROM ). & Misleading because some ROMs can be read and modified. Types of ROMs Types of ROMs & Programmable ROM ( PROM ) & Eraseable programmable ROM ( EPROM ) & Electrically eraseable PROM ( EEPROM ) & Flash memory Firmware Firmware & Program stored in a ROM ¡ Boot time code, BIOS (basic input/ouput system) ¡ graphics cards, disk controllers . – 5 – Typical Bus Structure Connecting CPU and Memory Typical Bus Structure Connecting CPU and Memory A A bus bus is a collection of parallel wires that carry is a collection of parallel wires that carry address, data, and control signals. address, data, and control signals. Buses are typically shared by multiple devices. Buses are typically shared by multiple devices. main memory I/O bridge bus interface ALU register file CPU chip system bus memory bus – 6 – Memory Read Transaction (1) Memory Read Transaction (1) CPU places address A on the memory bus. CPU places address A on the memory bus. ALU register file bus interface A A x main memory I/O bridge %eax Load operation: movl A, %eax – 7 – Memory Read Transaction (2) Memory Read Transaction (2) Main memory reads A from the memory bus, Main memory reads A from the memory bus, retreives retreives word x, and places it on the bus. word x, and places it on the bus. ALU register file bus interface x A x main memory %eax I/O bridge Load operation: movl A, %eax – 8 – Memory Read Transaction (3) Memory Read Transaction (3) CPU read word x from the bus and copies it into CPU read word x from the bus and copies it into register % register % eax eax ....
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This note was uploaded on 04/13/2008 for the course CS 211 taught by Professor Chakraborty during the Spring '08 term at Rutgers.

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Lecture10 - The Memory Hierarchy The Memory Hierarchy Topics Topics& Storage technologies and trends& Locality of reference& Caching in

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