3441Lab8 - tested it with a clock signal (see attached...

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ECE 3441 Laboratory VIII: Design of a Traffic Controller Performed by Due November 30, 2007
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Introduction One goal of this lab is to design a traffic controller using flip-flops and logical gates. Another goal is to test its operation by applying a clock. Design Details In order to simulate and design a traffic light "4-way intersection" we had to first create a state diagram with 10 states as described in the instructions. Based on this information we were able to draw the input and output karnaugh maps for use of the J-K flip-flop. In order to optimize our solution, we designed the gates using multiple function output reduction in LogicAid. We then drew our circuit in SimUAid and
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Unformatted text preview: tested it with a clock signal (see attached pages for draft and timing diagram). Conclusion This lab allowed us to think of a design using the only guidelines of having a traffic intersection with the green light on for four clock cycles, yellow for one, and the red light on for five clock cycles. We learned a real application for the problems on flip-flops we have been doing on homework. We were also able to see the amount of design it takes from the maps to the hardware implementation. Another lesson learned is how to simulate with a clock cycle controlled input. SimUaid_Drawing SimUaid Simulation...
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3441Lab8 - tested it with a clock signal (see attached...

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