This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: Name sowmous ECE Box # Problem. Score Points lﬂzs M " 69.8 25 3 ~—
0’ 17"} 2 . 30
st) 3 L 16
H .
74 4 8.0 18 EE4902 C2001
Analog IC Design Exam 3 . This is a closed book test!  Show all your work. Partial credit may be given. If
you think you need something that you can't remember,
write down what you need and what you'd do if you
remembered it. . Look for the singleI straightforward way to solve
the Eroblem for the level of accuracy required. Don't get entangled in unnecessary algebra.  You may assume all op—amps to be ideal, except as
otherwise noted.  As in real life, some problems may give you more information than you need. Don't assume that
all information must be used! It's your job to decide what's relevant to the solution.  You will have 55 minutes to complete this exam. There
are four problems on a total of 11 pages. .I CIRCUIT SYMBOL ACTIVE IDVDS CHARACTERISTIC 9
l—
92
E9
[—
OE
El:
q I"
IE
0'6
gs.
2'1
b—I MQSFET LARGE SIGNAL CHARACTERISTICS N CHANNEL ID Jﬂ‘. ﬂ (Ves Vm)2[1+ 1110108  Vaﬁ )1
2 L ‘—r" 10 V05 < Veff VDS > Veff
TRIODE ACTIVE T INCREASING
V63 V68 2» th
ACTIVE 2
ID: uncox ¥[(VGsVm)V05  V?“ P CHANNEL ID=4“Pg—°" $0.03 Vm)2[1 + lawnsVeal] V03 < Veﬁ V 03 > Veﬁ 10
ACTIVE moors DECREASING
V63 V65 4. th
ACTIVE 2
ID: “pom ¥qusvlp)v:ns  V?“ 1. This problemis concerned with the op—amp circuit shown in
FiQUIe l. The op—amp is connected as a unity gain follower with a 1V DC input. For the purposes of this problem, you may
ignore channel length modulation effects and the body effect. Use the following MOSFET parameters for the AMI 1.2um process: Figure lb. 4 a) Find the DC drain current ID (accuracy i10%) for all MOSFETS ..» Use the table below to record your answers.
[12] DIFF PAIR SPLIT
OF IFD7 MIRROR 0F In: Posts: 8% I03 (SEE (a) realm) $3le ero OF M3 ﬁns 23
E FORCED BY “DIODE"CGNNEC’HOM TOMé E RATfO OF SIZES 13) Find the DC node voltages (accuracy iEOmV) for all nodes. Use the table below to record your answers.
[12] Node voltage [V] VSi:.+]V—.V651 2+1Vl.14é
w
VIN '1‘ 1:00 Vtﬁi'F—th—I
Raj": BUT‘V‘N OUT 0 2. _ i 246
— MamS 46» ~ ' VS]. “0425
 Z . 
Ves Mm: In N M 3m; «Anowsmevas c) Will this op~amp exhibit a systematic offset? V63 =Vc35 H3, H5 ARE SIZED CORRECTLY’: 0c OPERATING 901m"
AT 131* STAGE OUTPUT (v55) CAUSES laser“ [1] EXPLAIN! [5] d} What is the slew rate (accuracy i10%) for this op—amlg?
{6] Slew Rate = L33 V '5 ZOE/i : ISS
GOPF Comp 2. The small—signal model of a two stage op—amp is shown below: Vout
O
+
Vid
6
gm] = gmll = _
3E5 AN 6E—4 AN H a} Determine the open—loop DC gain A0 (accuracy i10%) : A0 = W 3M1” Roi gm: Ron:
+ 80, ng {355) (6,? rm) (6 2—4) (2 SIkJL) b) On the following page, plot the magnitude and phase Bode plots
for the open loop gain transfer function A{f)= vout/vin
[12]
J i 2 2 ”,9 kH :: : 94 k
15’” 2n(é,r7r1J2;)(2F>F) 2' {P1 2n(35kJL)(zoPF) HZ c) With feedback for a closed—loop gain of unity, will this opvamp
be stable or unstable? W . [1]
STABLE UNSTABLE EXPLAIN! H [5]
PHASL: HARGIN z o_ [6] NOTE: WHICH PART (d) YOU ANSWER DEPENDS ON YOUR ANSWER TO (C) l !!
ONLY ANSWER ONE OF THE QUESTIONS BELOW!!! d) [5]
IF YOU SAID IF YOU SAID
STABLE UNSTABLE
ll U
Determine the gainbandwidth Describe qualitatively
product fT: what design change(s) would
be necessary to stabilize
f,r = the op—amp: NEED A COMPENSATEOM
CAP ' JT‘ Ex" One problem with the simple two—stage op—amp you built in Lab 3 is the high output impedance. That's why you had to use
feedback resistors of 11452 and lOOkQ in the gain of +11
amplifier —— lower values would have loaded down the output stage, reducing open—loop gain and drawing too much current. One solution to this problem is to add a source follower buffer
at: the output stage, as shown in the rap—amp circuit below
(compensation capacitor omitted for simplicity). M9 is the
source follower transistor; M10 is a current source to prov1de
DC bias current for M9. VDD = +5V Vss = 5V a) 13) Identify the inverting and non—inverting inputs.
I 8 l Inverting : L Non~inverting: VIM]. TWO INVERS‘ONS The maximum and minimum limits on the input common mode voltage
(defined as chu = (vm1 + vaZ) and the output voltage VOUT are
determined by the condition that all MOSFETS operate in the
active region. As you may recall from lecture, lab, and
problem sets, .at each limit one transistor "crashes" into the
triode region w This part of the problem requires no numerical calculation!
For each voltage limit case below, just tell which transistor
crashing into triode determines the voltage limit. [8] Voltage Limit Condition MOSFET "crashing"
Common mode voltage, maximum (V104,) M 2—— (Mi OK)
Common mode voltage, minimum WEN) M;
Output voltage, maximum 154—:F
Output voltage, minimum __ ML
’
>l= NOT M9! Foe M9 "m CRASH INTO "mime, V69 WOULD HAVETD
EXCEED V90. BUT M5 CEASHES FHQST. '4. This problem considers two implementations of a cascode current
source, shown in Figs. 4a and 413. For the purposes of this problem. you may ignore channel length modulation effects and
the body effect. Also, assume that all P~channel devices are '_ operating in the active region; this problem is concerned with
the N—channel devices making up the cascoded current mirror. Use the following MOSFET parameters for a typical MC14007: The "traditional" cascode current source (shown in Fig. 4a) is
great for achieving very high small—signal output impedance.
'Unfortunately, the tradeoff in reduced signal range (due to the
compliance voltage limit) is severe. This can be especially troublesome in low—supply—voltage environments, such as with
the single +5V supply rail shown in Fig. 4a. VDD = +5V M4 _
I”. \f GWEN 8‘} :LGQ CRASH WHEN V03 uVQH‘
GS l av _ V
l V 1 .19. 10 10 05404;
‘70 + 3.595 Mao IOWA
= Vepp:0.ev M1 M2 ﬂ V032 3 2.3V 165:2.3V 10 NEVER CEASHES! Fig. 4a — a) For the circuit in Fig. 4a, determine the minimum limit mem
of the voltage compliance range (that is, the minimum voltage at Vow for which all MOSEETs are in the active region).
Accuracy :5 Dmv. 4 V = +2.9v ' ‘61 MINIa} 10 Ft“: The problem with the cascode current source shown in Fig. 4a is
that the gate of the cascode transistor M4 is set to a higher
voltage than it needs to be. M1 and M2 realy do need to be
connected in a mirror configuration. But the only purpose of
M3 is to set: the DC voltage at the gate of M4. We can get
'better output voltage compliance if we use the approach shown
in Fig. 4b. VDD = +5V Fig. 41:) b) For the circuit in Fig. 4b, determine the minimum possible
limit meh] of the voltage: compliance range {that is, the
minimum voltage at Vm for which all MOSFETs are in the active
region) AND the required with W5 of M5 to achieve this limit. [12]
VHINIh} = 1’7",
W5 : 4032M V031 CAN BE AS LlTTLE As 0.6V (=Veﬁc) {=04 M1 TO BE
in THE Acme REGION. THEM meswomz SINCE V052 IS DETERMINED BY VGs—Vss4 :VGSS‘VGSLI, WE HAVE NANT:O.6V . '
V635 = 0.ew— v63 .1 : 0.6V; 2.3V: +29v 12) SIZE Ms 100M: iii—ﬁlo w—S (29v— 17v) s> Ws— [40Mm l 11 ...
View
Full Document
 Fall '01
 MCNEILL

Click to edit the document details