OctalDecoder.docx - LAB 4 DATE: 14/06/2021 TIME: 11:22 AM...

LAB 4 DATE: 14/06/2021
TIME: 11:22 AM
Octal Decoder
Objective: To design and implement an Octal Decoder using when statement in
VHDL and using assign statement in Verilog.
Schematic:
Using Gates:

LAB 4 DATE: 14/06/2021
TIME: 11:22 AM
VHDL (RTL View)
Verilog (RTL View)

LAB 4 DATE: 14/06/2021
TIME: 11:22 AM
C
ode:
VHDL
Verilog

LAB 4 DATE: 14/06/2021
TIME: 11:22 AM
Output Waveform: Same for VHDL and Verilog
Pin Planner:

LAB 4 DATE: 14/06/2021
TIME: 11:22 AM
Truth Table:
X2 X1 X0 Y7 Y6 Y5 Y4 Y3