This preview shows pages 1–14. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: A3 1 20 points
There is no need to show your work for this problem — just your answers
will be graded. 2 points for each answer. When boxes are provided, put your answers in them. (a) Consider the circuit shown below. Assume that v1 has been zero since t = —<>o and
switches to +5 volts at t = O . If R1 =1 k9, find the following three values: (b) Consider the circuit shown above again. Assume that V] = 3 volts since 1‘: —<>o and
switches to —2 volts at t = 0. If R1 =1 kg and TF = 2 us, find the following three values: QF(0—) = L/, 6 PC Cé‘D:~c5.z7mA x3; 8.é)?C, croHéPQ
(c) Draw a schematic for how to construct a 2input AND gate using only 2input NOR 9 cl O‘g/éPC gates.
>
>1 13 ml A4 (d) Consider the circuit shown below. If the size of M1(i.e., the W/L) is doubled while everything else is kept the same, what happens to tpHL ? (circle the correct answer) (a) It stays the same
(b) It doubles (c) It drops in h
(d) It rops to M: its previous value (e) None of the above (e) Consider the inverter shown above again. If the size of M1(i.e., the W/L) is increased while everything else is kept the same, what happens to the static transfer characteristic
(i.e., the static plot of V0 versus V, )? (circle the correct answer) (a) It stays the same (b) It shifts slihtl to the right
(c) It shifts slightly to the 16 t '
( e va ue o the typical low output voltage decreases (e) None of the above VDD +VDD
2 100
that everything is ideal, the two transistors are perfectly matched, C L is removed, and the (f) Consider the inverter shown above with an input 121 (t) = sin wt. Assume frequency wis low enough to ignore all capacitors. What do you expect the output to be?
(circle the correct answer) (a) v0(t) zygg——Ksinwt where K <VDD/100. V
(b) v0(t)=ﬂ—Ksina)t where K >VDD/lOO. (0) v0 (t) = VDTD— Ksin wt where K = VDD /100.
((1) None of the above A5 2 10 points Draw a schematic using only NMOS and PMOS transistors for a CMOS logic
gate that implements the Boolean expression Y 2 2+ B (C +5) given the four inputs A, B,C,andD. ?: A6 3 20 points
Consider the standard CMOS inverter shown below. 10 pts (a) Derive an equation for slope of the static transfer characteristic at the midpoint
assuming that KN , K P , VthN , Vthp , 2N and JP may all be different. Make it clear how you arrive at your answer or you will not receive full credit.
Assume 4446, asﬂmmel—rv‘ is $M6kl/ l J SD 4446 \MlCLPOM‘i'
‘13 sh U Hmt‘ Viz—V :— VDD/L and bag“ (WU/‘5 ($4345 0
WE: 3LT” SocL’UPGCLCci,
The; slape : we. 33 M13 Ac. gain l_ 6 7o, l4+
S$ MB RC. ‘70 C J (U0 ’u \/ _
@MU” )7.) p 8M” 4) 2K“ "—— Hare)
3%? a 0L) op a") CV39 +V )
2 T P a “4?
_' \ i __ i ’ I __ A... l
QN— XNIDN CE {29? E? ? LD"; I”? KN<ZEE V‘H’W) A7 10 pts (b) Now assume that the circuit is perfectly symmetric and derive an approximate
equation for tpHL. Make it clear how you arrive at your answer or you will not receive full credit. U
I C W...
Z. ”
ai’ i=0+J We. imngtsico is M 5m 1 ' L
CDCO'W : K (VDD. +\,\\ _ I t . ' 1
Law = KEMMWE  w] I? Let QED A8 4 25 points
Consider the common—emitter emitter—follower cascade amplifier shown below. 5 pts (21) Draw the mjdband small—signal AC equivalent circuit. A9 5 pts (b) Derive an equation for the midband output resistance of the amplifier Make
reasonable approximations and state what they are. Make it clear how you arrive at your answer or you will not receive ﬁull credit. ED is '5an (SA “Hat, , T; 56:“ [LISTO ﬂ UHFLO Since. we Maw: :avxcﬁei (:9, H is. Mﬁklﬂ‘éel‘ ‘HAAA RQ' a» «341:0 bcaao Se Then) We. use. EM—iPtﬁAﬂU/‘Ce— Fe‘Fléchion 1'4 o “as
@m’ctd‘ ‘94: Q1 ‘4 a ‘21 5 pts (c) Derive an equation for the midband input resistance of the amplifier. Make
reasonable approximations and state what they are. Make it clear how you arrive at your answer or you will not receive full credit. {22/ 75 SonuIA c9/\ 444:, $¢KACMCCHC~ REA
l‘ﬂ‘lo ‘ll/xc bags; 9“? 321 +0 A10 10 pts (d) Derive an equation for the midband overall voltage gain of the amplifier (i.e.,
v0 /vs ). Make reasonable approximations and state what they are. Make it clear how you arrive at your answer or you will not receive full credit. 05M Faﬂcclrion) (/06, PQPM 444.: All 5 15 points Consider the common—source amplifier shown below. ,
DD 5 pts (21) Draw the hi gh—frequency small—signal AC equivalent circuit assuming the
transistor is saturated. You do not need to provide equations for the small—signal model parameters. 11 A12 10 pts (b) Derive an equation for the high—frequency input impedance of this amplifier if
C g d is ignored (i.e., remove it from the circuit). Make it clear how you arrive at your answer or you will not receive ﬁill credit. c‘
3°; A13 15 points Consider the standard TTL NAND gate below. Remember that when this gate
switches from low to high at the output, there is a large transient current spike. Briefly explain what would happen, and why, to the magnitude of this spike if the
value of R4 were reduced. What other effects would reducing R4 have on the performance of the gate? More room is available on the next page. VCC R2 R3
1.6 kg 130 Q mil: ‘ A R K ‘k be.“
Pea/loom QLt lV‘C(‘Céu‘bas LR (,J\’\Il& Q3 5 a
«War its a; 625 ms are eats» owl 5‘ HA6 Currem+ sPrlé—e, will lac. narrower, ALSO) wlaan QP T5 on (seeixfrajracm V'V‘Ofef 5? L52.
(utqu it '3 :3 Q1:— {5 $MH6J‘) 61 64:14 Paclualvxa LJTCHM 04l “Hm‘4» Spike , [Ode/F3 A14 Additional room for problem 6. L4QUf‘m,‘ £185 4150 Facets +142, \Oﬁéc ov‘acLNUC “Odo” POP C23
Wye/n 1+ rg sack; Pad‘d 1? VOL 1% 4
w wane; Cora?“ Wok CW3 / A15 7 15 points Consider the amplifier shown below. 5 pts (a) Draw the high—frequency smallsignal AC equivalent circuit. Ignore r0 but do
not ignore rb . You do not need to provide equations for the small—signal model _ parameters. Es A16 10 pts (b) Derive an equation for the upper cutoff frequency of this circuit assuming that
the Miller effect dominates. Make it clear how you arrive at your answer or you will not receive full credit. Uéo +he, 3%?wa @Faxim‘ka4 =17 U$e_+"'in MfA‘oemc); gain morass 94: AL ‘— Elijg
M 1r ——6M_‘"2C— +Lxe,’ Q‘PPI‘GXEMF‘fazt lkk$ +0 0233, ‘HAc: Mala“; Unluc, I STWLe’,’ CT is \le LUNA/L CHM ) mmk‘na,
+L\evx.\ ‘. CM :‘CMM‘Q” Ctr V Riﬂe/i“ OVPPPOXL w 441 \ ,
CH Qh C; RM: {\TrH [Fiﬁ Psalms] T2; check”; if He 5199mm, I‘s Valfwe) L150 iﬁs'f
+0 saa VP Q¢CMD< < QMMCM ...
View
Full
Document
This test prep was uploaded on 04/16/2008 for the course EEC 110A taught by Professor Spencer during the Winter '08 term at UC Davis.
 Winter '08
 Spencer

Click to edit the document details