Engin112-F07-L28-seq-state-reduce

# Engin112-F07-L28-seq-state-reduce - Engin112 Lecture 28 FSM...

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Maciej Ciesielski Department of Electrical and Computer Engineering 11/14/2007 Engin112 – Lecture 28 FSM - State Reduction

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11/14/2007 Engin 112 - Intro to ECE 2 Recap from last lecture ± Last time y Sequential circuit design » FSM representation ± Today’s lecture y State reduction in FSM
11/14/2007 Engin 112 - Intro to ECE 3 Two Flavors of FSM ± Mealy vs Moore machine

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11/14/2007 Engin 112 - Intro to ECE 4 Comparison of Sequential Circuits ± Two sequential circuits are equivalent if output sequence produced by both circuits is the same for any input sequence. ± Example of input/output sequence y State represented by by letter y State: a a b c d e f y Input: 0 1 0 1 0 1 1 y Output: 0 0 0 0 0 1 1 ± What is a good input sequence ? (for the purpose of comparing circuits) y How long should the input sequence be? y How many different input sequences can we have? ± Circuits difficult to compare by example
11/14/2007 Engin 112 - Intro to ECE 5 State Reduction ± Equivalent states y

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## This note was uploaded on 04/16/2008 for the course ENGIN 112 taught by Professor Ciesielski during the Spring '08 term at UMass (Amherst).

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Engin112-F07-L28-seq-state-reduce - Engin112 Lecture 28 FSM...

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