Engin112-F07-L12-Kmaps

# Engin112-F07-L12-Kmaps - Engin112 Lectures 12,13 Karnaugh...

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Maciej Ciesielski Department of Electrical and Computer Engineering 10/01/2007 Engin112 – Lectures 12,13 Karnaugh Maps 10/01/2007 Engin 112 - Intro to ECE 2 Recap from Chapter 2 ± Canonical forms of Boolean functions y Sum of minterms, product of maxterms ± Non-canonical form y Sum of products ± DeMorgan’s Theorem ± Boolean functions and gates y 16 binary Boolean functions with 2 variable ± Introduction to Quartus II software ± Today’s lecture – start Chapter 3 y Minimization of Boolean functions y Karnaugh maps y Incompletely specified Boolean functions

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10/01/2007 Engin 112 - Intro to ECE 3 Minimization of Logic Functions ± We have chips with millions of gates y Why care about minimizing a function? y What do a few gates matter? ± Basic logic functions replicated thousands of times y Saving one gate for a memory cell pays off ± What is the criterion for “minimization” y Should we minimize » Number of product terms? » Number of logic operations? » Number of variables (literals)? » Number of wires? » …? ± For implementation: minimize number of gates 10/01/2007 Engin 112 - Intro to ECE 4 How to Minimize Gate Count? ± Example: y F=A’BC’+AB’C’+AB’C+ABC’= Σ (2,4,5,6) ± How many gates do we need for implementation? y If AND gates have 3 inputs and OR gates have 4 inputs? y If all gates are binary (2 inputs)? ± Are there any tricks we can use? y Combine minterms: A’BC’+ABC’=BC’ AB’C’+AB’C=AB’ y F = BC’+AB’ » How many gates does F need now? ± Simplest expression: y Minimum number of terms and literals per term ± We need systematic approach to minimize expression y Answer: Karnaugh maps (K-maps)
10/01/2007 Engin 112 - Intro to ECE 5 Karnaugh Maps ± A Karnaugh map is a graphical representation of a Boolean function y Minimization is performed by visually identifying “blocks” of logic

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Engin112-F07-L12-Kmaps - Engin112 Lectures 12,13 Karnaugh...

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