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ENGIN112-F07-12-Registers, Counters and Timing

# ENGIN112-F07-12-Registers, Counters and Timing - 4 Engin112...

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1 Tilman Wolf Department of Electrical and Computer Engineering 11/29/07 ENGIN 112 – Discussions 12 Registers, Counters and Timing Engin112 – 11/29/07 2 Shift register ± Assume 1011 is stored y Apply 0, 0, 1, 0 to input

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2 Engin112 – 11/29/07 3 Serial Addition ± Compute 0101 + 0111: Engin112 – 11/29/07 4 Universal Shift Register ± What are the operations for different S 0 , S 1 ?
3 Engin112 – 11/29/07 5 Universal Shift Register ± Sequence of operations: y 1001 is loaded y shift left (input 1) y shift right (input 0) y load 0110 Engin112 – 11/29/07 6 Ripple Counter ± Draw a 3-bit ripple counter with T-flip-flops

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Unformatted text preview: 4 Engin112 – 11/29/07 7 Ripple Counter ± Assume 1011 is loaded y What happens on count? Engin112 – 11/29/07 8 Synchronous Up-Down Counter ± Assume 1011 is loaded y Count up y Count down 5 Engin112 – 11/29/07 9 Timing Analysis ± Determine the (detailed) output y Contamination delay 3ns y Propagation delay 5ns Engin112 – 11/29/07 10 Timing Analysis ± Determine the contamination and propagation delay of the circuit: 5 ns 2 ns AND 4 ns 2 ns OR 3 ns 1 ns NOT Propagation delay Contamination delay Gate type...
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ENGIN112-F07-12-Registers, Counters and Timing - 4 Engin112...

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