Engin112-F07-L36-memory

Engin112-F07-L36-memory - Engin112 Lectures 35,36 Memory...

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Maciej Ciesielski Department of Electrical and Computer Engineering 12/03/2007 Engin112 – Lectures 35,36 Memory 12/03/2007 Engin 112 - Intro to ECE 2 Recap from last lectures ± Timing in digital logic y Combinational logic y Sequential logic y Timing analysis ± Today’s lecture: Computer Memory y Random Access Memory (RAM) y Read Only Memory (ROM)
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12/03/2007 Engin 112 - Intro to ECE 3 Memories ± Where is a memory used? y Memory hierarchy (next slide) ± What are the differences between memories? y Technology: magnetic, voltage, charge, fuse y Volatility: volatile, non-volatile y Access sequence: random, sequential y Speed: access time and throughput y Access type: » Random Access Memory (RAM) » Read Only memory (ROM) ± Is memory combinatorial or sequential logic? y RAM: sequential (similar to register) y ROM: combinatorial (programmable logic) 12/03/2007 Engin 112 - Intro to ECE 4 Memory Hierarchy Control Data- path Processor regs Secondary Memory L2 Cache L1 Cache Main Memory Speed (ns): 1ns 2ns 6ns 100ns 10,000,000ns Size (MB): 0.0005 0.1 1-4 100-1000 100,000 Cost ($/MB): -- $100 $30 $1 $0.05 Technology: Regs SRAM SRAM DRAM Disk
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12/03/2007 Engin 112 - Intro to ECE 5 Random-access Memory (RAM) ± Memory terminology: y Smallest unit is “word” ( n bits wide) y Identified by “address” ± Block diagram: y k address lines » At most 2 k words storage y n data lines input and output ± What is the total memory size in bits? y Size = 2 k × n bits ± Example: y 1024-bit memory with 16-bit words y How many address lines? 12/03/2007
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This note was uploaded on 04/16/2008 for the course ENGIN 112 taught by Professor Ciesielski during the Spring '08 term at UMass (Amherst).

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Engin112-F07-L36-memory - Engin112 Lectures 35,36 Memory...

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