Engin112-F07-L34-timing

# Engin112-F07-L34-timing - Maciej Ciesielski Department of...

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Unformatted text preview: Maciej Ciesielski Department of Electrical and Computer Engineering 11/28/2007 Engin112 Lectures 33,34 Timing Analysis 11/28/2007 Engin 112 - Intro to ECE 2 Recap from last lecture Registers and counters Lab 4 review y Building FSM for your design y Verilog coding FSM (Mealy, Moore) Todays lecture y Timing in digital logic Combinational logic Sequential logic 11/28/2007 Engin 112 - Intro to ECE 3 Delay in Logic Circuits Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs y Propagation delay ( t p ) Sequential circuits require a periodic clock Goal: analyze clock circuit to determine maximum clock frequency y Requires analysis of paths from flip-flop outputs to flip-flop inputs Even after inputs change, output signal of circuit maintains original output for short time y Contamination delay ( t c ) 11/28/2007 Engin 112 - Intro to ECE 4 Gate Output Falling edge on inverter: How does output behave? y Consider the actual voltage coming out of the gate Several scenarios: Why? y Output can be seen as RC circuit Capacitance (wires, transistors inside gates, etc.) Resistance (wires, inside gates, etc.) t 0 V V dd t 0 V V dd t 0 V V dd t 0 V V dd t 0 V V dd 11/28/2007 Engin 112 - Intro to ECE 5 Delays in Combinational Logic Gates have inherent delay y RC property determines delay y Gates cannot be made arbitrarily fast Delays in gates and circuits: y Propagation delay (t p ) Delay between valid input and valid output y Contamination delay (t c ) Delay between changed input and first change on output Both delays are important characteristics for circuits y Determine maximum clock rate t 0 V V dd t c t p input changes Logic 1 Logic 0 11/28/2007 Engin 112 - Intro to ECE 6 Combinational Logic Timing Combinational logic is made from electronic circuits...
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Engin112-F07-L34-timing - Maciej Ciesielski Department of...

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