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Maciej Ciesielski
Department of Electrical and Computer Engineering
10/15/2007
Engin112 – Lecture 17
Hardware Description Languages
10/15/2007
Engin 112 - Intro to ECE
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HDL Overview
Hardware description languages (HDL) offer a way to design circuits
using text-based descriptions
HDL
describes hardware using keywords and expressions.
y
Representations for common forms
»
Logic expressions, truth tables, functions, logic gates
y
Any combinational or sequential circuit
HDLs have two objectives
y
Allow for testing using computer simulation
»
Includes syntax for timing, delays
y
Allow for synthesis
»
Synthesizable HDL
y
The two forms often differ !
y
We will use synthesizable subset
of verilog
Two primary hardware description languages
y
VHDL
y
Verilog
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10/15/2007
Engin 112 - Intro to ECE
3
Hardware Description Language - Verilog
°
Represents hardware structure and behavior
°
Logic simulation:
generates waveforms
//HDL Example 3-1
//--------------------------
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or
g3(x,e,y);
endmodule
°
Detect errors before fabrication
10/15/2007
Engin 112 - Intro to ECE
4
Verilog Keywords and Syntax
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Lines that begin with // are comments (ignored by simulation)
°
About 100 keywords in total
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Syntax allows logic to be described precisely
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Keywords are case sensitive
//
HDL Example 3-1
//
--------------------------
module
smpl_circuit(A,B,C,x,y);
input
A,B,C;
output
x,y;
wire
e;
and
g1(e,A,B);
not
g2(y, C);
or
g3(x,e,y);
endmodule