ece314_sec5_student - ECE/CS 314 Spring 2007 Section 5:...

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ECE/CS 314 Spring 2007 Section 5: Verilog 1 VERILOG Contents What Is Verilog?. .......................................................................................................................................................... 2 Modules . ....................................................................................................................................................................... 2 Combinational Logic . ................................................................................................................................................... 2 Buses, Using Modules . ................................................................................................................................................. 3 Numbers. ....................................................................................................................................................................... 3 Operators . ..................................................................................................................................................................... 4 Concatenation . .......................................................................................................................................................... 4 Bitwise NOT. ............................................................................................................................................................ 4 Bitwise AND . ........................................................................................................................................................... 5 Bitwise OR. ............................................................................................................................................................... 5 Bitwise XOR. ............................................................................................................................................................ 5 Conditional Assignments. ......................................................................................................................................... 6 Tristating with Conditional Assignments . ................................................................................................................ 6 Reduction. ................................................................................................................................................................. 6 Bitslicing. ...................................................................................................................................................................... 6 Generate Loops. ............................................................................................................................................................ 7 `define Statement. ......................................................................................................................................................... 7 Espresso Output to Combinational Logic. .................................................................................................................... 8
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This note was uploaded on 02/15/2008 for the course ECE 3140 taught by Professor Mckee/long during the Spring '07 term at Cornell University (Engineering School).

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ece314_sec5_student - ECE/CS 314 Spring 2007 Section 5:...

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