ece314_sec5_student - ECE/CS 314 Spring 2007 Section 5...

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ECE/CS 314 Spring 2007 Section 5: Verilog 1 VERILOG Contents What Is Verilog? ........................................................................................................................................................... 2 Modules ........................................................................................................................................................................ 2 Combinational Logic .................................................................................................................................................... 2 Buses, Using Modules .................................................................................................................................................. 3 Numbers ........................................................................................................................................................................ 3 Operators ...................................................................................................................................................................... 4 Concatenation ........................................................................................................................................................... 4 Bitwise NOT ............................................................................................................................................................. 4 Bitwise AND ............................................................................................................................................................ 5 Bitwise OR ................................................................................................................................................................ 5 Bitwise XOR ............................................................................................................................................................. 5 Conditional Assignments .......................................................................................................................................... 6 Tristating with Conditional Assignments ................................................................................................................. 6 Reduction .................................................................................................................................................................. 6 Bitslicing ....................................................................................................................................................................... 6 Generate Loops ............................................................................................................................................................. 7 `define Statement .......................................................................................................................................................... 7 Espresso Output to Combinational Logic ..................................................................................................................... 8 Always Blocks .............................................................................................................................................................. 9 Sequential Always Blocks ........................................................................................................................................ 9 Combinational Always Blocks ............................................................................................................................... 10 Case Statement ........................................................................................................................................................ 10 Testing ........................................................................................................................................................................ 11 Initial Blocks and Delays ........................................................................................................................................ 11 System Tasks .......................................................................................................................................................... 12 Blocking & Non-Blocking Assignments .................................................................................................................... 12 Resources .................................................................................................................................................................... 13
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ECE/CS 314 Spring 2007 Section 5: Verilog 2 What Is Verilog? Verilog is a Hardware Description Language (HDL). It is designed to look familiar to those who know C and other programming languages, and it is possible to do ordinary programming with it, but it is crucial to know that Verilog is not an ordinary programming language. Verilog is event-based : there is a notion of the current time; changes can (and usually do) happen out of the order of lines in the code A subset of Verilog is synthesizable : it is possible (and common) to automatically transform a Verilog description of a circuit into a form that can be used in fabricating an integrated circuit. Modules Modules, representing group of hardware with a specified input and output, are the building blocks of Verilog programs. module ander_empty ( input wire A, input wire B, output wire Y ); /* * C-style multiline comments are allowed. */ // So are C++-style comments. endmodule Keep one module per file, and name the file the same as the module name, appending ' .v '. The wire type represents a simple wire; other types will be discussed later. Notice the semicolon after the module parameter list, but not after endmodule . Combinational Logic assign statements represent continuously executing combinational logic. module ander ( input wire A, input wire B, output wire Y ); assign Y = A & B; endmodule assign statements execute continuously, updating the output whenever the inputs change, just like the combinational logic they represent. Notice that the assign keyword is necessary, and that a semicolon terminates the line. Beware of race conditions, especially in conditional statements that may result from combinational logic evaluating simultaneously and not in program order.
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ECE/CS 314 Spring 2007 Section 5: Verilog 3 Buses, Using Modules A bus is a group of wires. A module can be contained inside of another module. module quad_ander ( input wire [3:0] a, input wire [3:0] b, output wire [3:0] y ); // Recommended way: ander bit0 ( .A( a[0] ), .B( b[0] ), .Y( y[0] ) ); ander bit1(.A(a[1]),.B(b[1]), .Y(y[1])); // shorthand // This style uses the wire order in the module definition. // Use it only when the connection order is obvious: ander bit2 (a[2], b[2], y[2]); ander bit3(a[3], b[3], y[3]); endmodule Buses, or groups of wires, are specified by wire [MSB:LSB] . Always use MSB larger than LSB , as in the above example, to avoid confusion, since our CPU will be big-endian. We recommend using the multi-line named instantiation method (used for bit0 above) for all but the most trivial instantiations. A partial bus can be
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  • Spring '07
  • MCKEE/LONG
  • .........

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