ch8 - Chapter 8 Main Memory Chapter 8 Memory Management s...

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Chapter 8:  Main Memory Chapter 8:  Main Memory
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8.2 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Chapter 8:  Memory Management Chapter 8:  Memory Management Background Swapping  Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium
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8.3 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Objectives Objectives To provide a detailed description of various ways of  organizing memory hardware To discuss various memory-management techniques,  including paging and segmentation To provide a detailed description of the Intel Pentium, which  supports both pure segmentation and segmentation with  paging
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8.4 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Background Background Program must be brought (from disk)  into memory and placed  within a process for it to be run Main memory and registers are only storage CPU can access  directly Register access in one CPU clock (or less) Main memory can take many cycles Cache  sits between main memory and CPU registers Protection of memory required to ensure correct operation
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8.5 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Base and Limit Registers Base and Limit Registers A pair of  base  and  limit  registers define the logical address space
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8.6 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Binding of Instructions and Data to Memory Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses  can happen at three different stages Compile time :  If memory location known  a priori absolute  code  can be generated; must recompile code if starting  location changes Load time :  Must generate  relocatable code   if memory  location is not known at compile time Execution time :  Binding delayed until run time if the  process can be moved during its execution from one  memory segment to another.  Need hardware support for  address maps (e.g.,  base  and  limit   registers )
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8.7 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Multistep Processing of a User Program  Multistep Processing of a User Program 
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8.8 Silberschatz, Galvin and Gagne  © 2005 Operating System Concepts – 7 th  Edition, Feb 22, 2005 Logical vs. Physical Address Space Logical vs. Physical Address Space The concept of a logical address space that is bound to a  separate  physical address space
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