EE306 HW3_Solution

EE306 HW3_Solution - HOME WORK 3 Due Date Q1(4.11 State the...

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HOME WORK # 3 Due Date: October 29, 2007 Q1) (4.11) State the phases of the instruction cycle and briefly describe what operations occur in each phase. (a) Fetch: Get instruction from memory. Load address of next instruction in the Program Counter. (b) Decode: Find out what the instruction does. (c) Evaluate Address: Calculate address of the memory location that is needed to process the instruction (d) Fetch Operands: Get the source operands (either from memory or register file). (e) Execute: Perform the execution of the instruction. (f) Store Result: Store the result of the execution to the specified destination. Q2) (4.8) Suppose a 32-bit instruction has the following format: OPCODE DR SR1 SR2 UNUSED If there are 255 opcodes and 120 registers, and every register is available as a source or destination for every opcode, 1. What is the minimum number of bits required to represent the OPCODE ? 2 7 < 255 < 2 8 So, 8 bits 2. What is the minimum number of bits required to represent the Destination Register ( DR )? 2 6 < 120 < 2 7 So, 7 bits 3. What is the maximum number of UNUSED bits in the instruction encoding? 32 (8 + 7 + 7 + 7) = 3 bits

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Q3) If a computer has a 16-bit MAR and a 32-bit MDR: 1. How many memory locations are available in the memory of this computer? 2^16 = 65,536 locations 2. How many bits are stored at each of those locations? 32 bits 3. What is the total size of the memory (in Bytes)? 32 * 65,536 = 2,097,152 bits, so 2,097,152/8 = 262144 Bytes
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This homework help was uploaded on 04/16/2008 for the course EE 306 taught by Professor Ambler during the Fall '07 term at University of Texas.

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EE306 HW3_Solution - HOME WORK 3 Due Date Q1(4.11 State the...

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