EE306 Revision List - Registers The Instruction Set Opcodes...

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EE306 Revision List Fall 2007 Chapter 1: What is a computer? Turing Machine concept. Chapter 2: Use of binary in the computer and why. Data Types Unsigned/signed integers 2’s complement Binary/Decimal/Binary conversion Different number bases Binary arithmetic addition/subtraction Sign extension Logical Functions AND, OR, NOT, XOR ASCII Hexadecimal Chapter 3: The transistor Logic Gates NOT, OR and NOR, AND and NAND DeMorgan’s Law Combinational Circuits Decoder, Mux, Full Adder Logical Completeness The R-S Latch Gated D-Latch The Register Concept of Memory Address Space Addressability Sequential Logic Circuits Concept of State Finite State Machines State Diagram The Data Path of the LC-3 (based on Fig. 4.3) Chapter 4: Basic Components Memory Processing Unit Input/Output Control Unit Instruction Processing Instruction Cycle Changing Sequence of Execution (e.g. JMP)
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Control of the Instruction Cycle Chapter 5: The Instruction Set Architecture
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Unformatted text preview: Registers The Instruction Set Opcodes Data Types Addressing Modes Condition Codes Operate Insructions Data Movement Instructions PC-Relative Indirect Base+Offset Immediate Control Instructions Conditional Branches JMP/Trap The Data Path Revisited Instruction Cycle Chapter 6: Programming Flow Chart Chapter 7: Instructions/Labels Pseudo-Ops (Assembler Directives) .FILL .ORIG .STRINGZ .END The Assembly Process Two Pass Symbol Table Chapter 8: Input/Output Memory-Mapped Asynchronous/Synchronous Interrupt/Polling Input from Keyboard Output to Display Status Registers Data Registers Chapter 9: TRAPS and Subroutines What they are How they work -Jump to subroutine -Jump back/return R0 and R7, and the PC Chapter 10: The Stack What is it? Why? PUSH/POP Underflow Overflow Reverse Polish Notation We did not cover, and will not examine Floating Point Data Type The Programmable Logic Array (PLA) Physical Implementation of Interrupts...
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EE306 Revision List - Registers The Instruction Set Opcodes...

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