f02f - 1 CS M51A/EE M16 FINAL EXAM closed books and notes(8...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 CS M51A/EE M16 FINAL EXAM { closed books and notes { (8 problems, 180 minutes) December 13, 2002 PLEASE BE SYSTEMATIC, ORGANIZED, and NEAT: { this will be considered in the grading. Name: Problem Points Score 1 20 2 10 3 14 4 12 5 8 6 13 7 13 8 10 Total 100 2 Problem 1. (20 points) Design a sequential system which recognizes the pattern 0101011. a) 6 points] Complete the following state diagram. Each state is labeled with a sequence that it "recognizes". 1/0 0/0 1/0 0/0 start 0 01 010 1/0 1/1 0101 0/0 1/0 010101 01010 The correspondence between the state assignment and sequence that it detects is shown in the next table. State Sequence S0 start S1 0 S2 01 S3 010 S4 0101 S5 01010 S6 010101 3 b) 4 points] Encode these states using three state variables (y2 y1 y0) so that the state assignment of state Si is the radix-2 representation of i. Complete the state and transition table: PS S0 S1 S2 S3 S4 S5 S6 y2y1y0 x = 0 x = 1 x = 0 x = 1 000 001,0 000,0 001 000 Input Input Y2Y1Y0 z T2T1T0 c) 6 points] Implement the network using NAND gates and T ip- ops. Indicate the T inputs in the state table. Give minimal sum of products expressions for T inputs. Show the logic diagram of the network. 4 d) 4 points] If the propagation delays are tp = 3:5ns, tsu = 0:9ns, tNAND = 2ns, tin = 1:5ns, and tout = 2:5ns, determine the maximum clock frequency. 5 Problem 2. (10 points) Derive the state transition/output table for the implementation of the sequential system shown in the gure below. The next state and output functions are implemented by a PLA structure. The machine has one input I and one output Z . Show expressions for the ip- op inputs. Show the state transition/output table. KA I JA QA TB QB CLK Z JA = KA = TB = z= PS(QA QB ) I JA KA TB NS Z 0 1 0 1 0 1 0 1 6 Problem 3. (14 points) (a) 8 points] Design a cyclic counter with the output sequence 0 1 4 7 6 3 0 1 : : : (of period 6) using JK ip- ops and AND, OR, NOT gates as needed. Assume that the input x is always 1. Select a state assignment that is the same as the coding for the output, that is z (t) = s(t). Show the state/output table. Minimize all expressions. Show the logic diagram of the counter. State/output table: Q0 Q0 Q0 Q2 Q1 Q2 Q1 Q2 Q1 Q0 Q0 Q0 Q2 Q1 Q2 Q1 Q2 Q1 J0 = K0 = J1 = K1 = J2 = K2 = 7 (b) 6 points] Design the cyclic counter de ned in part (a) using the "one ip- op per state" approach with D ip- ops. To obtain the output, use a suitable standard combinational module - do not design a gate network! Show all connections. Show the initial state of this implementation. 8 Problem 4. (12 points) Design a hierarchical combinational network that nds the second largest of four nonnegative integers A B C D. Each integer is represented by four bits. You may use only the following module types: 4 2-input multiplexer and four-bit comparator. The single-bit output of the comparator is z . If the rst integer is larger than the second, the output is z = 1. Otherwise, z = 0. De ne rst your basic module and then design the network using your module. Indicate all inputs and connections on the modules being used. 9 Problem 5. (8 points) Implement the following systems using standard combinational modules (no gate networks allowed): Input: x 2 f0 1 2 3 4 5 6 7g, represented in binary by x = fx2 x1 x0g xi 2 f0 1g. Output: y 2 f0 1 2 3 4 5 6 7g, represented in binary by y = fy2 y1 y0g yi 2 f0 1g Function: y = (3x + 2) mod 8 10 Problem 6. (13 points) a) 8 points] Complete the following table. If an entry in the table cannot be lled properly, explain why and how to x it. Representation values are given in the decimal number system. Number Number of Signed Representation Digit-vector digits n integer x value xR X system 2's compl. 7 -35 1s' compl. 8 169 2's compl. 100100110 2's compl. 6 -33 b) 5 points] Compute z = a + 2b ; c in 2's complement for a = ;9, b = 17, and c = ;77. Perform calculations on bit-vectors representing a, b and c and show every step of your work. How many bits should z have to represent the correct result? Check your work by showing, for each step, the corresponding values in decimal number system. 11 Problem 7. (13 points) Design a sequential system speci ed by the following state transition and output table using a modulo-8 counter with parallel load as the state register, a 8-to-1 multiplexer for the CNT input and NAND gates. Assume LD = CNT'. The design must take advantage of the count and parallel mode capabilities of the counter. Show a state diagram and all your work. PS Input Input Q2Q1Q0 x = 0 x = 1 S0 000 000,0 001,0 S1 001 000,0 010,0 S2 010 000,0 011,0 S3 011 100,0 011,0 S4 100 101,0 001,0 S5 101 000,1 001,0 NS z NS z 12 Problem 8. (10 points) Design a sequential system using combinational and sequential standard modules that detects when x(t ; 7 t ; 4) < x(t ; 3 t), where four-bit input sequences are interpreted as positive integers. 13 EXTRA PAGE 14 EXTRA PAGE ...
View Full Document

This note was uploaded on 04/17/2008 for the course CS 151A taught by Professor Miloseragovich during the Fall '07 term at UCLA.

Ask a homework question - tutors are online