hmwk3 - f ( x ) the output of the gate must be negated,...

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CSM51A Homework 3 UCLA TAs: Pouya Dormiani, Gabriel Pan [email protected], [email protected] Assigned: Friday 10/12/07 Due: Friday 10/19/07 Problem 1 Using the postulates of Boolean algebra and the theorems given in the Appendix, prove that a 0 b 0 + ab + a 0 b = a 0 + b Problem 2 Using the postulates of Boolean algebra and the theorems given in the Appendix, prove that abc 0 + bc 0 d + a 0 bd = abc 0 + a 0 bd Problem 3 Show a CMOS implementation for the XOR and XNOR gates, assume that the complement of inputs are available. Do not use transmission gates in the design. Problem 4 Consider the CMOS gate shown below, A A B B C A B B A C Z A B A B C C A B A B C C Y X 1
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The goal of this exercise is to walk you through understanding what this CMOS circuit performs by decom- posing the gate, writing the Boolean expressions for certain specified nodes and constructing the corresponding tabular representation. We know that CMOS technology is complimentary which means that in order to produce
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Unformatted text preview: f ( x ) the output of the gate must be negated, i.e. f ( x ) f ( x ) ′ x Pull Up Network Pull Down Network The node connecting the pull up network to the pull down network is the o output of the gate 1. Write the the Boolean expression for the value of node X in the diagram. 2. Write the Boolean expression for the value of node Y in the diagram in terms of A,B,C,Z . 3. Fill out the following table, A B C X Z Y . . . 4. What does the circuit do? 5. Give the min-terms with m-notation with E Z ( A,B,C ), and E Y ( A,B,C ). 6. Give the max-terms with M-notation with E Z ( A,B,C ) and E Y ( A,B,C ). Problem 5 Exercise 3.6 from the book. Also compute worst case t pLH and t pHL for each gate, in addition to the equivalent cost of the circuit. 2...
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This note was uploaded on 04/17/2008 for the course CS 151A taught by Professor Miloseragovich during the Fall '07 term at UCLA.

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hmwk3 - f ( x ) the output of the gate must be negated,...

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