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midterm-sols

# midterm-sols - CS M51A EE M16 MIDTERM — closed books and...

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Unformatted text preview: CS M51A / EE M16 MIDTERM — closed books and notes — — no programmable calculators/laptops — THIS IS STRICTLY YOUR WORK: ANY FORM OF COLLABORATION WILL BE PENALIZED (6 problems, 110 minutes) November 7, 2007 Name: MIA—MM..— IDNo.:_p6_&—__°u q CS'UC/a‘e‘lu' Problem Score Problem 1. (6 points) Show a two-level NAND-NAND network which implements the switch- ing function described by the following expression: E(a, b, c) = (a’ + b’ + c’)(a’ + b')(a’ + 0’) Use algebraic transformation to obtain an expression suitable for implementation with a NAND-NAND gate network using only two NAND gates. Complemented variables are available. Show the derivation of the sum of product expression and the NAND-NAND : [one +c')(a'+lo'>(af+c/>]” , = [(4/ka + c;)/ + (4+ L!) +(«' + C'ﬂ : [ am at + ac], = [ ado + ac], = law + 65]] z [a (1563,], ,— NAND(o\/ NAND(6’, 6)) / [0’ \\ Cl _D—L ____E(«,t,c> q Problem 2. (4 points) Design a CMOS circuit which implements the following switching expression. 2: (a+b’+c)(a+d’)(c+d) Complemented variables are also available. z (a W +£><<x + JIXC 1H0- 4 Problem 3. (10 points) a) Analyze the following network and obtain minimal sum-of—products expressions for its outputs. To facilitate analysis, use mixed-logic notation. b) The propagation delays of a NAND and a NOT gate are the same: tpLH = 0.45 + 0.3L and 13ng = 0.6 + 0.25L. The input load factor of a gate input is 1. Assuming that the zl output of the network is connected to 8 external inputs, each having load factor of 1, calculate the network delays TPLH (a, 21) and TpHL(a, 21) EXTRA PAGE (9 TM Cn‘ch’ PWH” \$0”) 4 ‘9 %, fa W Paﬂr ,2 6 Problem 4. (6 points) Given E(w,x,y,z) = Zm(0,1,4,5,6,7,8,9,10,1.1,14-1,15) Identify all prime implicants and determine a minimum sum of products expression for E. I O ‘ 03 iii? a! LAW 0 V5 1‘ l 7 Problem 5. (12 points) Design a combinational network which computes the quotient q and the remainder 2 obtained by dividing the dividend at E {0,1,2,3} by the divisor d 6 {1,2,3}. Use the binary code for the inputs :1: and d and the outputs q and z. a) Show a high—level speciﬁcation of the problem: the input / output sets, and the functions. b) Show the truth table for the outputs. c) Show the canonical expressions for the outputs using the m—notation. Use the following ordering of input variables x1, x0, d1, do). [/21 3g. @ 5&1: Zm @AﬁBAC—seléﬂﬁ ,lL 51W 3: Zn ('9’. \3 In), W ,\5>db5e(-<o,q [g . ‘2 slim (”WM °'”'8“l>- 17.:o — Zm ((7 « ll“ :73 AC'SCKO'Q'g‘lg ® ﬁrmly X6 {0' ‘B-Ju‘- «mg-5m .__, Kn— (1) Obtain minimal sum of product expressions for the outputs. d0 01 11 10 Problem 6. (12 points) Design a network to convert a: E {0, ..., 9} represented in the Excess—3 code with a bit- vector x = (x3, 902, 31:1, 31:0) to y = (yg, y2, y1,yo) in 2421 code shown in the following table. -_- n—- 1 0101 0110 0111 1000 1001 1010 ‘0 H I I! I was b—I -~ 0 _ OP-‘O x] 1101 a) Derive minimal sum of products expressions for the outputs. Note that yo = (1:6. Show all your work ' ‘ Y3 X0 3’2 X0 Y1 x0 00 01 11 10 - 00 01 11 10 00 01 11 10 10 b) Implement your expressions from part a) by programming the PLA shown below. AND Array - connection made YO )7 Y2 Y3 ...
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